JP2005310841A - Circuit module body and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To integrally form a shielding layer to a multilayer wiring layer, where ultra-fine wiring patterns and high accuracy passive elements are formed at a higher density. <P>SOLUTION: A wiring layer and an insulating layer are formed in multiple layers via a peeling layer 3 on the flat principle surface of a dummy substrate 2 and a thin-film laminated circuit body 4, including a multilayer wiring layer 11 to which passive elements 20 to 22 are formed within the layer, is also formed. Under the condition that the thin-film laminated circuit body 4 be mounted to a base substrate 5 formed of the multilayer wiring substrate, a shielding layer 13, formed on the outermost layer of the multilayer wiring layer 11, is connected to the ground. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a circuit module body in which a thin film laminated circuit body formed with fine wiring and high-accuracy passive elements in a layer to achieve a high density and thinning is mounted on a base substrate, and a manufacturing method thereof.

  In recent years, various types of mobile electronic devices such as personal computers, mobile phones, video devices, and audio devices have been reduced in size, weight, functionality, functionality, and speed. Various electronic components and circuit boards provided are also reduced in size and weight or mounted in high density. In mobile electronic devices, for this purpose, a wiring layer having a fine wiring pattern is formed in multiple layers using, for example, a thin film forming technique, and a passive element such as a capacitor, a resistor or an inductor, or a functional element such as a filter is provided in the wiring layer. A multifunctional circuit module built in is being developed.

  Particularly, in the high-frequency circuit module 100 for communication functions, in order to ensure high-frequency characteristics, measures are taken for wiring pattern routing, ground pattern placement, and the like, and electromagnetic interference noise (EMI: Electromagnetic Interference from the inside and outside). ) Needs to be addressed. In the high-frequency circuit module body 100, a capacitor element 102, a resistor 103, an inductor 104, and the like are formed in a layer on a base circuit portion 101 on which a control circuit portion, a power supply circuit, a ground pattern, and the like are formed as shown in FIG. A high-frequency circuit unit 105 is laminated. In the high-frequency circuit module 100, a high-frequency signal processing LSI 106 and a chip component 107 are mounted on the uppermost layer of the high-frequency circuit unit 105.

  In the high-frequency circuit module body 100, a shield case 108 is assembled to the uppermost layer of the high-frequency circuit unit 105. The shield case 108 is formed in a box shape by, for example, a nickel-plated copper plate or a stainless plate, and covers the high-frequency circuit unit 105 to block the influence of electromagnetic interference noise.

  Incidentally, the applicant previously provided a novel thin circuit module body and a method for manufacturing the same according to Patent Document 1. Thin circuit module body can form a high-precision flat surface, has excellent heat resistance characteristics for heating treatment during thin film formation, good depth of focus during lithographic processing, and good contact alignment characteristics during masking. In addition, a silicon substrate or a glass substrate having chemical resistance is used as a dummy substrate. The thin circuit module body forms a thin film laminated circuit body having a multilayer wiring layer in which a wiring pattern and a thin film element are formed on a main surface of the dummy substrate via a peeling layer.

  The thin circuit module body is mounted on the main surface of the base substrate while the thin film laminated circuit body is peeled off from the dummy substrate via the peeling layer or inverted while being formed on the dummy substrate. Compared with the above-described circuit module body 100 in which a thin wiring module, passive elements, and the like are sequentially laminated on a base substrate, the thin circuit module body has a fine wiring pattern without being affected by substrate warpage or surface irregularities. In other words, a multilayer wiring layer in which a high-precision thin film element is formed is formed.

JP 2002-164467 A

  The above-described thin circuit module body requires a careful handling when it is mounted on a base substrate or the like by reflow soldering or the like while being peeled from the dummy substrate because the thin film laminated circuit body is formed to be extremely thin. . Therefore, the thin circuit module body can be peeled off from the dummy substrate via the peeling layer after being mounted on the base substrate with the thin film laminated circuit body formed on the dummy substrate. In this case, the thin circuit module body is formed with a layer structure in which the thin film laminated circuit body is inverted with respect to the dummy substrate. In addition, when a plurality of thin film laminated circuit bodies are formed on a dummy substrate at the same time, the thin circuit module body is positioned in a state where a plurality of base substrates are arranged, and the thin film laminated circuit body is subjected to a peeling process. become.

  As described above, the thin circuit module body is thinly formed with a thin film laminated circuit body having a multilayer wiring layer in which fine wiring patterns and high-precision thin film elements are formed, and is used for mobile electronic devices and the like. Accordingly, it is possible to reduce the size, reduce the thickness, increase the number of functions, and increase the functions. However, in mobile electronic devices and the like, even if a thin circuit module body is used, there is a limit to miniaturization and thinning by providing the shield case 108. In mobile electronic devices and the like, there is a problem that the cost of parts of the shield case 108 or the assembly process increases the cost.

  Therefore, the present invention has a thin and high-frequency characteristic by forming a fine and high-density wiring pattern, a high-precision passive element, etc. in a multilayer wiring layer and also having a shield structure against integrated electromagnetic interference noise. An object of the present invention is to provide an excellent circuit module body and a manufacturing method thereof.

  A circuit module body according to the present invention that achieves the above-described object includes a base substrate and a thin film laminated circuit body mounted on the main surface thereof. In the circuit module body, the base substrate is formed of a multilayer substrate in which a signal pattern, a power supply pattern, or a ground pattern is formed and a terminal portion is formed on the main surface. In the circuit module body, the thin film laminated circuit body is formed on a release layer formed on a planarized main surface of a dummy substrate using a silicon substrate, a glass substrate, or the like. The circuit module body includes a multilayer wiring layer in which a thin film laminated circuit body is formed by laminating a wiring layer and an insulating layer, and a passive element is formed in the layer, and a shield formed by laminating on one main surface side of the multilayer wiring layer. And a ground terminal connected to the shield layer via an interlayer wiring, and a connection terminal formed on the other main surface side of the multilayer wiring layer so as to be opposed to the shield layer and connected to the terminal portion of the base substrate. And a terminal layer.

  In the circuit module body, a thin film laminated circuit body that is peeled off from the dummy substrate via the peeling layer and mounted on the main surface of the base substrate is connected to the connecting terminal and the terminal portion facing each other with the connecting terminal layer as a bonding surface. The The circuit module body electromagnetically shields the multilayer wiring layer by the thin film laminated circuit body mounted on the base substrate having the integrally formed shield layer positioned at the uppermost layer. The circuit module body is configured such that the base substrate and the thin film multilayer circuit body are electromagnetically separated without mutual interference, and power supply and control signals are supplied from the base substrate side to the thin film multilayer circuit body side. Is called.

  Circuit modules are heated when forming wiring layers, thin-film passive elements, etc., but they have good heat resistance, depth of focus retention during lithographic processing, and good contact alignment characteristics during masking. By forming a multilayer wiring layer and thin-film passive elements on the main surface of a dummy substrate that has insulating and chemical-resistant properties, a fine wiring pattern and high-precision thin film are not affected by substrate warpage or surface irregularities. A thin film laminated circuit body having a multilayer wiring layer in which a passive element is formed is provided. In the circuit module body, the thin-film laminated circuit body that is peeled off from the dummy substrate through the peeling layer blocks the multilayer wiring layer from electromagnetic interference noise by the shield layer that is the uppermost layer when mounted on the base substrate.

  In addition, in the method of manufacturing a circuit module body according to the present invention that achieves the above-described object, a dummy substrate made of a silicon substrate or a glass substrate having a flattened main surface is used, and a peeling layer forming step and a shield layer forming step are performed. A circuit module body in which a thin film multilayer circuit body is mounted on a base substrate is manufactured by including a process, a thin film multilayer circuit body forming step, a thin film multilayer circuit body peeling step, and a thin film multilayer circuit body mounting step.

  The method for manufacturing a circuit module includes a metal film soluble in an acid or alkali solution and a protective layer formed on the metal film as a first layer on the main surface of the dummy substrate in the peeling layer forming step. A release layer is formed. In the method for manufacturing a circuit module body, a shield layer made of a metal foil layer of Cu, Ni, or Al is formed as a first layer on the release layer in the shield layer forming step. The method of manufacturing a circuit module body includes a step of forming a multi-layered insulating layer and a wiring layer on a shield layer, a step of forming a thin film passive element in the wiring layer, and a connection to the uppermost layer in the thin film laminated circuit body forming step. A thin film laminated circuit body is formed by including a step of forming a terminal layer and a step of forming an interlayer connection for connecting the shield layer and the ground connection terminal of the connection terminal. The manufacturing method of a circuit module body forms a thin film laminated circuit body by peeling a thin film laminated circuit body from a dummy substrate through a peeling layer in a thin film laminated circuit body peeling step. The method of manufacturing a circuit module body is based on a base substrate in which a signal wiring pattern, a power supply wiring pattern, a ground pattern, etc. are formed in multiple layers and a terminal portion is formed on a main surface in a thin film laminated circuit body mounting process. The thin film multilayer circuit body is mounted with the shield layer side as the uppermost layer and the connection terminal portion side as the lowermost layer, and the connection terminal portions and terminal portions facing each other are connected.

  In the method of manufacturing the circuit module body, the flattened main surface, the heat resistance characteristics for the heating process during thin film formation, the maintenance of the focal depth during the lithographic process, and the contact alignment characteristics during masking are good and insulating. Thin film laminated circuit consisting of multilayer wiring layers with fine wiring patterns and high-precision thin film elements built in without being affected by substrate warpage or surface irregularities The body is formed. In the method of manufacturing a circuit module body, a thin film laminated circuit body that is peeled off from a dummy substrate via a release layer and mounted on a base substrate is positioned at the uppermost layer, and the internal wiring layer, passive elements, etc. A shield layer that shields from is integrally formed.

  As described above in detail, according to the present invention, a thin and high-precision thin-film laminated circuit body having a multilayer wiring layer in which a fine wiring pattern and a high-precision thin-film passive element are formed, a power supply section and a signal wiring The base substrate part on which the part is formed is electromagnetically separated and mutual interference is suppressed to improve the characteristics, and a power source and a ground having a sufficient area are formed on the base substrate to form a thin film laminated circuit Necessary power supply to the body is performed. Further, according to the present invention, it is possible to form an integral shield layer that shields the internal circuit from electromagnetic interference noise on the uppermost layer of the thin film laminated circuit body. Therefore, according to the present invention, it is possible to obtain a highly accurate electronic device that is small and light and has high functionality or multiple functions. In addition, according to the present invention, the uppermost shield layer reliably blocks the internal thin film laminated circuit portion from electromagnetic interference noise, thereby improving the reliability and reducing the thickness and reducing the cost. Makes it possible to obtain

  Hereinafter, the high-frequency circuit module body 1 shown in the drawings as an embodiment of the present invention will be described in detail. The high-frequency circuit module body 1 shown in FIG. 1 has, for example, an information communication function, a storage function, and the like, and is mounted on various mobile electronic devices such as a personal computer, a cellular phone, or an audio device, or is optionally inserted or removed. The high-frequency circuit of the ultra-small communication function module body is configured. Although not described in detail, the high-frequency circuit module body 1 performs transmission / reception of information signals without performing conversion to a high-frequency transmission / reception circuit unit or intermediate frequency by a superheterodyne method in which a transmission / reception signal is once converted to an intermediate frequency. A high-frequency transmission / reception circuit unit or the like based on the direct conversion method is formed.

  As will be described in detail later, the high-frequency circuit module body 1 uses a dummy substrate 2 to form a release layer 3 on its main surface 2a, and after forming a thin film multilayer circuit body 4 on the release layer 3, a thin film The laminated circuit body 4 is manufactured by mounting on the base substrate 5 and peeling from the dummy substrate 2 through the peeling layer 3. The high-frequency circuit module body 1 constitutes a power supply system or a control system wiring section or a ground section in which the base substrate 5 supplies power, control signals, and the like to the thin film multilayer circuit body 4. The high-frequency circuit module body 1 has a structure in which the thin film laminated circuit body 4 and the base substrate 5 are electrically and electromagnetically separated, thereby suppressing mutual interference and improving characteristics and sufficiently. A power supply pattern and a ground pattern having a large area are formed on the base substrate 5 so that the circuit portion in the thin film multilayer circuit body 4 performs a stable operation.

  The base substrate 5 is an organic multilayer substrate based on glass epoxy, polyimide, polyphenylene ether, bismaletotriazine, polytetrafluoroethylene or the like generally used as a base material of a multilayer substrate, glass, alumina, ceramic, etc. An inorganic substrate or a composite material of an organic material and a ceramic material is used as a base material. The base substrate 5 is formed at a low cost by using a relatively inexpensive base material and a multilayer wiring technique that does not require much accuracy. Although details are omitted on the base substrate 5, signal wiring patterns 6, power supply wiring patterns 7, ground patterns 8, and the like are formed in multiple layers in the layer.

  A large number of terminals 9 for mounting the thin film multilayer circuit body 4 are formed on the uppermost layer 5 a of the base substrate 5. A large number of connection terminals 10 for mounting the high-frequency circuit module body 1 on an interposer or the like are formed on the lowermost layer 5b of the base substrate 5.

  The thin film multilayer circuit body 4 is a multilayer wiring layer 11 in which a high-precision wiring pattern having a fine width and pitch and a high-precision thin film passive element are formed using a thin film technique and a thick film technique to be described later in detail. Is formed. In the thin film multilayer circuit body 4, the connection terminal layer 12 is formed on the first main surface 11 a which is the lower layer side of the multilayer wiring layer 11, and the shield layer 13 is formed on the second main surface 11 b which is the upper layer side.

  As will be described in detail later, the thin film laminated circuit body 4 is laminated on the dummy substrate 2 and peeled off from the dummy substrate 2 via the peeling layer 3, but is mounted in an inverted state with respect to the base substrate 5. . In the thin film laminated circuit body 4, the connection terminal layer 12 constitutes the first layer, but the multilayer wiring layer 11 includes the first insulating layer 14, the first wiring layer 15, the second insulating layer 16, and the second wiring. The layer 17, the third insulating layer 18, and the third wiring layer 19 are stacked in this order. In the thin film multilayer circuit body 4, a capacitor element 20, a resistor element 21 and an inductor element 22 are formed in the multilayer wiring layer 11.

  The capacitor element 20 is, for example, a decoupling capacitor or a DC cut capacitor, and is formed of a tantalum oxide (TaO) film or a tantalum nitride (TaN) film by a process described in detail later. The register element 21 is, for example, a resistor for termination resistance, and is formed of a tantalum nitride film. The high-frequency circuit module body 1 can be mounted with an extremely small and high-performance passive element by forming a passive element, which has been conventionally handled by a chip component, in the multilayer wiring layer 11.

  The thin film multilayer circuit body 4 has an underfill layer 23 interposed between the uppermost layer 5a and the connection terminal layer 12 with respect to the base substrate 5, and the connection terminals 25 opposed by solder bumps 24 melted by, for example, reflow soldering. And the terminal 9 are mounted by soldering. The thin film multilayer circuit body 4 has an interlayer connection between the first wiring layer 15 and the second wiring layer 17 through a first via 26 that is appropriately formed through the second insulating layer 16, and a third insulating layer. Interlayer connection between the second wiring layer 17 and the third wiring layer 19 is performed through a second via 27 that is appropriately formed through the layer 18.

  In the thin film laminated circuit body 4, a fourth insulating layer 28 is formed between the third wiring layer 19 and the shield layer 13 to achieve electrical insulation therebetween. In the thin film multilayer circuit body 4, a ground terminal 29 formed in the third wiring layer 19 is electrically connected to the shield layer 13 through a third via 30 that penetrates the fourth insulating layer 28. In the thin film multilayer circuit body 4, the shield layer 13 is connected to the ground pattern 8 on the base substrate 5 side and the interlayer via the first via 26, the second via 27, or the third via 30 formed between the layers of the multilayer wiring layer 11. Connected.

  In the high-frequency circuit module body 1, the shield layer 13 may be formed only in a necessary portion on the thin film laminated circuit body 4. In the high-frequency circuit module body 1, for example, a large number of terminals formed in the third wiring layer 19 are exposed on the fourth insulating layer 28 where the shield layer 13 is not formed, and a semiconductor chip, LSI, or various types of terminals are exposed by these terminals. Electronic parts are mounted.

  Since the high-frequency circuit module body 1 has a structure in which the shield layer 13 is integrally formed on the uppermost layer, an electronic device on which the high-frequency circuit module body 1 is mounted is made thinner and lighter. Since the high-frequency circuit module body 1 is formed with the shield layer 13 only in a necessary portion and an LSI or the like is mounted on the uppermost layer, it is possible to achieve multi-function and high-speed processing. The high-frequency circuit module body 1 can also form a shield layer 13 having a complicated shape, and the cost is reduced by eliminating the need for a shield member and its assembly process.

  The high-frequency circuit module body 1 includes a so-called Via-on-Via structure in which a via between upper and lower wiring layers is directly formed in the multilayer wiring layer 11, for example. The connection is made with a shortened length and reduced attenuation of the transmission signal and with a minimum signal delay. In the high-frequency circuit module body 1, it is possible to mount a passive element or the like that could not be formed in the thin film laminated circuit body 4 on the uppermost layer, so that the wiring length can be shortened.

  In the high-frequency circuit module body 1, a low-speed signal circuit such as a power supply circuit, a ground, or a control signal is formed on the base substrate 5 side, and a high-speed signal circuit between LSIs is formed on the thin film laminated circuit body 4 side. . In the high-frequency circuit module body 1, the power supply circuit pattern 7 and the ground pattern 8 having a sufficient area are formed on the base substrate 5 side, so that a highly regulated power supply is performed to the thin film multilayer circuit body 4. become.

  The high-frequency circuit module body 1 configured as described above is manufactured through the manufacturing process shown in FIG. In the manufacturing process, a dummy substrate 2 made of a silicon substrate or a glass substrate whose main surface is flattened is supplied, and a release layer forming step s-1 for forming a release layer 3 on the main surface 2a, and a shield layer 13 are formed. The thin film laminated circuit body forming step s-2 for forming the thin film laminated circuit body 4 using the shield layer forming step s-20 to be formed as the first step, and the base substrate 5 manufactured by the base substrate manufacturing step t-1 are thin film laminated. A thin film laminated circuit body mounting step s-3 for mounting the circuit body 4 and a thin film laminated circuit body peeling step s-4 for separating the dummy substrate 2 and the thin film laminated circuit body 4 through the peeling layer 3 are included. .

  As shown in FIG. 3, the manufacturing process includes a shield layer forming step s-20 for forming the shield layer 13 on the release layer 3 and a fourth insulation on the shield layer 13 as shown in FIG. A fourth insulating layer forming step s-21 for forming the layer 28. The manufacturing process includes a third wiring layer forming step s-22 for forming the third wiring layer 19 on the fourth insulating layer 28, and a third insulating layer forming for forming the third insulating layer 18 on the third wiring layer 19. Step s-23 and a second wiring layer forming step s-24 for forming the second wiring layer 17 on the third insulating layer 18 are included. The manufacturing process includes a second insulating layer forming step s-25 for forming the second insulating layer 16 on the second wiring layer 17, and a first wiring layer forming for forming the first wiring layer 15 on the second insulating layer 16. Step s-26, a first insulating layer forming step s-27 for forming the first insulating layer 14 on the first wiring layer 15, and a connecting terminal layer forming step s-28 for forming the connecting terminal layer 12 are included.

  In the manufacturing process, a via forming process for forming the third via 30 is performed in the fourth insulating layer forming process s-21. In the manufacturing process, a terminal forming process for forming the ground terminal 29 together with the third wiring layer 19 is performed in the third wiring layer forming process s-22. In the manufacturing process, a passive element forming process for forming the capacitor element 20, the register element 21, and the inductor element 22 in the second wiring layer 17 is performed in the second wiring layer forming process s-24. In the manufacturing process, a via forming process is appropriately performed in each wiring layer forming process and insulating layer forming process. In the manufacturing process, in the first wiring layer forming step s-26, a terminal forming step for forming the connection terminal 25 together with the first wiring layer 15 is performed to configure the connection terminal layer 12.

  In the peeling layer forming step s-1, peeling is performed on the main surface 2a of the dummy substrate 2 made of a silicon substrate or a glass substrate, which is excellent in heat resistance and chemical resistance and capable of forming a highly accurate flat surface. Layer 3 is formed over the entire surface. As shown in FIG. 4, the release layer 3 is formed on the first metal film 31 formed on the first metal film 31 by, for example, sputtering or chemical vapor deposition (CVD). A second metal film 32 and an insulating resin film 33 covering the second metal film 32.

  In the peeling layer 3, the first metal film 31 is formed of a metal film such as titanium, titanium nitride, or chromium having a film thickness of about 200 to 500 mm, and the second metal film 32 has a film thickness of about 1000 to 3000 mm. It is formed by a copper or aluminum metal film. For the release layer 3, for example, a polyimide resin is applied to the insulating resin film 33 on the second metal film 32, and uniformity and thickness controllability are maintained. For example, a spin coating method, a curtain coating method, a roll coating method, a dip coating method, or the like. Is formed with a film thickness of about 1 μm to 3 μm. The release layer 3 has a function of improving the adhesion between the first metal film 31 and the dummy substrate 2 and a function of peeling the thin film laminated circuit body 4 from the dummy substrate 2 as described later. Play. The release layer 3 functions as a protective film that protects the thin film multilayer circuit body 4 from a chemical solution during the peeling process of the insulating resin film 33.

  In the thin film multilayer circuit body forming step s-2, since the thin film multilayer circuit body 4 formed on the dummy substrate 2 is mounted on the uppermost layer 5a of the base substrate 5 in an inverted state, the shield layer formation is performed as described above. Step s-20 is the first step, and the shield layer 13 is formed on the release layer 3 as shown in FIG. In the shield layer forming step s-20, for example, a metal foil 34 such as copper or nickel is bonded with an adhesive 35.

  Although the thickness of the shield layer 13 varies depending on the frequency band that requires the shielding effect of the high-frequency circuit module body 1, a metal foil 34 having a thickness of approximately 10 μm to several tens of μm is used. Further, when the required thickness specification is small, for example, a copper film or a nickel film may be directly formed by the electroless plating method or the like. As described above, the shield layer 13 may be formed not only on the entire surface of the release layer 3 but also partially on a necessary portion.

  In the fourth insulating layer forming step s-21, as shown in FIG. 6, the fourth insulating layer 28 is formed on the shield layer 13, and the third via 30 is appropriately formed in the fourth insulating layer 28. It is. The fourth insulating layer 28 is formed of a dielectric insulating material having a low dielectric constant, low loss, excellent high frequency characteristics, and excellent heat resistance and chemical resistance. The fourth insulating layer 28 is made of, for example, polyimide, benzocyclobutene (BCB), polynorbornene (PNB), liquid crystal polymer (LCP), epoxy resin, or acrylic resin. The fourth insulating layer 28 is formed to a thickness of 50 μm to 100 μm in order to ensure high frequency characteristics of the thin film capacitor element 20, the thin film resistor element 21, and the thin film inductor element 22.

  In the fourth insulating layer forming step s-21, when a photosensitive dielectric insulating material is used, a uniform dielectric insulating film is formed on the shield layer 13 by, for example, a spin coating method and patterned by photolithography processing. Then, the via hole 30a is formed so that the shield layer 13 faces the upper layer. In the fourth insulating layer forming step s-21, when a non-photosensitive dielectric insulating material is used, a reactive etching process or a dry etching process such as laser irradiation is performed on the dielectric insulating film formed on the shield layer 13. To form a via hole 30a.

  In the fourth insulating layer forming step s-21, for example, electrolytic copper plating is performed in the via hole 30a formed in the fourth insulating layer 28 by the above-described step to form a copper plated layer 30b as shown in FIG. Thus, the third via 30 is formed. The third via 30 is formed by energizing the shield layer 3 exposed to the surface through the via hole 30a as a seed metal, so that the fourth insulating layer 28 functions as a resist for electrolytic plating. Then, the copper plating layer 30b grows.

  In the step of forming the third via 30, the plating control is performed so that the copper plating layer 30 b has a plating thickness that is equal to or slightly smaller than the film thickness of the fourth insulating layer 28. In the manufacturing process, by performing such plating control, the step of polishing the copper plating layer 30b raised from the via hole 30a is omitted, and the third via 30 can be formed simultaneously with the third wiring layer 19 described later. It becomes possible.

  In the third wiring layer forming step s-22, the third wiring layer 19 having a predetermined thickness is formed by electrolytic copper plating on the fourth insulating layer 28 in which the third via 30 is formed. In the forming step, as shown in FIG. 8, a seed metal layer 36 is formed on the entire surface of the fourth insulating layer 28 by sputtering or the like, and a plating resist layer 37 is formed on the seed metal layer 36 by a photoresist method. Patterning is formed. For example, the seed metal layer 36 has a two-layer structure of a titanium layer with a film thickness of about 200 to 3000 mm and a copper layer with a film thickness of about 1000 to 3000 mm, thereby achieving a seed metal function when performing an electrolytic copper plating process. Further, since the unnecessary portion is removed after the electrolytic copper plating process as will be described later, the seed metal layer 36 only needs to have a thickness sufficient to perform the seed metal function of the electrolytic copper plating process, and is formed as thin as possible. The

  In the third wiring layer formation step s-22, the copper plating layer 38 is formed in the opening 37a of the plating resist layer 37 as shown in FIG. Is done. In the third wiring layer formation step s-22, the copper plating layer 38 is formed to a thickness sufficient to ensure sufficient electrical characteristics as the third wiring layer 19, and is formed to a thickness of, for example, about 5 μm.

  In the third wiring layer forming step s-22, when the predetermined electrolytic copper plating process is finished, a process of removing the plating resist layer 37 is performed as shown in FIG. The plating resist layer removing process is performed by, for example, a kind of wet etching method in which the plating resist is dissolved by immersion in acetone or a resist stripping solution, or a dry etching method by oxygen plasma processing or the like. In the third wiring layer forming step s-22, as described above, the seed metal layer 36 is formed on the bottom of the plating resist layer 37, and by removing the resist layer 37, the unnecessary portion exposed from the opening is unnecessary. By removing the seed metal layer 36, the third wiring layer 19 is formed on the fourth insulating layer 28. The unnecessary seed metal layer 36 is removed by wet etching, for example, a copper layer is removed by a mixed solution of nitric acid, acetic acid and sulfuric acid, and a titanium layer is removed by a dilute hydrofluoric acid aqueous solution.

  In the third wiring layer forming step s-22, the electrolytic copper plating process for forming the copper plating layer 30b of the third via 30 formed in the fourth insulating layer 28 is omitted, and the third wiring layer 19 is omitted. You may make it perform the process which forms the copper plating layer 30b simultaneously with the electrolytic copper plating process which forms. In the electrolytic copper plating process, the plating conditions are set so that the third wiring layer 19 is formed with a predetermined thickness in this case.

  In the third insulating layer forming step s-23, the same process as the above-described fourth insulating layer forming step s-21 is performed using the same dielectric insulating material as that shown in FIG. As shown, a third insulating layer 18 having a predetermined thickness is formed. Also in the third insulating layer forming step s-23, the via hole 27a constituting the second via 27 is formed at a predetermined position in the third insulating layer 18 formed with a predetermined thickness. In the third insulating layer forming step s-23, when the third insulating layer 18 is formed to a thickness of 10 μm to 30 μm, the via hole 27a has a diameter of 10 μm to 50 μm by, for example, dry etching using reactive ion etching or laser irradiation. It is possible to form with.

  A second wiring layer 16 is formed on the third insulating layer 18 and a passive element is formed in the second wiring layer 16. A process of forming the capacitor element 20 and the register element 21 will be described with reference to FIGS. The passive element forming step includes a receiving electrode step of forming the receiving electrode 20a of each capacitor element 20 and the receiving electrode 21a of the resistor element 21 at predetermined positions on the third insulating layer 18, and a dielectric on the receiving electrodes 20a and 21a. A dielectric layer forming step for forming the layer 20b and a resistor forming step for forming the resistor 21b.

  In the receiving electrode forming step, a titanium layer and a copper layer are formed on the third insulating layer 18 by a sputtering method, and a photoresist is formed by a spin coating method or the like and patterned into a predetermined pattern by a photolithography process. The receiving electrodes 20a and 21a are formed as shown in FIG. 12 with a step and a step of etching the titanium layer and the copper layer into a predetermined pattern by a wet etching method. The sputtering method removes the copper layer with a mixed solution of nitric acid, acetic acid and sulfuric acid by setting the titanium layer to a thickness of 500 to 2000 mm and the copper layer to a thickness of about 1000 to 3000 mm, similarly to the seed metal layer 36. At the same time, the titanium layer can be removed with a dilute hydrofluoric acid aqueous solution. The photoresist is removed by, for example, a wet etching method in which the plating resist layer 37 is immersed and dissolved in acetone or a resist stripping solution, or a dry etching method such as an oxygen plasma treatment.

  In the resistor forming step, after the receiving electrode 21a is formed by the above-described receiving electrode forming step, for example, a resistor material such as tantalum, tantalum nitride, nickel chrome, etc. is formed by sputtering, and a photoresist is spin-coated. Forming a film by a method or the like and patterning by a photolithographic process. The resistor forming step includes an anodic oxidation step in which the resistor material film is applied as an anode in an electrolytic solution such as ammonium borate, and a step of removing unnecessary resistor material films by an etching method. Then, the resistor 21b is formed.

  In the anodic oxidation step, a tantalum oxide layer 20c is formed as shown in FIG. 13 by applying an electric field of 100 V to 200 V to tantalum or tantalum nitride for 10 minutes to 60 minutes. Tantalum and tantalum nitride are patterned by forming a photoresist by spin coating or the like, and selectively leaving the photoresist only in the portion where the tantalum oxide layer is formed by photolithography. A predetermined pattern is formed by a dry etching method using tetrafluoromethane and oxygen plasma. In the thin film passive element forming step, the capacitor element 20 and the resistor element 21 are formed in the same layer, so that the sputtering process can be reduced by using the same electrode material.

  In the second wiring layer forming step s-24, the second wiring layer 17 having a predetermined wiring pattern is formed on the third insulating layer 18, the capacitor element 20 and the register element 21 formed on the third insulating layer 18. Is a step of forming. The second wiring layer forming step s-24 includes substantially the same steps as the above-described third wiring layer forming step s-22, and includes a step of forming a seed metal layer by a sputtering method and a step of forming a plating resist layer. , Applying a photolithographic process to the plating resist layer to remove the unnecessary plating resist layer and performing a predetermined patterning, and performing an electrolytic copper plating process to form a copper plating layer having a predetermined thickness in the resist opening The second wiring layer 17 is formed as shown in FIG. 14 through a step of removing an unnecessary plating resist, a step of removing an unnecessary seed metal layer, and the like.

  In the second wiring layer formation step s-24, a copper plating layer is formed in the via hole 27a by electrolytic copper plating, and the second via 27 that interconnects the third wiring layer 19 and the second wiring layer 17 is simultaneously formed. It is formed. In the second wiring layer forming step s-24, the spiral inductor element 22 is simultaneously formed as shown in FIG. 14 by the sputtering method and the electrolytic copper plating process for forming the second wiring layer 17. In the second wiring layer forming step s-24, the electrolytic copper plating process is controlled so that the second wiring layer 17 is formed with a thickness of about 5 μm, which is equivalent to the third wiring layer 19.

  In the second insulating layer forming step s-25, as shown in FIG. 15, the second insulating layer 16 is formed on the second wiring layer 17, and the first via 26 is formed at a predetermined position of the second insulating layer 16. This is a step of forming the via hole 26a to be formed. Also in the second insulating layer forming step s-25, the second insulating layer 16 is formed by the same process using the same dielectric insulating material as the fourth insulating layer forming step s-21 and the third insulating layer forming step s-23. Form. In the second insulating layer forming step s-25, the second insulating layer 16 is patterned to form the via hole 26a. The capacitor element 20 and the register element formed in the second wiring layer 17 described above. A via hole 26a is formed by exposing the upper portion of 21.

  The first wiring layer forming step s-26 is a step of forming the first wiring layer 15 on the second insulating layer 16. Similarly to the second wiring layer forming step s-24, the first wiring layer forming step s-26 includes a step of forming a seed metal layer over the entire surface by sputtering on the second insulating layer 16, and plating. A step of forming a resist layer, a step of performing a photolithographic process on the plating resist layer to remove an unnecessary plating resist layer and performing a predetermined patterning, and a step of performing an electrolytic copper plating process to form a predetermined opening in the resist opening. The first wiring layer 15 shown in FIG. 16 is formed by a step of forming a copper plating layer having a thickness, a step of removing an unnecessary plating resist, a step of removing an unnecessary seed metal layer, and the like.

  In the first wiring layer forming step s-26, the spiral type inductor element 22 is simultaneously formed by sputtering and electrolytic copper plating as necessary. Further, in the first wiring layer forming step s-26, a copper plating layer 26b is formed in the via hole 26a formed in the second insulating layer 16, and the first wiring layer 15 and the second wiring layer 17 are connected to each other between the layers. The first via 26 is formed. Similarly, in the first wiring layer forming step s-26, the copper plated layer 26b is also formed in the via hole 26a exposing the capacitor element 20 and the register element 21 to form the upper electrode, whereby the capacitor element 20 is formed. .

  Note that the capacitor element 20 can obtain a desired capacitor capacity by appropriately changing the shape of the via forming the upper electrode. In the first wiring layer forming step s-26, the capacitor element 20 and the register element 21 are formed in the first wiring layer 15 by performing the above-described passive element forming step in advance.

  In the thin film multilayer circuit body formation step s-2, an intermediate body 41 is formed by forming the thin film multilayer circuit body 4 having a multilayer structure on the main surface 2a of the dummy substrate 2 via the release layer 3 through the above-described steps. Produced. In the thin film multilayer circuit body forming step s-2, the thin film multilayer circuit body 4 is subjected to the above-described steps, and the multilayer wiring having the three-layer wiring structure including the first wiring layer 15, the second wiring layer 17, and the third wiring layer 19 is performed. Although the layer 11 is formed, the multilayer wiring layer 11 can be further multilayered by repeating the wiring layer forming step and the insulating layer forming step. In the thin film multilayer circuit body forming step s-2, the thin film multilayer circuit body 4 is laminated on the dummy substrate 2 having the flattened main surface 2a, so that a highly accurate multilayer wiring layer 11 can be formed. Is possible.

  In the thin film laminated circuit body 4, the connection terminal layer 12 for mounting on the base substrate 5 is formed on the first wiring layer 15 by the connection terminal layer forming step s-28. The connecting terminal layer forming step s-28 includes a step of forming a solder resist layer 39 that covers the entire surface of the first wiring layer 15 by spin coating or the like, and a photolithography process for the solder resist layer 39. Forming an opening 40 for exposing the first wiring layer 15. Further, the connection terminal layer formation step s-28 includes a surface treatment step for the exposed portion of the first wiring layer 15 and a solder bump attachment step.

  In the thin film laminated circuit body 4, as shown in FIG. 17, an opening 40 is formed in the solder resist layer 39 covering the first wiring layer 15 by a predetermined patterning. The thin film multilayer circuit body 4 is applied to the copper plating layer of the first wiring layer 15 exposed to the outside through the opening 40 by performing a surface treatment such as electrolytic plating or electroless plating. Thus, a gold-nickel layer that improves solderability is formed. For the surface treatment, for example, a solder coat layer or a water-soluble heat-resistant flux layer may be formed on the copper plating layer of the first wiring layer 15.

  In the thin film laminated circuit body 4, the copper plating layer of the first wiring layer 15 subjected to the surface treatment functions as an inspection terminal. In the thin film laminated circuit body 4, the operation characteristics and the like of the multilayer wiring layer 11 are inspected in the state formed on the dummy substrate 2. In the thin film multilayer circuit body 4, continuity inspection such as so-called open / short check is performed before mounting the base substrate 5, so that only non-defective products are supplied to the next process, thereby reducing man-hours and member costs. It is possible to plan.

  In the thin film laminated circuit body 4, solder bumps 24 are respectively formed in the openings 40 as shown in FIG. The solder bumps 24 are bonded to the internal first wiring layer 15 by forming a solder brazing by a printing method or a plating method, or by arranging a solder ball in the opening 40 and performing a reflow process.

  In the manufacturing process of the high-frequency circuit module body 1, the base substrate manufacturing process t-1 is performed by the thin film multilayer circuit body mounting process s-3 in the state of the intermediate body 41 in which the thin film multilayer circuit body 4 is formed on the dummy substrate 2. It is mounted on the base substrate 5 manufactured by the above. The base substrate manufacturing process t-1 includes a well-known multilayer wiring board forming process, and therefore the details thereof are omitted, but a multilayer wiring layer is formed on an organic multilayer board, an inorganic board, or a composite board.

  In the thin film laminated circuit body mounting step s-3, the intermediate body 41 positions and combines the thin film laminated circuit body 4 formed on the dummy substrate 2 with respect to the base substrate 5, and the thin film laminated circuit with respect to the base substrate 5 And fixing the body 4 electrically and mechanically. In the thin film laminated circuit body mounting step s-3, the intermediate body 41 is inverted so that the dummy substrate 2 faces upward, and the thin film laminated circuit body 4 has the respective solder bumps 24 formed on the uppermost layer 5a. Are positioned and combined so as to correspond to each other. In the thin film multilayer circuit body mounting step s-3, as shown in FIG. 19, a thin film multilayer circuit is formed by an underfill layer 23 formed by filling an underfill material between the base substrate 5 and the thin film multilayer circuit body 4. The intermediate body 41 is temporarily fixed via the body 4.

  In the thin film multilayer circuit body mounting step s-3, the solder bumps 24 are melted by performing reflow soldering, and the connection terminals 25 on the thin film multilayer circuit body 4 side and the terminals 9 on the base substrate 5 side are soldered. The In the thin film multilayer circuit body mounting step s-3, the multilayer wiring layer 11 on the thin film multilayer circuit body 4 side and the wiring layer in the base substrate 5 are thereby connected, and the multilayer wiring layer 11 is connected via the intra-layer wiring. Thus, the shield layer 13 connected to the connection terminal 25 is electrically connected to the ground pattern 8 on the base substrate 5 side.

  The thin film multilayer circuit body mounting step s-3 is not limited to the above-described reflow soldering process for melting the solder bumps 24, but also includes a flip chip bonding method in which the intermediate body 41 is used as a semiconductor chip mounting method, such as TAB (Tape The thin film laminated circuit body 4 may be mounted on the base substrate 5 by a face-down mounting method such as an automated bonding method or a beam lead bonding method. In this case, the thin film laminated circuit body 4 is constituted by a terminal structure in which the connection terminal layer 12 is adapted to each mounting method.

  In the thin film multilayer circuit body mounting step s-3, the intermediate body 41 is mounted on the base substrate 5 while being formed on the dummy substrate 2 as described above. Therefore, in the thin film multilayer circuit body mounting step s-3, the intermediate body 41 can be handled as a rigid body by having the dummy substrate 2, and there are inconveniences such as simplification of the handling process and cutting of the multilayer wiring layer 11 by bending. Is also avoided. The intermediate body 41 and the base substrate 5 are each provided with appropriate positioning means for positioning and mounting.

  In the manufacturing process of the high-frequency circuit module body 1, the intermediate body 41 separates the dummy substrate 2 and the thin film multilayer circuit body 4 via the release layer 3 as shown in FIG. Thus, the high-frequency circuit module body 1 is completed. In the thin film laminated circuit body peeling step s-4, the dummy substrate 2 and the thin film laminated circuit body 4 are separated from the peeling layer 3 and the shield layer 13 by immersing the base substrate 5 on which the intermediate body 41 is mounted in an acid solution or an alkaline solution. And a step of removing the insulating resin layer 33 of the release layer 3 remaining on the shield layer 13 side.

  In the thin film laminated circuit body peeling step s-4, when the peeling layer 3 is formed of the copper layer as described above, the peeling layer 3 is immersed in, for example, a diluted hydrochloric acid solution, and the second metal film 32 is made of aluminum. When formed by a layer, for example, it is immersed in a sodium hydroxide solution. The release layer 3 is slightly etched by the solution with respect to the second metal film 32, causing a release phenomenon between the second metal film 32 and the insulating resin layer 33, and the dummy substrate 2 and the thin film laminated circuit body 4. And are separated.

  In the thin film laminated circuit body peeling step s-4, the high-frequency circuit module body 1 is completed by removing the insulating resin layer 33 remaining on the surface of the shield layer 13 by a dry etching process such as oxygen plasma. The dummy substrate 2 is collected after the thin film laminated circuit body 4 is peeled off and supplied to the next manufacturing process of the high frequency circuit module body.

  In the high-frequency circuit module body 1, the multilayer wiring layer 11 is formed on the dummy substrate 2 with the shield layer 13 as the first layer via the release layer 3, but the multilayer is formed with the first insulating layer 14 as the first layer. The wiring layer 11 may be formed. In this case, the high-frequency circuit module body 1 is mounted on the base substrate 5 by performing a thin film multilayer circuit body peeling step prior to the thin film multilayer circuit body mounting step. In the high-frequency circuit module body 1, the configuration of the thin film laminated circuit body 4 and the base substrate 5 is substantially the same. For example, solder bumps 24 are provided on the base substrate 5 side.

It is a longitudinal cross-sectional view of the high frequency circuit module body shown as embodiment of this invention. It is a manufacturing process figure of a high frequency circuit module body. It is a manufacturing-process figure of a thin film laminated circuit body. It is a longitudinal cross-sectional view of the dummy substrate in which the peeling layer was formed. It is a longitudinal cross-sectional view of the intermediate body in which the shield layer was formed. It is a longitudinal cross-sectional view of the intermediate body in which the 4th insulating layer was formed. It is a longitudinal cross-sectional view of the intermediate body which formed the 3rd via | veer. It is a longitudinal cross-sectional view of the intermediate body in which the plating resist layer which forms a 3rd wiring layer was formed. It is a longitudinal cross-sectional view of the intermediate body in which the copper plating layer which forms a 3rd wiring layer was formed. It is a longitudinal cross-sectional view of the intermediate body in which the 3rd wiring layer was formed. It is a longitudinal cross-sectional view of the intermediate body in which the 3rd insulating layer was formed. It is a longitudinal cross-sectional view of the intermediate body which formed the receiving electrode of the passive element in the 3rd insulating layer. It is a longitudinal cross-sectional view of the intermediate body which formed the passive element. It is a longitudinal cross-sectional view of the intermediate body in which the 2nd wiring layer was formed. It is a longitudinal cross-sectional view of the intermediate body in which the 3rd insulating layer was formed. It is a longitudinal cross-sectional view of the intermediate body in which the 1st wiring layer was formed. It is a longitudinal cross-sectional view of the intermediate body which formed the soldering resist layer on the 1st wiring layer. It is a longitudinal cross-sectional view of the intermediate body in which the external terminal layer was formed. It is a longitudinal cross-sectional view of the intermediate body mounted in the base substrate. It is a longitudinal cross-sectional view of the intermediate body which separated the thin film laminated circuit body and the dummy board | substrate. It is a principal part longitudinal cross-sectional view of the conventional high frequency circuit module body.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 High frequency circuit module body, 2 Dummy board, 3 Release layer, 4 Thin film laminated circuit body, 5 Base board, 6 Signal wiring pattern, 7 Power supply wiring pattern, 8 Ground pattern, 9 Terminal, 10 Connection terminal, 11 Multilayer wiring layer, DESCRIPTION OF SYMBOLS 12 Connection terminal layer, 13 Shield layer, 14 1st insulating layer, 15 1st wiring layer, 16 2nd insulating layer, 17 2nd wiring layer, 18 3rd insulating layer, 19 3rd wiring layer, 20 Capacitor element, 21 Register element, 22 Inductor element, 23 Underfill layer, 24 Solder bump, 25 Connection terminal, 26 First via, 27 Second via, 28 Fourth insulating layer, 30 Third via, 41 Intermediate

Claims (6)

A base substrate on which a signal pattern, a power supply pattern, or a ground pattern is formed and a terminal portion is formed on the main surface;
Using a dummy substrate made of a silicon substrate or glass substrate having a flattened main surface, a wiring layer and an insulating layer are formed in a multilayer on the release layer formed on the main surface, and a passive element is formed in the layer. A multilayer wiring layer in which the multilayer wiring layer is formed, a shield layer laminated on one main surface side of the multilayer wiring layer, and the base substrate formed on the other main surface side of the multilayer wiring layer so as to face the shield layer. A connection terminal layer connected to the terminal portion and a thin film laminated circuit body formed with a connection terminal layer having a ground terminal connected to the shield layer via an interlayer wiring,
The thin film laminated circuit body that is peeled from the dummy substrate through the peeling layer is mounted on the base substrate by connecting the connecting terminal and the terminal portion with the connecting terminal layer as a bonding surface. The circuit module body is characterized in that the integrally formed shield layer constitutes the uppermost layer and shields the multilayer wiring layer.   The circuit module body according to claim 1, wherein the shield layer is formed of a metal foil layer of Cu, Ni, or Al.   An organic multilayer substrate based on glass epoxy, polyimide, polyphenylene ether, bismaletotriazine or polytetrafluoroethylene, a ceramic multilayer substrate based on alumina or glass ceramic, or an organic material and a ceramic material. The circuit module body according to claim 1, wherein a multilayer substrate based on the composite material is used. A dummy substrate made of a silicon substrate or glass substrate with a flattened main surface is used,
A peeling layer forming step of forming a peeling layer formed on the main surface of the dummy substrate and comprising a metal film soluble in an acid or alkali solution and a protective layer formed on the metal film;
A shield layer forming step of forming a shield layer made of a metal foil layer of Cu, Ni, or Al as the first layer on the release layer;
Forming a multilayer insulating layer and a wiring layer on the shield layer; forming a thin-film passive element in the wiring layer; forming a connection terminal layer on the uppermost layer; and connecting the shield layer and the connection Forming a thin film multilayer circuit body having a step of forming an interlayer connection portion for connecting the ground connection terminal of the terminal portion; and
A thin film laminated circuit body peeling step of peeling the thin film laminated circuit body from the dummy substrate via the peeling layer;
With respect to the base substrate on which the signal pattern, the power supply pattern, or the ground pattern is formed and the terminal portion is formed on the main surface, the thin film laminated circuit body has the shield layer side as the uppermost layer and the connection terminal portion. A thin film laminated circuit body mounting step in which the side is the bottom layer and the connection terminal portion and the terminal portion facing each other are connected and mounted,
The ground terminal of the connection terminal portion is connected to the ground terminal of the connection portion, and the multilayer wiring layer of the thin film multilayer circuit body mounted on the base substrate is covered with a shield layer integrally formed on the uppermost layer. A method of manufacturing a circuit module body, comprising manufacturing a circuit module body.   5. The method of manufacturing a circuit module body according to claim 4, wherein the base substrate is an organic multilayer substrate, a ceramic multilayer substrate, or a multilayer substrate based on a composite material of an organic material and a ceramic material.   6. The method of manufacturing a circuit module body according to claim 5, wherein the thin film multilayer circuit body peeling step is performed in a pre-process or a post-process of the thin film multilayer circuit body mounting step.

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