KR20150130516A - 비아와 커패시터의 플레이트 사이에 유전체를 갖는 커패시터 - Google Patents

비아와 커패시터의 플레이트 사이에 유전체를 갖는 커패시터 Download PDF

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Publication number
KR20150130516A
KR20150130516A KR1020157029145A KR20157029145A KR20150130516A KR 20150130516 A KR20150130516 A KR 20150130516A KR 1020157029145 A KR1020157029145 A KR 1020157029145A KR 20157029145 A KR20157029145 A KR 20157029145A KR 20150130516 A KR20150130516 A KR 20150130516A
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KR
South Korea
Prior art keywords
capacitor
substrate
plate
dielectric
vias
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1020157029145A
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English (en)
Korean (ko)
Inventor
제-흐시웅 란
청지에 주오
창한 윤
데이비드 에프. 버디
데릭 디. 김
로버트 피. 미쿨라
마리오 프란시스코 벨레즈
종해 김
Original Assignee
퀄컴 인코포레이티드
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Application filed by 퀄컴 인코포레이티드 filed Critical 퀄컴 인코포레이티드
Publication of KR20150130516A publication Critical patent/KR20150130516A/ko
Abandoned legal-status Critical Current

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    • H01L28/40—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • G06F17/5068—
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H01L23/15—
    • H01L23/49822—
    • H01L23/49827—
    • H01L27/016—
    • H01L27/12—
    • H01L28/10—
    • H01L28/60—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/20—Inductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/80—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors
    • H10D86/85—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple passive components, e.g. resistors, capacitors or inductors characterised by only passive components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
  • Ceramic Capacitors (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Semiconductor Memories (AREA)
KR1020157029145A 2013-03-15 2014-03-12 비아와 커패시터의 플레이트 사이에 유전체를 갖는 커패시터 Abandoned KR20150130516A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/833,632 US9935166B2 (en) 2013-03-15 2013-03-15 Capacitor with a dielectric between a via and a plate of the capacitor
US13/833,632 2013-03-15
PCT/US2014/024118 WO2014150747A1 (en) 2013-03-15 2014-03-12 Capacitor with a dielectric between a via and a plate of the capacitor

Publications (1)

Publication Number Publication Date
KR20150130516A true KR20150130516A (ko) 2015-11-23

Family

ID=50625088

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020157029145A Abandoned KR20150130516A (ko) 2013-03-15 2014-03-12 비아와 커패시터의 플레이트 사이에 유전체를 갖는 커패시터

Country Status (6)

Country Link
US (1) US9935166B2 (https=)
EP (1) EP2973693B1 (https=)
JP (1) JP2016518702A (https=)
KR (1) KR20150130516A (https=)
CN (1) CN105009280B (https=)
WO (1) WO2014150747A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10943908B2 (en) 2018-09-21 2021-03-09 Samsung Electronics Co., Ltd. Method of forming semiconductor device

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US10480774B2 (en) 2013-05-16 2019-11-19 Mckeon Products, Inc. Light emitter with communication or power connector
US9264013B2 (en) 2013-06-04 2016-02-16 Qualcomm Incorporated Systems for reducing magnetic coupling in integrated circuits (ICS), and related components and methods
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US9954267B2 (en) 2015-12-28 2018-04-24 Qualcomm Incorporated Multiplexer design using a 2D passive on glass filter integrated with a 3D through glass via filter
US10373868B2 (en) * 2016-01-18 2019-08-06 Infineon Technologies Austria Ag Method of processing a porous conductive structure in connection to an electronic component on a substrate
JP6857329B2 (ja) * 2016-10-24 2021-04-14 大日本印刷株式会社 高周波部品及びその製造方法
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TWI669997B (zh) * 2018-01-25 2019-08-21 欣興電子股份有限公司 線路板結構及其製作方法
IT202000017554A1 (it) * 2020-07-20 2022-01-20 Thales Alenia Space Italia Spa Con Unico Socio Feedthrough capacitivo per moduli ermetici ibridi
US12322669B2 (en) * 2021-04-23 2025-06-03 Beijing Boe Sensor Technology Co., Ltd. Substrate integrated with passive devices and manufacturing method thereof
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10943908B2 (en) 2018-09-21 2021-03-09 Samsung Electronics Co., Ltd. Method of forming semiconductor device

Also Published As

Publication number Publication date
EP2973693B1 (en) 2020-08-26
JP2016518702A (ja) 2016-06-23
CN105009280A (zh) 2015-10-28
US9935166B2 (en) 2018-04-03
US20140268616A1 (en) 2014-09-18
WO2014150747A1 (en) 2014-09-25
EP2973693A1 (en) 2016-01-20
CN105009280B (zh) 2017-12-15

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P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000