KR20120031121A - 패키지 기판 및 이것을 이용한 모듈 및 전기/전자 기기 - Google Patents
패키지 기판 및 이것을 이용한 모듈 및 전기/전자 기기 Download PDFInfo
- Publication number
- KR20120031121A KR20120031121A KR1020110086435A KR20110086435A KR20120031121A KR 20120031121 A KR20120031121 A KR 20120031121A KR 1020110086435 A KR1020110086435 A KR 1020110086435A KR 20110086435 A KR20110086435 A KR 20110086435A KR 20120031121 A KR20120031121 A KR 20120031121A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive layer
- interlayer
- region
- package substrate
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/63—Vias, e.g. via plugs
- H10W70/635—Through-vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
- H10W70/65—Shapes or dispositions of interconnections
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Physics & Mathematics (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2010-211641 | 2010-09-22 | ||
| JP2010211641A JP5581933B2 (ja) | 2010-09-22 | 2010-09-22 | パッケージ基板及びこれを用いたモジュール並びに電気・電子機器 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20120031121A true KR20120031121A (ko) | 2012-03-30 |
Family
ID=45817006
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020110086435A Withdrawn KR20120031121A (ko) | 2010-09-22 | 2011-08-29 | 패키지 기판 및 이것을 이용한 모듈 및 전기/전자 기기 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US8866277B2 (https=) |
| JP (1) | JP5581933B2 (https=) |
| KR (1) | KR20120031121A (https=) |
| CN (1) | CN102412209A (https=) |
| TW (1) | TW201214647A (https=) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9368477B2 (en) * | 2012-08-27 | 2016-06-14 | Invensas Corporation | Co-support circuit panel and microelectronic packages |
| US8987872B2 (en) * | 2013-03-11 | 2015-03-24 | Qualcomm Incorporated | Electromagnetic interference enclosure for radio frequency multi-chip integrated circuit packages |
| US8901748B2 (en) * | 2013-03-14 | 2014-12-02 | Intel Corporation | Direct external interconnect for embedded interconnect bridge package |
| US9955568B2 (en) * | 2014-01-24 | 2018-04-24 | Dell Products, Lp | Structure to dampen barrel resonance of unused portion of printed circuit board via |
| US9824990B2 (en) * | 2014-06-12 | 2017-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pad design for reliability enhancement in packages |
| US9650242B2 (en) | 2015-09-22 | 2017-05-16 | International Business Machines Corporation | Multi-faced component-based electromechanical device |
| US10164002B2 (en) * | 2016-11-29 | 2018-12-25 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device and layout method |
| US10431537B1 (en) * | 2018-06-21 | 2019-10-01 | Intel Corporation | Electromigration resistant and profile consistent contact arrays |
| US11488901B2 (en) * | 2020-04-29 | 2022-11-01 | Advanced Semiconductor Engineering, Inc. | Package structure and method for manufacturing the same |
| CN115377051B (zh) * | 2022-08-25 | 2025-03-25 | 飞腾信息技术有限公司 | 封装基板、封装基板设计方法及相关设备 |
| US20240145364A1 (en) * | 2022-11-02 | 2024-05-02 | Stmicroelectronics S.R.L. | Semiconductor device and corresponding method |
| EP4372812A1 (en) * | 2022-11-16 | 2024-05-22 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Defining distribution of wiring elements compliant with target current-related value in component carrier with rows of equidistant wiring elements |
| CN120226154A (zh) * | 2022-11-16 | 2025-06-27 | 奥特斯奥地利科技与系统技术有限公司 | 具有连接至相互间隔开的传导区域的位于不同高度处的成排的等距布线元件和另外的布线元件的部件承载件 |
| US12389538B2 (en) * | 2023-01-26 | 2025-08-12 | Hewlett Packard Enterprise Development Lp | Varying diameters of power-vias in a PCB based on via location |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5665473A (en) * | 1994-09-16 | 1997-09-09 | Tokuyama Corporation | Package for mounting a semiconductor device |
| JP2004134679A (ja) * | 2002-10-11 | 2004-04-30 | Dainippon Printing Co Ltd | コア基板とその製造方法、および多層配線基板 |
| JP4534062B2 (ja) * | 2005-04-19 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2007201030A (ja) * | 2006-01-25 | 2007-08-09 | Fujitsu Ltd | 電子デバイス |
| JP2007221014A (ja) | 2006-02-20 | 2007-08-30 | Hitachi Ltd | 多層配線基板構造 |
| JP5165912B2 (ja) * | 2007-03-15 | 2013-03-21 | 株式会社日立製作所 | 低ノイズ半導体装置 |
| TWI416673B (zh) * | 2007-03-30 | 2013-11-21 | 住友電木股份有限公司 | 覆晶半導體封裝用之接續構造、增層材料、密封樹脂組成物及電路基板 |
-
2010
- 2010-09-22 JP JP2010211641A patent/JP5581933B2/ja not_active Expired - Fee Related
-
2011
- 2011-08-09 TW TW100128424A patent/TW201214647A/zh unknown
- 2011-08-29 KR KR1020110086435A patent/KR20120031121A/ko not_active Withdrawn
- 2011-09-13 US US13/231,518 patent/US8866277B2/en not_active Expired - Fee Related
- 2011-09-15 CN CN2011102742479A patent/CN102412209A/zh active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| TW201214647A (en) | 2012-04-01 |
| CN102412209A (zh) | 2012-04-11 |
| US20120068322A1 (en) | 2012-03-22 |
| JP2012069618A (ja) | 2012-04-05 |
| US8866277B2 (en) | 2014-10-21 |
| JP5581933B2 (ja) | 2014-09-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
|
| PC1203 | Withdrawal of no request for examination |
St.27 status event code: N-1-6-B10-B12-nap-PC1203 |
|
| WITN | Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid | ||
| PN2301 | Change of applicant |
St.27 status event code: A-3-3-R10-R13-asn-PN2301 St.27 status event code: A-3-3-R10-R11-asn-PN2301 |
|
| P22-X000 | Classification modified |
St.27 status event code: A-2-2-P10-P22-nap-X000 |