1335655 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種封裝基板之線路結構，尤指一種適 用於提高線路佈局靈活性之裝基板之線路結構。 5 【先前技術】 隨著電子產業的蓮勃發展，電子產品亦逐漸進入多功 能、尚性能的研發方向。封裝件為滿足半導體晶片高積集 度以及微型化的封裝要求，封裝基板的研究方向’在於提 10高封裝基板有限空間裡的佈線密度以配合積體電路 (Integrated circuit)晶片的需求。為此，業界遂發展出一種 夕層封裝基板，係在一核心基板（c〇re substrate)表面上形成 介電層及線路層，並於該介電層中形成導電盲孔 (conductive via holes)以提供線路層之間的電性連接。 I5 另一方面’多層封裝基板的層數愈多，愈不利於電子 產品輕薄短小的需求，因此在滿足大量的電訊輸入/輸出端 的需求上’如何能持續提高佈線密度，以降低封裝基板的 層數，為業界所重視之課題。 習知封裝基板可為覆晶式封裝基板或打破式封裝基 20 板。請參考圖1 ’承載層10表面配置有一圖案化線路層u， 其中’該承載層10係為核心板、封裝基板及多層封裝基板 内部的介電層之其中一者《該圖案化線路層11具有複數電 性連接端ΙΙΙ,ΙΙΓ，其中兩電性連接端111間具有一連接線 路112，且該連接線路112行經兩電性連接端111·之間。電性 5 1335655 5 ^接端nuu，可為電性接觸墊、凸塊焊墊及—打線焊塾之 若該承載層1G係為封裝基板之最外層介 電層，則該承載層1G及圖案化線路H之表面復配置有— =焊層（圖未示），且該防焊層具有開孔以顯露該些電性連接 h 111,111’。1335655 IX. Description of the Invention: [Technical Field] The present invention relates to a circuit structure of a package substrate, and more particularly to a circuit structure of a package substrate suitable for improving line layout flexibility. 5 [Prior Art] With the development of the electronics industry, electronic products have gradually entered the development direction of multi-function and performance. The package is designed to meet the high integration and miniaturization of semiconductor wafers. The research direction of package substrates is to increase the wiring density in the limited space of the package substrate to meet the needs of integrated circuit chips. To this end, the industry has developed an enamel package substrate by forming a dielectric layer and a wiring layer on a surface of a core substrate, and forming conductive via holes in the dielectric layer. To provide an electrical connection between the circuit layers. On the other hand, the more the number of layers of the multi-layer package substrate, the more it is not conducive to the light and short requirements of electronic products. Therefore, how to continuously increase the wiring density to reduce the layer of the package substrate when meeting the requirements of a large number of telecommunication input/output terminals The number is a topic that the industry values. The conventional package substrate may be a flip chip package substrate or a break package package 20 board. Please refer to FIG. 1 'the surface of the carrier layer 10 is provided with a patterned circuit layer u, wherein the carrier layer 10 is one of the core layer, the package substrate and the dielectric layer inside the multilayer package substrate. The utility model has a plurality of electrical connection terminals ΙΙΓ, wherein a connection line 112 is arranged between the two electrical connection ends 111, and the connection line 112 runs between the two electrical connection ends 111·. Electrical 5 1335655 5 ^ terminal nuu, which can be an electrical contact pad, a bump pad and a wire bonding if the carrier layer 1G is the outermost dielectric layer of the package substrate, the carrier layer 1G and the pattern The surface of the line H is reconfigured with a = solder layer (not shown), and the solder mask has openings to expose the electrical connections h 111, 111'.
10 在向線路密集度的目標上，圖案化線路U必須在兩個 方向上取得最佳化的組合，其—是為兩電性連接端⑴間之 連接線路m尋求最短的線路長度’以達到最高的電性傳輸 效率：其二是在兩電性連接端lu，間尋求最短的距離 (PltCh)，以朗最高的線路錢度。這些是影響圖案化線路 層11佈局靈活度的重要因素。 1510 On the line-dense goal, the patterned line U must be optimized in both directions, which is to find the shortest line length for the connection line m between the two electrical connections (1) to achieve The highest electrical transmission efficiency: The second is to find the shortest distance (PltCh) between the two electrical connections, to maximize the line cost. These are important factors influencing the layout flexibility of the patterned wiring layer 11. 15
然而，在圖案化線路層U中，欲符合半導體封裝件微 型化的要求’會因為追求高密集度線路佈局，將防焊層的 開孔縮小’以減小電性連接端⑴，lu，的面積，以及縮小線 路112的線寬’進而縮小兩電性連接端lu，間的間距。然而 縮小防焊層開孔卻容易影響電性連接端lu，ui，（例如凸 塊焊堅）之表面於後續所製作焊料凸塊之可靠纟例如焊料 凸塊容易脫落，致使良率降低。 20 此外，縮小線路112的線寬，容易因 斷路的問題，也會使良率降低。 細線路而產生線路 因此，如何在有限封裝基板的空間裡，提高線路佈局 之靈活性’以追求高密集度線路佈局，而不損及良率實 為重要之課題。 6 【發明内容】 本心a月之主I目的係在 — 構’俾能在有限封裝基板的空二之線路結 有度線路佈局，而不損及良率。 有▲於S知技術之缺點， 之線路結構，係包括：_承載層务:士 :：種封裝基板 係配置於該承載層: ®案化線路層， 山 層表面案化線路層具有至少-對電 H性連接端間之輕祕具有兩分合點， 〆連接線路於泫兩分合點間一 . *’ 局之靈活性。 刀為一，俾以棱尚線路佈 ’、中’承載層係為核心板' 封裝基 内部的介電層之其中一者。 夕曰封裝基板 復次，該兩分合點間一分為二之連接線路其線路長 义相同’寬度亦相!5]，俾以均分電流密度。 此外，電性連接端係為一電性接觸墊（1邮、—凸塊焊 墊（bump pad)及一打線焊墊（wire b〇nding pad)之其中一者。 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式’熟習此技藝之人士可由本說明書所揭示之内容輕易地 了解本發明之其他優點與功效。本發明亦可藉由其他不同 的具體實施例加以施行或應用，本說明書中的各項細節亦 可基於不同觀點與應用，在不悖離本發明之精神下進行各 種修飾與變更。 1335655 '月參考圖2，係為本發明封裝基板之線路結構示意圖。 本發明之實施方式中，係包括一承載層2〇以及一圖案化線 路層21，其中，該承載層2〇係為核心板、封裝基板及多層 封裝基板内部的介電層之其中—者，本實施例中係為封裝 5基板。圖案化線路層21係配置於該承載層2〇表面，該圖案 化料層21具有複數電性連接端211，211，，其巾兩電性連接 端211間具有一連接線路212，該連接線路212具有兩分合點 213 ’忒連接線路212於該兩分合點213間係一分為二，以形 籲 《兩線路212a，212b，並分別行經兩電性連接端211，之間， 10 俾以提高線路佈局之靈活性。 復·人，该兩分合點間一分為二之連接線路2i2a212b , 其線路長度、寬度皆相同，俾以均分電流密度。 . 此外，電性連接端211，211'係為一電性接觸墊、一凸塊 輝墊及一打線焊墊之其中一者。 15 最後，若該承載層2〇係為封裝基板之最外層介電層， 則該承載層20及圖案化線路層21之表面復配置有—防焊層 • (圖未不且該防焊層具有開孔以顯露該些電性連接端 211,21Γ 〇 '所述本發明係使二電性連接端間之連接線路且 有兩分合點，且連接線路於兩分合點間係一分為二。㈣ 係可提局封裝基板線路佈局之靈活性。該兩分合點間一分 為之連接線路，其線路長度可相同寬度亦可相同俾 以均分電流密度；並且其中一條線路斷線時，仍可經由另 條線路電性導接二電性連接端，而不影響電性品質。 8 1335655 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 5 【圖式簡單說明】 圖1係習知之封裝基板之線路結構示意圖。 圖2係本發明一較佳實施例之封裝基板線路結構示意 圖。 10 【主要元件符號說明】 10>20 承載層 • 11,21 圖案化線路層 ΙΙΙ,ΠΓ,211,211' 電性連接端 112,212,212a,212b 連接線路 213 分合點However, in the patterned circuit layer U, in order to meet the requirements of miniaturization of the semiconductor package, 'the hole of the solder resist layer is reduced by pursuing a high-density line layout' to reduce the electrical connection end (1), lu, The area, as well as the line width of the reduced line 112, further reduces the spacing between the two electrical connections lu. However, reducing the opening of the solder resist layer easily affects the surface of the electrical connection end lu, ui, (for example, bump soldering), which is reliable for subsequent solder bumps, such as solder bumps, which tend to fall off, resulting in a decrease in yield. Further, by narrowing the line width of the line 112, it is easy to cause a problem of disconnection, and the yield is also lowered. Thin lines create lines Therefore, how to improve the flexibility of line layout in the space of a limited package substrate is an important issue in pursuit of high-density line layout without compromising yield. 6 [Summary of the Invention] The main purpose of the heart of the month is that the structure can be placed on the line of the space of the limited package substrate without compromising the yield. There are ▲ in the shortcomings of the S-known technology, the line structure, including: _ bearer layer: Shi:: kind of package substrate is placed in the carrier layer: ® case circuit layer, the mountain surface case circuit layer has at least - The lightness of the electric H-connector has two points of separation, and the connecting line is between the two points. The knives are one, and the 承载, zhong, and the middle carrier layer are one of the dielectric layers inside the core board's package base. At the same time, the package substrate is duplicated, and the two connection points are divided into two, and the lines have the same length and the width is also the same! 5, and the current density is evenly divided. In addition, the electrical connection end is one of an electrical contact pad (1 post, bump pad, and wire b〇nding pad). EMBODIMENT OF THE INVENTION The present invention will be readily understood by those skilled in the art from this disclosure. Other advantages and advantages of the invention are readily apparent. The details of the present invention can be variously modified and changed without departing from the spirit and scope of the present invention. 1335655 'Month reference FIG. 2 is a schematic diagram of the circuit structure of the package substrate of the present invention. In an embodiment of the present invention, a carrier layer 2 〇 and a patterned circuit layer 21 are included, wherein the carrier layer 2 is a core layer, a package substrate, and a dielectric layer inside the multilayer package substrate. In this embodiment, the substrate is packaged 5. The patterned circuit layer 21 is disposed on the surface of the carrier layer 2, and the patterned material layer 21 has a plurality of electrical connection ends 211, 211. There is a connecting line 212 between the two electrical connecting ends 211. The connecting line 212 has two branching points 213'. The connecting line 212 is divided into two at the two points of separation 213 to describe the two lines 212a. 212b, and respectively through the two electrical connection end 211, between 10 俾 to improve the flexibility of the line layout. Fu people, the two points are divided into two connection lines 2i2a212b, the length and width of the line Similarly, the current density is divided. In addition, the electrical connection ends 211, 211' are one of an electrical contact pad, a bump pad and a wire bonding pad. 15 Finally, if the carrier layer 2 is the outermost dielectric layer of the package substrate, and the surface of the carrier layer 20 and the patterned circuit layer 21 is repeatedly provided with a solder mask layer (not shown and the solder resist layer has openings to reveal the The electrical connection end 211, 21Γ 〇 'the invention is a connection line between the two electrical connection ends and has two points of separation, and the connection line is divided into two between the two points of separation. (4) The flexibility of the layout of the board package substrate. The two points are divided into connection lines. The length of the line can be the same width or the same to equalize the current density; and when one line is broken, the two electrical connections can still be electrically connected via another line without affecting the electrical quality. 8 1335655 For the sake of convenience of description, the scope of the claims should be based on the scope of the patent application, and is not limited to the above embodiments. 5 [Simple description of the drawings] Fig. 1 is a conventional package substrate 2 is a schematic diagram of a circuit structure of a package substrate according to a preferred embodiment of the present invention. 10 [Description of main component symbols] 10>20 carrier layer • 11,21 patterned circuit layer ΠΓ, ΠΓ, 211, 211' Connection end 112, 212, 212a, 212b connection line 213 junction point