TWI359467B - Via structure of packages for high frequency semic - Google Patents

Via structure of packages for high frequency semic Download PDF

Info

Publication number
TWI359467B
TWI359467B TW094105867A TW94105867A TWI359467B TW I359467 B TWI359467 B TW I359467B TW 094105867 A TW094105867 A TW 094105867A TW 94105867 A TW94105867 A TW 94105867A TW I359467 B TWI359467 B TW I359467B
Authority
TW
Taiwan
Prior art keywords
substrate
metal
holes
pair
hole
Prior art date
Application number
TW094105867A
Other languages
Chinese (zh)
Other versions
TW200605235A (en
Inventor
Gregory E Howard
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of TW200605235A publication Critical patent/TW200605235A/en
Application granted granted Critical
Publication of TWI359467B publication Critical patent/TWI359467B/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6605—High-frequency electrical connections
    • H01L2223/6616—Vertical connections, e.g. vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01031—Gallium [Ga]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30105—Capacitance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09236—Parallel layout
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09381—Shape of non-curved single flat metallic pad, land or exposed part thereof; Shape of electrode of leadless component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09454—Inner lands, i.e. lands around via or plated through-hole in internal layer of multilayer PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709—Staggered pads, lands or terminals; Parallel conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09781—Dummy conductors, i.e. not used for normal transport of current; Dummy electrodes of components

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

13594671359467

九、發明說明： 【發明所屬之技術領域】 本發明一般係關於電子系統及半導體裝置領域，更明確 • δ之係關於用以製造用於高頻裝置之半導體封裝中的基板 之改良結構及方法》 ** 【先前技術】 - 積體電路（IC)技術目前的二個趨勢為：朝較高整合與縮 • 小組件特徵尺寸的動力。二個趨勢均支援朝較高操作速度 與較高信號頻率的趨勢。整合之較高位準包含需要較多的 ^號線路及電源線路，而較小特徵尺寸使得越來越難以保 持清晰信號不受相互干擾。此外，隨著信號頻率的增加， 需要細心注意信號之發射及屏蔽。 該等趨勢及要求不僅控制併入1(：的半導體晶片，而且控 制封入並保護ic晶片的封裝。實際上，在該等考量中必須 將電子產品之主板及其他零件包含作為一系統。 • 現代半導體封裝通常包括由絕緣體及導體之許多交替層 • 之堆疊組成的基板。通常而言，導體/絕緣體選路層之數量 可從4至25變化（某些裝置僅具有一個金屬層導體層之厚 度可以在約5至75 μηΐ之間，而絕緣體厚度大約在25至25〇〇 μιη之間。從封裝之晶片内部之印刷電路板獲得的高速信號 • 必須透過此層堆疊穿過金屬填充通孔。 _ 對於涉及到數百至數千信號及電源埠之高密度輸入/輸 出（I/O)設計而言，封裝選路層通常具有約15〇至25〇〇 之 間的厚度。對於高速1/0設計而言，此厚度為波長之可評估 99897.doc 1359467 部分’例如對於6至12兆位元設計（1 GHz或更高）而言，此 臨界範圍出現在約1000 μιη。當封裝之通孔部分變為波長之 可評估部分時’其波特性必須與源發射線路之波特性匹 配°此意味著通孔結構之阻抗必須與輸出及輸出發射線路 之阻抗匹配。 遺懷的係，並非由傳統通孔結構及給定的封裝技術需要 遵循的設計規則所提供此阻抗匹配。例如，若最小通孔間 距（中心至中心通孔間距）需要為2〇〇 μιη，並且通孔直徑為 100 μιη或較小’則此通孔至通孔對之阻抗為接近。然 而’輸入線路通常具有50 Ω之阻抗。因此，通孔中的反射 率將為約〇. 17%或17%，此對應於約15 dB之匹配。在與系 統中的所有其他反射組合之情況下，該等數值表示不可接 受的系統回應。 因此需要將調整封裝之通孔結構之相干低成本方法用於 高頻半導體裝置。此方法應導致優良的電氣封裝性能，尤 其係關於速度與功率、機械穩定性以及高產品可靠性。通 孔結構之製造方法應足夠靈活以應用於不同半導體產品系 列以及較廣頻譜範圍的設計及程序變化。較佳而言，在縮 短生產週期時間並增加產量的同時，應實現該等創新，並 且採用所安裝的裝備基礎以便不需要投資新的製造機械。 【發明内容】 本發明之一項具體實施例為一種用於高頻半導體裝置之 封裝之基板’其包括一平面絕緣基板，其具有嵌入該絕緣 體中的複數個平行、平面金屬層。基板進一步具有穿過基 99897.doc 1359467 板之至少一對平行、金屬填充通孔；通孔具有至少與其直 徑一樣大之彼此間的距離。各通孔中的金屬在該等金屬層 之各個所選平面上具有薄片狀延伸部分，從而導致增加的 -通孔至通孔容量，因此高頻信號之反射率係小於10%。 本發明之技術優點在於可採用許多不同方法使容量增加 金屬延伸部分成形。在較佳具體實施例中，使金屬延伸部 分接近成形為包圍各金屬層之平面中的各通孔之環形。 # 在另一較佳具體實施例中，使金屬延伸部分成形為平叉 形，其得以配置以便在金屬層之一個平面上，該對通孔之 第一通孔之叉形物係朝第二通孔定向並且部分包圍第二通 孔；而在金屬層之下一個平面上，第二通孔之又形物係朝 該對通孔之第一通孔定向並且部分包圍該對通孔之第一通 孔。 本發明之另一具體實施例為高頻半導體裝置，其具有： 具有至少一個焊墊的半導體晶片及具有複數個平行'平面 ί 金屬層的平面絕緣基板，該等金屬層嵌入絕緣體中及在第 • 一與第二基板表面上的輸入/輸出埠。基板具有穿過該基板 之至少一對平行、金屬填充通孔；該等通孔具有一直徑及 至少此直徑之彼此間的一距離，並且連接第一與第二表面 上的金屬埠。各通孔中的金屬在金屬層之各個所選平面上 具有薄片狀延伸部分，從而導致增加的通孔至通孔容量， 因此高頻信號之反射率係小於1〇〇/。。將晶片組裝在第一 Α 板表面上’以便將至少一個晶片焊墊連接至第一基板表面 上的基板埠之一。互連元件係附於第二基板上的埠以連接 99897.doc 1359467IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to the field of electronic systems and semiconductor devices, and more particularly to the improved structure and method of a substrate for manufacturing a semiconductor package for a high frequency device. ** ** [Prior Art] - The current two trends in integrated circuit (IC) technology are: the power to the higher integration and shrinkage of the small component feature size. Both trends support a trend toward higher operating speeds and higher signal frequencies. The higher level of integration involves the need for more ^ lines and power lines, while the smaller feature sizes make it increasingly difficult to maintain clear signals without interference. In addition, as the signal frequency increases, careful attention to signal transmission and shielding is required. These trends and requirements not only control the incorporation of a semiconductor wafer, but also control the encapsulation and protection of the package of the ic wafer. In fact, the motherboard and other parts of the electronic product must be included as a system in these considerations. Semiconductor packages typically include a substrate consisting of a stack of insulators and a plurality of alternating layers of conductors. In general, the number of conductor/insulator routing layers can vary from 4 to 25 (some devices have only one metal layer conductor layer thickness) It can be between about 5 and 75 μηΐ, and the insulator thickness is between 25 and 25 μm. The high-speed signal obtained from the printed circuit board inside the packaged wafer must be stacked through this layer through the metal-filled via. _ For high-density input/output (I/O) designs involving hundreds to thousands of signals and power supplies, the package routing layer typically has a thickness between approximately 15 〇 and 25 。. For design purposes, this thickness is evaluable for the wavelength of 99897.doc 1359467' For example, for a 6 to 12 megabit design (1 GHz or higher), this critical range appears at approximately 1000 μιη. When the through-hole portion of the package becomes an evaluable portion of the wavelength, its wave characteristics must match the wave characteristics of the source emission line. This means that the impedance of the via structure must be compatible with the impedance of the output and output transmission lines. The matching system is not provided by the traditional through-hole structure and the design rules that a given packaging technique needs to follow. For example, if the minimum via pitch (center-to-center via spacing) needs to be 2〇〇 Μιη, and the via diameter is 100 μηη or smaller, the impedance of the via-to-via pair is close. However, the input line usually has an impedance of 50 Ω. Therefore, the reflectivity in the via will be about 〇. 17% or 17%, which corresponds to a match of approximately 15 dB. In the case of combination with all other reflections in the system, these values represent an unacceptable system response. Therefore, the coherence of the via structure of the package is required to be low. The cost method is used for high frequency semiconductor devices. This method should result in excellent electrical package performance, especially with regard to speed and power, mechanical stability and high product reliability. The manufacturing method should be flexible enough to be applied to different semiconductor product families and to a wide spectrum of design and process variations. Preferably, these innovations should be achieved while reducing production cycle time and increasing throughput. The equipment base is installed so as not to invest in a new manufacturing machine. SUMMARY OF THE INVENTION One embodiment of the present invention is a substrate for a package of a high frequency semiconductor device that includes a planar insulating substrate having an embedded insulator a plurality of parallel, planar metal layers. The substrate further has at least one pair of parallel, metal filled vias through the substrate 99897.doc 1359467; the vias have a distance from each other at least as large as their diameter. The metal has flake-like extensions on each of the selected planes of the metal layers, resulting in increased through-via to via capacity, such that the reflectivity of the high frequency signal is less than 10%. A technical advantage of the present invention is that a number of different methods can be employed to shape the expanded metal extension. In a preferred embodiment, the metal extension is formed to approximate the annular shape of each of the through holes in the plane surrounding the respective metal layers. In another preferred embodiment, the metal extension portion is formed into a flat fork shape configured to be disposed on a plane of the metal layer, the fork of the first through hole of the pair of through holes being oriented toward the second The through hole is oriented and partially surrounds the second through hole; and in a plane below the metal layer, the shape of the second through hole is oriented toward the first through hole of the pair of through holes and partially surrounds the pair of through holes a through hole. Another embodiment of the present invention is a high frequency semiconductor device having: a semiconductor wafer having at least one pad and a planar insulating substrate having a plurality of parallel 'plane metal layers, the metal layers being embedded in the insulator and at • Input/output ports on the surfaces of the first and second substrates. The substrate has at least one pair of parallel, metal filled vias through the substrate; the through holes having a diameter and at least a distance from each other of the diameters and connecting the metal turns on the first and second surfaces. The metal in each of the vias has a lamellar extension on each of the selected planes of the metal layer, resulting in an increased via to via capacity, such that the reflectance of the high frequency signal is less than 1 〇〇/. . The wafer is assembled on the surface of the first rafter' to connect at least one of the wafer pads to one of the substrate rafts on the surface of the first substrate. The interconnecting component is attached to the second substrate to connect 99897.doc 1359467

至外部零件。 本發明之另一具體實施例為製造用於高頻半導體封裝的 基板之方法。忒方法選擇具有嵌入絕緣體中的複數個平行 - 平面金屬層之平面絕緣基板之材料及結構，並接著決定在 • 層之該等部分之各個所選金屬層中’何金屬層在附於金屬 « 填充通孔時將朝鄰近通孔提供通孔之容量增加。接著，形 . 成通孔延伸部分，同時構造該等金屬層之各個，重複步驟 • 直至逐步製造平面基板。再接著，形成穿過基板的至少一 對平打通孔，該等通孔具有某一直徑及至少該直徑之彼此 間的一距離。希望通孔連接基板上的金屬埠並且採用金屬 加以填充，該金屬亦使通孔與所選金屬層中的延伸部分接 觸。 本發明之具體實施例係關於希望用於高速及功率性能的 尚I/O計數裝置。技術優點在於，本發明提供裝置設計者數 個相依參數以達到增加的基板通孔容量及因此減少的信號 _ 反射’從而導致高度受控信號完整性及電感，與增加的功 . 率性能。參數包含通孔延伸部分之數量及形狀，與通孔之 數量及位置。本發明之-或多個具體實施例提供用於基板 上晶片互it之選#，例如受控焊接線路、較小金凸塊或較 大的回力凸塊。另夕卜，該等選擇之數個使裝置對於環境影 •響或溫度變化變得較不敏感。 * 當結合附圖及所时請專利範圍中提出的新穎特徵而考 量時，從本發明之較佳具體實施例之以下說明，將明白本 發明之某些具體實施例所表示的技術優點。 99897.doc 1359467 【實施方式】 圖1與2分別示意性描述一般指定為100與2〇〇的半導體裝 置之斷面圖。裝置分別由半導體晶片1〇1與201組成，該等 晶片在其主動表面1〇13與2〇 la上分別具有積體電路。晶片 101或201之半導體材料可以為矽、矽鍺、砷化鎵或任何其 他半導體材料。在圖1中，主動表面具有複數個焊墊i 02a、 102b等，及附於各焊墊的互連元件1〇3<)在圖2中，焊塾2〇2a 係顯示為適合於藉由焊接線路203進行連接。 在圖1與2中’裝置1〇〇與200進一步包含基板ι〇4與2〇4。 基板係由例如陶瓷或塑膠之絕緣材料（例如fr_4)製成。基 板在圖1中分別具有第一與第二表面1043與1〇4b，以及在圖 2中分別具有第一與第二表面2〇4a與204b。在各表面上，基 板具有金屬接觸墊或埠’其通常作為金屬跡線路之網路之 部分。在圖1中，該等埠與跡線係指定為第一表面1〇4a上的 105a與l〇5c，以有及第二表面1〇朴上的l〇5b與105d。在圖2 中’埠與有關跡線係指定為第一表面2Q4a上的2〇5&與 2〇5c，以及第二表面2〇4b上的2〇51?與2〇5(1。如該等圖式所 解說，埠通常為基板之電氣跡線之部分（嚴格地說，在基板 表面上存在跡線並且在基板内的多層金屬化中存在跡線， 圖1與2僅顯示幾條跡線）。 在圖1中’藉由將晶片之主動表面上的互連元件ι〇3附於 第一基板表面上的埠l〇5a ,將半導體晶片1〇1倒裝組裝在基 板104上。在圖2中，將半導體晶片2〇1之被動表面2〇lb安裝 在第一基板表面204a上；將焊墊2〇2a(僅表示複數個墊之一） 99897.doc 1359467 以線路焊接至第一基板表面2〇4a上的埠2〇5a。 分別將互連元件107與207附於圓1中的痒i〇5b、】㈣以 及圖2令的20_ 205d。該等元件通常係由可回流材料（例 如焊料）製造，並且係希望將裝置互連至外部零件。 金屬填充通孔連接裝置100與2〇〇之基板埠。在圖】中通 孔係指定為106,而在圖2中其係指定為2〇6。對於高頻裝置 而口，該等通孔因為包圍通孔的介電基板材料之（相對）介電 常數而變為電氣阻抗之實質部分。 對於四頻裝置而言，電氣信號之頻率内涵係如此以便裝 置封裝尺寸為電氣波長之可評估部分，例如波長的五分之 一或更大。在該等頻率或較大頻率情況下，電氣跡線之阻 抗會控制電氣信號是否可以穿過封裝。如結合圖1與2所說 明，封裝之電氣路徑之一部分包含透過封裝基板的通孔。 舉例而言，在2.5 mm厚之低溫共同燒制陶瓷基板中，介 電常數ε約為5，而電氣波長約為12.5_。因此，基板跡線 之阻抗開始控制電氣信號之發射的頻率為接近l〇 GHz。 本發明利用雙線式柱型導體線路之特徵阻抗係由以下等 式提供： z〇=Vl/c » 其中L為橫向電磁電感，而c為橫向電磁容量（例如參見 D「avid M.〜加於199〇年由Addis〇nWesley出版公司發行的 「Micr〇wave Engineering」第73頁）。對於無限長的線路而 言，橫向電磁場係靜態的’並且可以定義電感與容量。若 柱型線路具有半徑a及中心至中心距離D，則電感係由 99897.doc 1359467 ί=μ/π cosh-1 (D/2a)給定， 八中μ為材料滲透性。容量係由以下等式給定： C=7t£[cosh_ 1 (D/2a)] 將該等等式插入以上等式以獲得z〇，本發明導出： Ζο=>/μ/£· · 1/π · cosh· 1 (D/2a)。 在用於两頻半導體裝置之基板中，柱型導體線路通常係 由金屬填充通孔實現，該等通孔連接定位在基板之各表面 上的金屬槔。將以上等式應用於一對通孔，對於典型的50Ω 阻抗（其為設計所需要的標準阻抗）而言，D/2a比率為接近於 1β此意味著二個通孔將幾乎彼此碰觸。 另—方面’依據標準封裝設計規則，通孔直徑係從約1 〇〇 至250 μηι之範圍内。通孔隔開的間距為通孔直徑之間距的2 倍。然而對於高頻封裝而言，通孔間距應甚小於通孔直徑， 約為25 μιη。此對於製造將係不切實際的，因為基板通孔間 距通常為通孔直徑的2倍。因此，極難以僅採用傳統通孔直 控及通孔至通孔間距作為設計變數而設計具有約5〇 Ω之阻 抗的線路。 由本發明之具體實施例提供，用以建立較低阻抗ζ〇數值 的辦法係增加通孔之間的容量之概念。圖3之示意透視圖所 解說的具體實施例顯示一般指定為3〇〇的平面基板，其具有 複數個平行、平面金屬層301a、3〇lb、.等（圖3描述23層）。 金屬較佳為具有厚度約100 μιη之銅或銅合金。金屬層加以 圓案化以用作選路跡線（圖3中未顯示）。金屬層3 〇 1之間的間 距係由約1000至2500 μηι厚的絕緣介電質（圖3中未顯示）填 99897.doc 1359467 充。 至少一對通孔302與303穿過基板300。通孔302與303係彼 此平行並且採用金屬（較佳為銅或銅合金）加以填充。通孔通 吊用以連接基板表面上的金屬埠。例如，通孔3 〇2連接埠3〇4 與305’而通孔3〇3連接埠306與307。 在圖4之示意透視圖中放大通孔之小部分。如圖4所示， 通孔302具有直徑402 ’而通孔3〇3具有直徑4〇3。用於通孔 直么'之較佳數值係在約〇. 1至0.3 mm之範圍内。該等直徑可 彼此元全相同或不同。此外，通孔3〇2與3〇3具有彼此間的 距離405，其係至少與直徑402或403—樣大。 如圖3與4所示’各通孔之金屬在各金屬層之平面上具有 薄片狀延伸部分。在圖3之具體實施例中，各通孔金屬3〇2 與303具有各金屬層3〇la、3〇lb之平面上的延伸部分。例 如’通孔金屬302具有金屬層301a中的延伸部分321a、金屬 層301b中的延伸部分321b等。 圖4更詳細地描述該等金屬延伸部分。作為複數個範例 (如圖3所示）’通孔302中的金屬之延伸部分4〇1與通孔303 中的金屬之延伸部分402形成一對，因為已從基板金屬層之 堆疊中的相同金屬層建立該等部分。圖4中的延伸部分4〇1 與402之整體形狀係指示為接近圓形，但是延伸部分可配置 成任何合適形狀。因為已從基板中的堆疊之金屬層建立延 伸部分’所以其具有與金屬層相同的厚度，較佳在從約5 至75 μηι之範圍内的厚度4〇2a指示一範例。堆疊中金屬層之 間的絕緣體（圖4中未顯示）較佳具有約25與800 μηι之間的 99897.doc -12· 1359467 厚度。 為了最大化金屬填充通孔302與303之間的容量増加，使 例如401與402之延伸部分盡可能實際上接近在_起。用以 實現接近直徑之較佳設計特徵係使具有線性或直邊緣的延 伸部分401b與402b成形。該等直部分4011)與4〇几之接近部 分4〇4較佳為層厚度402a之50%或較多。例如，對於延伸部To external parts. Another embodiment of the present invention is a method of fabricating a substrate for a high frequency semiconductor package. The tantalum method selects the material and structure of a planar insulating substrate having a plurality of parallel-planar metal layers embedded in an insulator, and then determines which metal layer is attached to the metal in each of the selected metal layers of the layer. Filling the vias increases the capacity of the vias provided adjacent the vias. Next, the through-hole extension is formed, and each of the metal layers is constructed, and the steps are repeated until the planar substrate is gradually manufactured. Next, at least one pair of planed through holes are formed through the substrate, the through holes having a diameter and at least a distance from each other. It is desirable that the vias connect the metal germanium on the substrate and are filled with a metal that also contacts the via with the extended portion of the selected metal layer. Specific embodiments of the present invention are directed to still I/O counting devices that are desirable for high speed and power performance. A technical advantage is that the present invention provides device designers with several dependent parameters to achieve increased substrate via capacity and thus reduced signal_reflection' resulting in highly controlled signal integrity and inductance, with increased power performance. The parameters include the number and shape of the through-hole extensions, and the number and location of the through-holes. The - or more embodiments of the present invention provide for the selection of wafers on a substrate, such as controlled solder traces, smaller gold bumps, or larger pullback bumps. In addition, the number of such selections makes the device less sensitive to environmental effects or temperature changes. The technical advantages expressed by certain embodiments of the present invention will be apparent from the following description of the preferred embodiments of the invention. 99897.doc 1359467 [Embodiment] Figs. 1 and 2 schematically illustrate cross-sectional views of semiconductor devices generally designated 100 and 2, respectively. The devices are respectively composed of semiconductor wafers 1〇1 and 201, which respectively have integrated circuits on their active surfaces 1〇13 and 2〇 la. The semiconductor material of wafer 101 or 201 can be germanium, germanium, gallium arsenide or any other semiconductor material. In FIG. 1, the active surface has a plurality of pads i 02a, 102b, etc., and interconnecting elements 1 〇 3 attached to the pads. In FIG. 2, the pads 2 〇 2a are shown as being suitable for The welding line 203 is connected. In Figs. 1 and 2, the devices 1 and 200 further include substrates ι 4 and 2 〇 4. The substrate is made of an insulating material such as ceramic or plastic (for example, fr_4). The substrate has first and second surfaces 1043 and 1〇4b, respectively, in Fig. 1, and first and second surfaces 2〇4a and 204b, respectively, in Fig. 2. On each surface, the substrate has a metal contact pad or 埠' which is typically part of the network of traces. In Fig. 1, the turns and traces are designated as 105a and l5c on the first surface 1a4a to have l〇5b and 105d on the second surface 1 . In Fig. 2, '埠 and related traces are designated as 2〇5& and 2〇5c on the first surface 2Q4a, and 2〇51? and 2〇5(1) on the second surface 2〇4b. As illustrated by the figures, 埠 is typically part of the electrical trace of the substrate (strictly speaking, traces are present on the surface of the substrate and traces are present in the multilayer metallization within the substrate, Figures 1 and 2 show only a few traces In Fig. 1, the semiconductor wafer 1〇 is flip-chip mounted on the substrate 104 by attaching the interconnection member ι3 on the active surface of the wafer to the 埠10a on the surface of the first substrate. In FIG. 2, the passive surface 2〇1b of the semiconductor wafer 2〇1 is mounted on the first substrate surface 204a; the bonding pad 2〇2a (only one of the plurality of pads is shown) 99897.doc 1359467 is soldered to the line埠2〇5a on a substrate surface 2〇4a. The interconnection elements 107 and 207 are respectively attached to the itch i5b in the circle 1, (4) and 20_205d in the order of Fig. 2. These elements are usually reflowable. Materials such as solder are fabricated and it is desirable to interconnect the device to external components. The metal fills the via connections 100 and the substrate. In the figure, the through hole is designated as 106, and in Fig. 2, it is designated as 2〇6. For high frequency devices, the through holes are due to the (relative) dielectric constant of the dielectric substrate material surrounding the through holes. And become a substantial part of the electrical impedance. For a quad-band device, the frequency content of the electrical signal is such that the device package size is an evaluable portion of the electrical wavelength, such as one-fifth or more of the wavelength. At these frequencies or At larger frequencies, the impedance of the electrical traces controls whether electrical signals can pass through the package. As explained in connection with Figures 1 and 2, one of the electrical paths of the package contains through-vias through the package substrate. For example, at 2.5 In a mm-thick low-temperature co-fired ceramic substrate, the dielectric constant ε is about 5 and the electrical wavelength is about 12.5 Å. Therefore, the impedance of the substrate trace begins to control the frequency of emission of the electrical signal to be close to 1 GHz. The characteristic impedance of a two-wire column conductor is provided by the following equation: z〇=Vl/c » where L is the lateral electromagnetic inductance and c is the lateral electromagnetic capacitance (see, for example, D “avid M.~added to 19” "Micr〇wave Engineering", published by Addis〇n Wesley Publishing Company, 9th page.) For infinitely long lines, the transverse electromagnetic field is static and can define inductance and capacity. If the column line has a radius a And the center-to-center distance D, the inductance is given by 99897.doc 1359467 ί=μ/π cosh-1 (D/2a), and the eighth is the material permeability. The capacity is given by the following equation: C= 7t£[cosh_ 1 (D/2a)] Insert the equation into the above equation to obtain z〇, and the present invention derives: Ζο=>/μ/£· · 1/π · cosh· 1 (D/2a ). In a substrate for a two-frequency semiconductor device, the columnar conductor lines are typically implemented by metal filled vias that connect metal germanium positioned on each surface of the substrate. Applying the above equation to a pair of vias, for a typical 50 Ω impedance, which is the standard impedance required for the design, the D/2a ratio is close to 1β which means that the two vias will almost touch each other. Another aspect is that the through hole diameter ranges from about 1 250 to 250 μηι according to standard package design rules. The vias are spaced apart by a distance of 2 times the diameter of the vias. For high frequency packages, however, the via pitch should be much less than the via diameter, which is approximately 25 μm. This would be impractical for manufacturing because the substrate via spacing is typically twice the diameter of the via. Therefore, it is extremely difficult to design a circuit having an impedance of about 5 Ω Ω using only the conventional through-hole direct control and the via-to-via pitch as design variables. Provided by a specific embodiment of the invention, the method for establishing a lower impedance enthalpy value is to increase the concept of capacitance between vias. The specific embodiment illustrated in the schematic perspective view of Fig. 3 shows a planar substrate generally designated 3 turns having a plurality of parallel, planar metal layers 301a, 3〇lb, ., etc. (Fig. 3 depicts 23 layers). The metal is preferably a copper or copper alloy having a thickness of about 100 μm. The metal layer is rounded for use as a routing trace (not shown in Figure 3). The spacing between the metal layers 3 〇 1 is filled with an insulating dielectric (not shown in Figure 3) of about 1000 to 2500 μm thick. 99897.doc 1359467 Charge. At least a pair of through holes 302 and 303 pass through the substrate 300. The vias 302 and 303 are parallel to each other and are filled with a metal (preferably copper or copper alloy). The through hole is used to connect the metal crucible on the surface of the substrate. For example, the through holes 3 〇 2 are connected to the 埠 3 〇 4 and 305' and the through holes 3 〇 3 are connected to the 埠 306 and 307. A small portion of the through hole is enlarged in the schematic perspective view of FIG. As shown in Fig. 4, the through hole 302 has a diameter 402' and the through hole 3〇3 has a diameter of 4〇3. The preferred value for the through hole is in the range of about 1 to 0.3 mm. The diameters may be identical or different from each other. Further, the through holes 3〇2 and 3〇3 have a distance 405 from each other which is at least as large as the diameter 402 or 403. The metal of each of the through holes shown in Figs. 3 and 4 has a sheet-like extension in the plane of each metal layer. In the embodiment of Fig. 3, each of the via metal 3〇2 and 303 has an extension on the plane of each of the metal layers 3〇1, 3〇1b. For example, the through-hole metal 302 has an extended portion 321a in the metal layer 301a, an extended portion 321b in the metal layer 301b, and the like. Figure 4 depicts the metal extensions in more detail. As a plurality of examples (shown in FIG. 3), the metal extension portion 4〇1 in the via hole 302 forms a pair with the metal extension portion 402 in the via hole 303 because the same has been obtained from the stack of the substrate metal layers. The metal layer establishes these parts. The overall shape of the extensions 4〇1 and 402 in Fig. 4 is indicated as being nearly circular, but the extension may be configured in any suitable shape. Since the extended portion ' has been established from the stacked metal layers in the substrate, so it has the same thickness as the metal layer, preferably a thickness 4 〇 2a ranging from about 5 to 75 μηι indicates an example. The insulator between the metal layers in the stack (not shown in Figure 4) preferably has a thickness of 99897.doc -12. 1359467 between about 25 and 800 μm. In order to maximize the capacity increase between the metal filled vias 302 and 303, for example, the extensions of 401 and 402 are as close as possible to the actual position. A preferred design feature for achieving a near diameter is to shape the extended portions 401b and 402b having linear or straight edges. The portions 411) of the straight portions 4011) and 4" are preferably 50% or more of the layer thickness 402a. For example, for extensions

分金屬厚度1〇 μηι而言，直延伸部分之接近部分為至少$ μηι 〇 當在通孔302與303之間增加的複數個容量係累加用於圖 3中的所有延伸部分時，對到達通孔埠（3〇4與3〇6或3〇5與 3〇7)的信號之可能反射率的影響應為：借助於延伸部分，' 將僅反射小於_任何到達信號。此設計目的適用於高 頻及低頻信號。 圖5解說用以藉由增加通孔之間的容量建立較低阻抗數In the case of a metal thickness of 1 〇 μηι, the approximate portion of the straight extension portion is at least $ μηι 〇 when a plurality of capacity increases between the via holes 302 and 303 are accumulated for all the extension portions in FIG. The effect of the possible reflectivity of the signals of the apertures (3〇4 and 3〇6 or 3〇5 and 3〇7) should be: by means of the extension, 'will only reflect less than _ any arriving signal. This design is intended for high frequency and low frequency signals. Figure 5 illustrates the use of a lower impedance number by increasing the capacitance between vias

值的本發明之另-具體實_。該|體實施例再次使用具 有嵌入絕緣體中的複數個平行、平面金屬層之平面絕緣基 板。圖5之示意透視圖所描述的具體實施例顯示穿過平面基 板之一對通孔502與5〇3,該基板具有形成金屬層之堆疊的 複數個平行、平面金屬層(圖5中未顯示)。通孔502與503係 彼此平行並且採用金屬（例#為銅或鋼合金）加以填充。通孔 通常用以連接基板表面上的金科，例如通孔如連接璋 504與505,而通孔503連接埠5〇6與5〇7。 在圖6之示意透視圖中放大通孔之小部分。如圖6所示， 通孔502具有直徑612，而通孔5〇3具有直徑⑴。通孔直徑 99897.doc 之較佳數值為0·1至〇 3 mm。該等直徑可以彼此完全相同或 不同°此外’通孔502與5〇3具有彼此間的距離615，其係基 於實際原因至少與直徑612或613—樣大。 如圖5與6所示，各通孔之金屬具有選定金屬層之平面上 的薄片狀延伸部分。金屬延伸部分係成形為平又形，其得 以配置以便在金屬層之堆疊之一個平面上，該對通孔之第 通孔的又形物（例如通孔5〇2之叉形物6〇1幻係朝該對通孔 之第二通孔定向並且部分包圍該對通孔之第二通孔（例如 具有遺留金屬601b之通孔5〇3)，而在金屬層之堆疊之下一 個平面上’第二通孔之叉形物（例如通孔5〇3之叉形物6〇2a) 係朝該對通孔之第一通孔定向並且部分包圍該對通孔之第 一通孔（例如具有遺留金屬602b之通孔502)。叉形物之準確 形狀、又形物包圍該對通孔之鄰近通孔多少之範圍及組 態、以及留在該對通孔之第一通孔中的金屬數量，可用作 本發明之各具體實施例的設計變數；其部分取決於絕緣基 板材料之電氣特徵與基板中的金屬層之數量。 本發明之其他具體實施例為高頻半導體裝置，其具有利 用以上說明的一個或其他通孔金屬延伸部分特徵之基板。 圊7之不忍透視圖及斷面圖解說此類具體實施例之一範 例。一般指定為700的高頻裝置具有半導體晶片7〇1，其具 有至少一對焊墊702a與702b。平面絕緣基板7〇3具有嵌入絕 緣體（圖7中未顯示）中的複數個平行 '平面金屬層7〇钝、 704b .. 704n，以及第一基板表面上的輸入/輸出埠7〇5a 與7〇5b，與第二基板表面上的輸入/輸出埠7〇以與讣。較 99897.doc •14· / 佳絕緣材料包含陶瓷盥 化人物·欠β 物，但是可包括任何其他絕緣 ° s之較佳厚度範圍係在1〇〇〇與25〇〇叫之間。用 於導電層的較佳金屬包含銅、銅合金與錄，但是可包括任 可其他金屬或導電材料；層的較佳厚度範圍為約1〇〇 金屬層之數量可從僅幾層至3〇層以上。對於GHz範圍 内的向頻裝置而言’層的較佳數量係在15與25之間。 基板703具有穿過基板的至少一對平行、金屬填充通孔 與川。通孔具有直徑72()及至少該直徑之彼此間的距離 較佳通孔直徑範圍係從〇1至〇3麵，而用於通孔對 的較佳距離範圍係從—至二倍的直徑數值。通孔川連接第 一表面上的金屬埠702a與第二基板表面上的埠7〇^，而通 孔711連接第-表面上科鳩與第二表面上料鳩。 各通孔中的金屬具有金屬層之各個所選平面上的薄片 延伸部分。舉例而言’通孔710之金屬具有金屬層騎之平 面中的延伸部分740，而通孔711之金屬也具有金屬層704f 之平面中的延伸部分741。在圖7之具體實施例中，金屬延 伸部分具有圖3與4中所說明的形狀。其他具體實施例較佳 採用如圖5與6解說所成形的延伸部分。然而應強調金屬延 伸部分之許多其他幾何組態可同樣用於通孔容量增強目 的。作為薄片狀延伸部分740 ' 741等之結果，增加的通孔 容量之總和將分別到達通孔埠7053與7〇5b或7〇6&與7〇6b的 高頻信號之反射率減少至小於10〇/〇。 將晶片701組裝在第一基板表面上，以便將該對晶片焊墊 之各個連接至第一基板表面上的基板埠之一。在圖7之範例 99897.doc 15 1359467 中，祥塾702a係藉由金屬凸塊75〇連接至#7〇5a，而祥塾 腿係藉由金屬凸塊751連接至物*金屬凸塊服⑸ 較佳係由可回流金屬(例如錫、錫合金)或洋料製造。缺而， 已開發其他凸塊材料，包含導電黏著劑或z轴導體。鹿強調 也可頻繁使用不同的互連構件(例如焊接線路)，其可能會需 要修改的組裝方案，如圖2所指示。 而 為了連接至外部零件（例如印刷電路板或其他裝幻，基The value of the present invention is another specific. The body embodiment again uses a planar insulating substrate having a plurality of parallel, planar metal layers embedded in the insulator. The particular embodiment depicted in the schematic perspective view of Figure 5 shows through a pair of planar substrates, through holes 502 and 5, 3 having a plurality of parallel, planar metal layers forming a stack of metal layers (not shown in Figure 5). ). The through holes 502 and 503 are parallel to each other and are filled with a metal (Example #为铜 or steel alloy). The through holes are generally used to connect metal substrates on the surface of the substrate, such as through holes such as ports 504 and 505, and through holes 503 are connected to 埠5〇6 and 5〇7. A small portion of the through hole is enlarged in the schematic perspective view of FIG. As shown in FIG. 6, the through hole 502 has a diameter 612, and the through hole 5〇3 has a diameter (1). The preferred value of the through hole diameter 99897.doc is from 0·1 to 〇 3 mm. The diameters may be identical or different from each other. Further, the through holes 502 and 5〇3 have a distance 615 from each other which is at least as large as the diameter 612 or 613 for practical reasons. As shown in Figures 5 and 6, the metal of each of the through holes has a sheet-like extension on the plane of the selected metal layer. The metal extension portion is formed into a flat shape which is configured such that, in a plane of the stack of the metal layers, a shape of the through hole of the pair of through holes (for example, a fork of the through hole 5〇2) The magical system is oriented toward the second through hole of the pair of through holes and partially surrounds the second through hole of the pair of through holes (for example, the through hole 5〇3 having the remaining metal 601b), and on a plane below the stack of the metal layers 'The fork of the second through hole (for example, the fork 6 〇 2a of the through hole 5 〇 3) is oriented toward the first through hole of the pair of through holes and partially surrounds the first through hole of the pair of through holes (for example a through hole 502) having a residual metal 602b. The exact shape of the fork, the extent and configuration of the shape surrounding the adjacent through hole of the pair of through holes, and the remaining in the first through hole of the pair of through holes The amount of metal can be used as a design variable for various embodiments of the present invention; it depends in part on the electrical characteristics of the insulating substrate material and the number of metal layers in the substrate. Other embodiments of the present invention are high frequency semiconductor devices. Having one or other through-hole metal extensions utilizing the above description The substrate is exemplified. An example of such a specific embodiment is shown in Fig. 7. A high frequency device, generally designated 700, has a semiconductor wafer 〇1 having at least one pair of pads 702a and 702b. The planar insulating substrate 7〇3 has a plurality of parallel 'planar metal layers 7 blunt, 704b.. 704n embedded in an insulator (not shown in FIG. 7), and input/output ports 7〇5a and 7 on the surface of the first substrate. 〇5b, with the input/output 埠7〇 on the surface of the second substrate. 较 897 讣 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 897 The preferred thickness range is between 1 〇〇 and 25 〇〇. The preferred metal for the conductive layer comprises copper, copper alloy and recorded, but may include any other metal or conductive material; the preferred thickness of the layer The number of metal layers may range from only a few layers to more than 3 layers. For a frequency-frequency device in the GHz range, the preferred number of layers is between 15 and 25. The substrate 703 has a pass through. At least one pair of parallel, metal-filled through-holes of the substrate and the channel Having a diameter of 72 () and at least the diameter of each other preferably has a through hole diameter ranging from 〇1 to 〇3, and a preferred distance for the pair of through holes is from - to twice the diameter value. The through hole is connected to the metal crucible 702a on the first surface and the crucible on the surface of the second substrate, and the through hole 711 is connected to the first surface and the second surface. The metal in each through hole has a sheet extension on each selected plane of the metal layer. For example, the metal of the via 710 has an extension 740 in the plane of the metal layer ride, and the metal of the via 711 also has an extension in the plane of the metal layer 704f. Portion 741. In the particular embodiment of Figure 7, the metal extension has the shape illustrated in Figures 3 and 4. Other embodiments are preferably formed using the extensions as illustrated in Figures 5 and 6. However, it should be emphasized that many other geometric configurations of the metal extensions can be equally used for via capacity enhancement purposes. As a result of the sheet-like extensions 740 '741 and the like, the sum of the increased via capacities will reduce the reflectance of the high-frequency signals reaching the vias 7053 and 7〇5b or 7〇6& and 7〇6b, respectively, to less than 10 〇/〇. The wafer 701 is assembled on the surface of the first substrate to connect each of the pair of wafer pads to one of the substrate stacks on the surface of the first substrate. In the example 99897.doc 15 1359467 of Figure 7, the 塾 702a is connected to #7〇5a by a metal bump 75〇, and the 塾 leg is connected to the metal bump device by a metal bump 751 (5) It is preferably made of a reflowable metal such as tin, tin alloy or foreign material. In the absence of other bump materials, conductive adhesives or z-axis conductors have been developed. The deer emphasizes that different interconnecting members (such as welding lines) can also be used frequently, which may require a modified assembly scheme, as indicated in Figure 2. And in order to connect to external parts (such as printed circuit boards or other illusions, base

板703之第二表面具有例如7〇6&與7〇讣的埠。其可用作至外 部零件的磨力接點，或可具有如圓7所示由金屬凸塊752與 753附加的互連元件。該等金屬凸塊較佳係由可回流金屬 (例如錫、錫合金)或焊料製造’然而已開發其他凸塊材料， 例如導電黏著劑。 本發明之另一具體實施例為製造層壓基板之方法，該基 板具有複數個由絕緣層所分離的平行、平面金屬層，其中 此基板可尤其適合於高頻半導體封裝。該方㈣概述在圖8 之流程圖中，其從開始步驟8〇1開始並包括以下步驟： 步驟802:將電氣跡線蝕刻於第一絕緣體上金屬對之金屬 層中，而同時蝕刻與該等跡線分離的複數個金屬幾何結構。 以下事實為本發明之製造方法之非額外花費性質的基 礎：此蝕刻步驟同時建立第一金屬層之電氣跡線，以及整 合至本發明中的複數個金屬幾何結構係與該等跡線分離。 步驟803 :在已將平面位置處的各對添加至先前對上之 後，重複用於各連續絕緣體上金屬對的個別電氣跡線與幾 何結構之蝕刻步驟，因而逐步建立垂直對準金屬幾何結構 99897.doc -16· 1359467 之堆疊。 步驟804 :開啟複數層之各幾何堆疊之位置處的通孔。通 孔具有某直徑’並且一對通孔内的通孔具有至少此直徑之 彼此間的距離。 步驟805:採用金屬填充通孔，以便建立通孔金屬與各堆 邊之各個別金屬幾何結構之間的電氣接點，並且將幾何結 構轉換成個別通孔金屬之延伸部分。 步驟806:包裝所完成的基板以用於高頻半導體封裝。 雖然已參考解說性具體實施例說明本發明，但是不希望 將此說明視為具有限制意義。參考說明，熟悉此項技術者 將明白解說性具體實施例與本發明之其他具體實施例之各 修改及組合》 + J而。可以構造通孔對之通孔距離以及通孔金屬延 t P刀之輪廓以便可以達到任何通孔阻抗，從而避免高The second surface of the plate 703 has, for example, 7〇6& and 7〇讣. It can be used as a friction joint to the outer part or can have additional interconnecting elements by metal bumps 752 and 753 as indicated by circle 7. The metal bumps are preferably made of a reflowable metal (e.g., tin, tin alloy) or solder. However, other bump materials have been developed, such as conductive adhesives. Another embodiment of the present invention is a method of making a laminated substrate having a plurality of parallel, planar metal layers separated by an insulating layer, wherein the substrate is particularly suitable for high frequency semiconductor packaging. The party (iv) is summarized in the flow chart of FIG. 8 starting from the beginning step 8.1 and including the following steps: Step 802: etching the electrical traces into the metal layer of the metal pair on the first insulator while etching and A plurality of metal geometries separated by traces. The following facts are the basis for the non-extra cost nature of the fabrication method of the present invention: this etching step simultaneously establishes electrical traces of the first metal layer, and the plurality of metal geometries integrated into the present invention are separated from the traces. Step 803: After each pair at the planar position has been added to the previous pair, the individual electrical traces and geometry etching steps for the metal pairs on each of the continuous insulators are repeated, thereby gradually establishing a vertical alignment metal geometry 99897 Stack of .doc -16· 1359467. Step 804: Open a through hole at a position of each geometric stack of the plurality of layers. The through holes have a certain diameter' and the through holes in the pair of through holes have at least a distance from each other of the diameters. Step 805: Fill the vias with metal to establish electrical contacts between the via metal and the individual metal geometries of the stacks and to convert the geometry to an extension of the individual via metal. Step 806: Packaging the completed substrate for use in a high frequency semiconductor package. Although the present invention has been described with reference to illustrative embodiments, it is not intended to be construed as limiting. The modifications and combinations of the illustrative embodiments and other specific embodiments of the invention will be apparent to those skilled in the art. It is possible to construct the through hole distance of the through hole pair and the profile of the through hole metal extension so that any through hole impedance can be achieved, thereby avoiding high

5αΩ A 頻裝置中的實質信號反射。以上具體實施例中說明的 之阻抗僅為數.個範例之—。 另一範例為高頻裝置之基板中的本發明之一且 例因=須採用線料接而非倒裝晶片技術加以㈣。 施例 2㈣申請專利_包含任何此類修改與具體實 【圖式簡單說明】 圖1為具有帶有金屬填充通孔 以及用於附於外部 &上的倒裝組裝晶片 面圖。 料的互連兀件之半導體裝置之示意斷 99897.doc 1359467 圖2為具有帶有金屬填充通孔之基板上的焊接線路組裝 晶片以及用於附於外部零件的互連元件之半導體裝置之示 意斷面圖。 • 圖3解說包括具有複數個平行、平面金屬層之絕緣基板及 •具有金屬延伸部分的一對通孔之本發明之一具體實施例之 示意透視圖。 圖4為圖3之一部分的放大細節。 • 圖5解說包括具有金屬延伸部分、穿過絕緣基板之一對通 孔的本發明之另一具體實施例之示意透視圖。 圖6為圖5之一部分的放大細節。 圖7解說包括具有帶有複數個平行、平面金屬層之絕緣基 板上的倒裝組裝晶片，及帶有金屬延伸部分的一對通孔之 半導體裝置的本發明之另一具體實施例之示意透視圖。 圖8顯示依據用以製造適用於高頻半導體封裝之基板的 本發明之另一具體實施例的程序流程之示意方塊圖。 【主要元件符號說明】 100 半導體裝置 101 半導體晶片 l〇la 主動表面 l〇2a 焊墊 102b 焊墊 103 互連元件 104 基板 104a 第一表面 99897.doc • 18- 1359467 104b 第二表面 105a-105d 埠/跡線 106 通孔 107 互連元件 200 半導體裝置 201 半導體晶片 201a 主動表面 201b 被動表面 202a 焊墊 203 焊接線路 204 基板 204a 第一表面 204b 第二表面 205a-205d 埠/跡線 206 通孔 207. 互連元件 300 基板 301a 金屬層 301b 金屬層 302 通孔 303 通孔· 304-307 埠 321a 延伸部分 321b 延伸部分 -19- 99897.doc 1359467Substantial signal reflection in a 5αΩ A-frequency device. The impedances described in the above specific embodiments are only a few examples. Another example is one of the inventions in a substrate for a high frequency device and is exemplified by the use of wire bonding rather than flip chip technology (4). Example 2 (4) Patent Application _ Include any such modifications and specifics [Simplified description of the drawings] Fig. 1 is a flip-chip assembly wafer having a metal filled via and for attaching to an external & Illustrative of a semiconductor device for interconnecting devices 99897.doc 1359467 FIG. 2 is a schematic illustration of a semiconductor device having a solder trace assembly wafer on a substrate with metal filled vias and interconnecting features for attaching external components Sectional view. • Figure 3 illustrates a schematic perspective view of one embodiment of the present invention including an insulating substrate having a plurality of parallel, planar metal layers and a pair of through holes having metal extensions. Figure 4 is an enlarged detail of a portion of Figure 3. • Figure 5 illustrates a schematic perspective view of another embodiment of the present invention including a pair of through-holes having a metal extension and passing through an insulating substrate. Figure 6 is an enlarged detail of a portion of Figure 5. 7 illustrates a schematic perspective view of another embodiment of the present invention including a flip-chip assembled wafer having a plurality of parallel, planar metal layers and a pair of vias with metal extensions. Figure. Figure 8 shows a schematic block diagram of a program flow in accordance with another embodiment of the present invention for fabricating a substrate suitable for use in a high frequency semiconductor package. [Major component symbol description] 100 semiconductor device 101 semiconductor wafer 10a active surface l〇2a pad 102b pad 103 interconnection element 104 substrate 104a first surface 99897.doc • 18- 1359467 104b second surface 105a-105d 埠/ Trace 106 Via 107 Interconnect Element 200 Semiconductor Device 201 Semiconductor Wafer 201a Active Surface 201b Passive Surface 202a Pad 203 Solder Line 204 Substrate 204a First Surface 204b Second Surface 205a-205d 埠/Trace 206 Via 207. Interconnecting element 300 substrate 301a metal layer 301b metal layer 302 through hole 303 through hole · 304-307 埠 321a extension portion 321b extension portion -19-99897.doc 1359467

401 401b ' 402b 402 402a 403 404 405 502 503 504-507 601a 601b 602a 602b 612 613 615 700 701 702a 702b 703 704a-704n 705a 延伸部分 延伸部分 直徑 厚度 直徑 接近部分 距離 通孔 通孔 埠 叉形物 金屬 叉形物 金屬 直徑 直徑 距離 高頻裝置 半導體晶片 焊墊 焊墊 基板 金屬層 輸入/輸出蜂 •20· 99897.doc 1359467401 401b '402b 402 402a 403 404 405 503 504-507 601a 601b 602a 602b 612 613 615 700 701 702a 702b 703 704a-704n 705a extension portion extension portion diameter thickness diameter close to portion distance through hole through hole 埠 fork metal fork Shape metal diameter diameter distance high frequency device semiconductor wafer pad pad substrate metal layer input / output bee • 20·99897.doc 1359467

705b 706a 706b 720 730 710 711 740 741 750 751 752 753 輸入/輸出埠 輸入/輸出埠 輸入/輸出埠 直徑 距離 通孔 通孔 延伸部分 延伸部分 金屬凸塊 金屬凸塊 金屬凸塊 金屬凸塊 99897.doc -21 -705b 706a 706b 720 730 710 711 740 741 750 751 752 753 Input / Output 埠 Input / Output 埠 Input / Output 埠 Diameter Distance Through Hole Through Hole Extension Extension Metal Bump Metal Bump Metal Bump Metal Bumps 99897.doc -twenty one -

Claims (1)

1359467 第094105867號專利申請案 中☆申靖拜利fff榇拖太η叫年川只） 十、申請專利範圍： 1. 一種用於高頻半導體裝置之一封裝之基以，其包f 一平面絕緣基板，其具有嵌入該絕緣基板中的複數個 平行平面金屬層； 穿過該基板的至少一對平行、金屬填充通孔，該等通 孔具有一直徑及至少該直徑之彼此間的一距離，該等通 孔連接該基板上的金屬埠；以及 各通孔中的該金屬在該等金屬層之各個所選平面上具 有一薄片狀延伸部分； 該等通孔具有約0.1至0.3 mm之一直徑，以及約〇丨至〇 3 mm之彼此間的一距離。 2. 如相求項1之基板，其中該等薄片狀金屬延伸部分係配置 成致使各延伸部分增加該電氣通孔至通孔之容量，並且 該等增加的容量之總和將到達該等通孔埠的一高頻信號 之反射率減少至小於10%。 3·如明求項1之基板’其中使該等金屬延伸部分接近為環 形’其包圍各金屬層之該平面中的各通孔，該等延伸部 分附於該通孔金屬。 4. 5. 如請求項3之基板，其中該等環形具有直邊緣部分，其中 該等部分係緊密接近於附於鄰近通孔之個別延伸部分。 =:項4之基板，其中該等鄰近直邊緣部分之該接近部 刀係該等金屬延伸部分之該層厚度之至少5〇%。 其得到項1之基板其中將該等金屬延伸部分為平又形， 其仔到配置以便在該等金屬層之—個平面中，該對通孔 99897-1001028.doc 1359467 之第一通孔之該叉形物係朝該對通孔之第二通孔定向並 且部分包圍該對通孔之第二通孔，而在該等金屬層之該 下一個平面中，該第二通孔之該又形物係朝該對通孔之 第一通孔定向並且部分包圍該對通孔之該第—通孔。 7·如請求項1之基板，其中介於相鄰薄片狀延伸部分之間的 該絕緣基板具有約1000至2500微米之一厚度。 8. 一種面頻半導體裝置，其包括： 一半導體晶片，其可操作於至少一十億赫之頻率，該 晶片具有至少一對焊塾； 一平面絕緣基板，其具有嵌入該絕緣基板中的複數個 平行、平面金屬層，以及在第一基板表面與第二基板表 面上的輸入/輸出埠； 該基板具有穿過該基板之至少一對平行、金屬填充通 孔，該等通孔具有一直徑以及至少該直徑之彼此間的一 距離，該等通孔連接該第一表面與該第二表面上的該等 金屬埠，各通孔中的該金屬在該等金屬層之各個所選平 面中具有一薄片狀延伸部分； 將該晶片組裝在該第一基板表面上，以便將該至少一 對晶片焊墊分別連接至該第一基板表面上的一對該等基 板埠；以及 將互連元件附於該第二基板表面上的該等埠以連接至 外部零件該等薄片狀金屬延伸部分係配置成致使各延伸 部分增加該電氣通孔至通孔之容量，並且該等增加的容 $之總和將到達該第一基板表面或該第二基板表面上之 99897-1001028.doc • 2 - 1359467 該等通孔埠的一高頻信號之反射率減少至小於ι〇%。 9. 如請求項8之農置，其中該對晶片焊塾與該第-基板表面 上的該等基板埠之間的該等連接為金屬凸塊。 10. 如請求項8之裝置’其中該對晶片焊塾與該第一基板表面 上的該等基板埠之間的該等連接為焊接線路。 η·如請求項8之穿(置，其中該等互連元件為金屬回流凸塊。 12·如請求項8之裝置，其中介於相鄰薄片狀延伸部分之間的 該絕緣基板具有約1000至25〇〇微米之一厚度。 13.種用於在一半導體裝置中最小化一封裝通孔結構之阻 抗與高頻信號傳輸線之阻抗間之差異之基板，其包含： 一平面絕緣基板，其具有嵌入該絕緣基板中的複數個 平行平面金屬層； 穿過該基板的至少一對平行、金屬填充通孔，該等通 孔具有一直徑及至少該直徑之彼此間的一距離，該等通 孔連接該基板上的金屬埠； 各通孔中的該金屬在該等金屬層之各個所選平面上具 有一薄片狀延伸部分；以及 該等通孔具有不大於約〇‘3 mm之一直徑以及不大於 約0.3 mm之彼此間的一距離。 14.如請求項13之基板，其中介於相鄰薄片狀延伸部分之間 的該絕緣基板具有約1000至2500微米之一厚度。 99897-1001028.doc1359467 Patent application No. 094105867 ☆ Shenjing Bailey fff榇 dragging too η called Nianchuan only) X. Patent application scope: 1. A base for packaging of a high-frequency semiconductor device, which is a plane An insulating substrate having a plurality of parallel planar metal layers embedded in the insulating substrate; at least one pair of parallel, metal filled vias passing through the substrate, the through holes having a diameter and at least a distance between the diameters The through holes are connected to the metal crucible on the substrate; and the metal in each of the through holes has a sheet-like extension on each of the selected planes of the metal layers; the through holes have a thickness of about 0.1 to 0.3 mm a diameter, and a distance from about 〇丨 to 3 mm. 2. The substrate of claim 1, wherein the flaky metal extensions are configured to cause each extension to increase the capacity of the electrical via to the via, and the sum of the increased capacities will reach the vias The reflectivity of a high frequency signal of 埠 is reduced to less than 10%. 3. The substrate of claim 1, wherein the metal extensions are brought into a ring shape which surrounds each of the through holes in the plane of the metal layers, the extension portions being attached to the via metal. 4. The substrate of claim 3, wherein the rings have straight edge portions, wherein the portions are in close proximity to individual extensions attached to adjacent through holes. =: The substrate of item 4, wherein the proximity portion of the adjacent straight edge portions is at least 〇% of the thickness of the layer of the metal extensions. The substrate of item 1 is obtained, wherein the metal extension portions are flat and shaped, and are arranged to be in a plane of the metal layers, the first through holes of the pair of through holes 99897-1001028.doc 1359467 The fork is oriented toward the second through hole of the pair of through holes and partially surrounds the second through hole of the pair of through holes, and in the next plane of the metal layers, the second through hole The shape is oriented toward the first through hole of the pair of through holes and partially surrounds the first through hole of the pair of through holes. 7. The substrate of claim 1, wherein the insulating substrate between adjacent sheet-like extensions has a thickness of about 1000 to 2500 microns. 8. A surface frequency semiconductor device comprising: a semiconductor wafer operable at a frequency of at least one billion Hz, the wafer having at least one pair of solder pads; and a planar insulating substrate having a plurality of embedded in the insulating substrate a parallel, planar metal layer, and input/output ports on the surface of the first substrate and the surface of the second substrate; the substrate having at least one pair of parallel, metal-filled vias through the substrate, the vias having a diameter And at least a distance between the diameters, the through holes connecting the first surface and the metal ridges on the second surface, the metal in each of the through holes being in each selected plane of the metal layers Having a sheet-like extension; assembling the wafer on the surface of the first substrate to respectively connect the at least one pair of wafer pads to a pair of the substrates on the surface of the first substrate; and interconnecting the components The rafts attached to the surface of the second substrate to be connected to the outer component, the flaky metal extensions are configured to cause the extensions to increase the electrical vias to the vias And the sum of the increased capacitances will reach 99897-1001028.doc • 2 - 1359467 on the surface of the first substrate or the surface of the second substrate. The reflectivity of a high frequency signal of the through holes is reduced to Less than ι〇%. 9. The agricultural device of claim 8, wherein the connections between the pair of wafer pads and the substrate turns on the surface of the first substrate are metal bumps. 10. The device of claim 8 wherein the connections between the pair of wafer pads and the substrate turns on the surface of the first substrate are solder lines. η. The insertion of claim 8 wherein the interconnecting elements are metal reflow bumps. 12. The apparatus of claim 8, wherein the insulating substrate between adjacent sheet-like extensions has about 1000 a thickness of one to 25 Å. 13. A substrate for minimizing a difference between an impedance of a package via structure and an impedance of a high frequency signal transmission line in a semiconductor device, comprising: a planar insulating substrate; Having a plurality of parallel planar metal layers embedded in the insulating substrate; at least one pair of parallel, metal filled vias passing through the substrate, the through holes having a diameter and at least a distance between the diameters, The holes are connected to the metal crucible on the substrate; the metal in each of the through holes has a sheet-like extension on each of the selected planes of the metal layers; and the through holes have a diameter of not more than about 〇'3 mm And a distance of not more than about 0.3 mm from each other. 14. The substrate of claim 13, wherein the insulating substrate between adjacent sheet-like extensions has a thickness of about 1000 to 2500 microns. 1001028.doc
TW094105867A 2004-02-27 2005-02-25 Via structure of packages for high frequency semic TWI359467B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/788,711 US7154047B2 (en) 2004-02-27 2004-02-27 Via structure of packages for high frequency semiconductor devices

Publications (2)

Publication Number Publication Date
TW200605235A TW200605235A (en) 2006-02-01
TWI359467B true TWI359467B (en) 2012-03-01

Family

ID=34887059

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094105867A TWI359467B (en) 2004-02-27 2005-02-25 Via structure of packages for high frequency semic

Country Status (2)

Country Link
US (1) US7154047B2 (en)
TW (1) TWI359467B (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100468706C (en) * 2003-12-04 2009-03-11 松下电器产业株式会社 Circuit board and method for manufacturing the same, semiconductor package, component built-in module
KR100651414B1 (en) * 2004-02-13 2006-11-29 삼성전기주식회사 Printed circuit board having coaxial via hole
US9006028B2 (en) * 2008-09-12 2015-04-14 Ananda H. Kumar Methods for forming ceramic substrates with via studs
JP5758584B2 (en) * 2010-03-18 2015-08-05 本田技研工業株式会社 Junction box
CN102378476A (en) * 2010-08-26 2012-03-14 鸿富锦精密工业（深圳）有限公司 Printed circuit board
US8546903B2 (en) * 2010-10-07 2013-10-01 Texas Instruments Incorporated Ionic isolation ring
TWI456726B (en) * 2011-01-24 2014-10-11 Ind Tech Res Inst Interconnection structure, apparatus therewith, circuit structure therewith, and method to prevent an interconnection structure from emi
JP5904856B2 (en) * 2012-04-23 2016-04-20 キヤノン株式会社 Printed wiring board, semiconductor package and printed circuit board
US10103054B2 (en) * 2013-03-13 2018-10-16 Intel Corporation Coupled vias for channel cross-talk reduction
EP3033801A4 (en) * 2013-08-12 2017-05-17 Telefonaktiebolaget LM Ericsson (publ) Via transition and method of fabricating the same
US9722012B1 (en) * 2016-09-02 2017-08-01 Qualcomm Incorporated Circuits and methods providing mutual capacitance in vertical electrical connections
US10727190B2 (en) * 2018-12-27 2020-07-28 Tektronix, Inc. Compound via RF transition structure in a multilayer high-density interconnect
US10842017B2 (en) * 2019-01-29 2020-11-17 Dell Products L.P. Printed circuit boards with non-functional features
CN117787197A (en) * 2022-09-22 2024-03-29 长鑫存储技术有限公司 Circuit structure, forming method thereof and memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6538538B2 (en) * 1999-02-25 2003-03-25 Formfactor, Inc. High frequency printed circuit board via
US6137161A (en) * 1999-09-14 2000-10-24 International Business Machines Corporation Interposer array module for capacitive decoupling and filtering
US6943063B2 (en) * 2001-11-20 2005-09-13 Taiwan Semiconductor Manufacturing Co., Ltd. RF seal ring structure
US7152312B2 (en) * 2002-02-11 2006-12-26 Adc Dsl Systems, Inc. Method for transmitting current through a substrate
JP2004241680A (en) * 2003-02-07 2004-08-26 Mitsubishi Electric Corp Multilayer printed circuit board
US7081650B2 (en) * 2003-03-31 2006-07-25 Intel Corporation Interposer with signal and power supply through vias
US7583513B2 (en) * 2003-09-23 2009-09-01 Intel Corporation Apparatus for providing an integrated printed circuit board registration coupon

Also Published As

Publication number Publication date
TW200605235A (en) 2006-02-01
US20050191785A1 (en) 2005-09-01
US7154047B2 (en) 2006-12-26

Similar Documents

Publication Publication Date Title
TWI359467B (en) Via structure of packages for high frequency semic
TWI712145B (en) Interface structures and methods for forming same
US7800916B2 (en) Circuitized substrate with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
US7924131B2 (en) Electrical component having an inductor and a method of formation
TWI377878B (en) Multi-layer printed circuit board comprising a through connection for high frequency applications
US6362525B1 (en) Circuit structure including a passive element formed within a grid array substrate and method for making the same
US6532143B2 (en) Multiple tier array capacitor
US5530288A (en) Passive interposer including at least one passive electronic component
EP3442314A1 (en) Ic package
JP2005191518A (en) Printed circuit board and package formed with skew via
US9048232B2 (en) Package with integrated pre-match circuit and harmonic suppression
US11937368B2 (en) Structure for circuit interconnects
EP1795057A1 (en) Circuit board assembly with reduced capacitive coupling
JP3899059B2 (en) Electronic package having low resistance and high density signal line and method of manufacturing the same
JP2001203300A (en) Board for wiring, semiconductor device and producing method for board for wiring
US8324508B2 (en) Composite circuit board
TW201306213A (en) Through silicon via structure for impedance matching and electrical interconnection
JPH05335475A (en) Circuit chip packaged device
CN216902914U (en) Silicon-based substrate and chip
EP2387295A1 (en) IC-Package with integrated impedance matching and harmonic suppression
WO2018054057A1 (en) Package structure
US20220238449A1 (en) Hybrid integrated circuit package
WO2006019336A2 (en) Impedance controlled interconnect substrate and package for high-frequency electronic device
Liao et al. Numerical analysis on compliance and electrical behavior of multi-copper-column flip-chip interconnects for wafer-level packaging
EP4095905A1 (en) Flip-chip ball grid array-type integrated circuit package for very high frequency operation