KR20100111666A - 셀 소스 ｉｒ 강하를 방지하기 위해 소스 전위를 조절하는 방법 - Google Patents

셀 소스 ｉｒ 강하를 방지하기 위해 소스 전위를 조절하는 방법 Download PDF

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Publication number
KR20100111666A
KR20100111666A KR1020107013249A KR20107013249A KR20100111666A KR 20100111666 A KR20100111666 A KR 20100111666A KR 1020107013249 A KR1020107013249 A KR 1020107013249A KR 20107013249 A KR20107013249 A KR 20107013249A KR 20100111666 A KR20100111666 A KR 20100111666A
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South Korea
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source
page
voltage
memory cell
memory
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English (en)
Korean (ko)
Inventor
다나 리
니마 모클레시
딥팩 찬드라 세카르
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쌘디스크 코포레이션
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

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  • Read Only Memory (AREA)
KR1020107013249A 2007-12-20 2008-12-12 셀 소스 ｉｒ 강하를 방지하기 위해 소스 전위를 조절하는 방법 Withdrawn KR20100111666A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/961,871 US7764547B2 (en) 2007-12-20 2007-12-20 Regulation of source potential to combat cell source IR drop
US11/961,871 2007-12-20

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KR20100111666A true KR20100111666A (ko) 2010-10-15

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KR1020107013249A Withdrawn KR20100111666A (ko) 2007-12-20 2008-12-12 셀 소스 ｉｒ 강하를 방지하기 위해 소스 전위를 조절하는 방법

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US (1) US7764547B2 (enExample)
EP (1) EP2223304A1 (enExample)
JP (1) JP2011508354A (enExample)
KR (1) KR20100111666A (enExample)
CN (1) CN101903955A (enExample)
TW (1) TW200945349A (enExample)
WO (1) WO2009082637A1 (enExample)

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KR20150130637A (ko) * 2014-05-13 2015-11-24 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 프로그램 방법
KR20200102671A (ko) * 2019-02-22 2020-09-01 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템

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US9892791B2 (en) * 2015-06-16 2018-02-13 Sandisk Technologies Llc Fast scan to detect bit line discharge time
CN105895153B (zh) * 2016-03-25 2019-07-02 上海华虹宏力半导体制造有限公司 存储器及其干扰检测和消除的方法、装置
KR102620805B1 (ko) * 2016-09-22 2024-01-04 에스케이하이닉스 주식회사 반도체 메모리 장치
US10763304B2 (en) * 2017-06-27 2020-09-01 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of forming the same
JP7091130B2 (ja) * 2018-05-08 2022-06-27 キオクシア株式会社 半導体記憶装置
JP2019200828A (ja) * 2018-05-16 2019-11-21 東芝メモリ株式会社 半導体記憶装置
US10984872B1 (en) * 2019-12-05 2021-04-20 Integrated Silicon Solution, (Cayman) Inc. Non-volatile memory with source line resistance compensation
US11049572B1 (en) * 2020-03-06 2021-06-29 Macronix International Co., Ltd. Memory device, source line voltage adjuster and source line voltage adjusting method thereof
TWI764104B (zh) * 2020-03-06 2022-05-11 旺宏電子股份有限公司 記憶體裝置、源極線電壓調整器及其源極線電壓調整方法
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JP2024136330A (ja) * 2023-03-23 2024-10-04 キオクシア株式会社 半導体記憶装置

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20150130637A (ko) * 2014-05-13 2015-11-24 삼성전자주식회사 비휘발성 메모리 장치 및 그것의 프로그램 방법
KR20200102671A (ko) * 2019-02-22 2020-09-01 삼성전자주식회사 반도체 메모리 장치 및 이를 포함하는 메모리 시스템

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Publication number Publication date
US20090161433A1 (en) 2009-06-25
US7764547B2 (en) 2010-07-27
EP2223304A1 (en) 2010-09-01
WO2009082637A1 (en) 2009-07-02
TW200945349A (en) 2009-11-01
CN101903955A (zh) 2010-12-01
JP2011508354A (ja) 2011-03-10

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PA0105 International application

Patent event date: 20100616

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid