KR20090093880A - 반도체 장치 - Google Patents

반도체 장치

Info

Publication number
KR20090093880A
KR20090093880A KR1020090016884A KR20090016884A KR20090093880A KR 20090093880 A KR20090093880 A KR 20090093880A KR 1020090016884 A KR1020090016884 A KR 1020090016884A KR 20090016884 A KR20090016884 A KR 20090016884A KR 20090093880 A KR20090093880 A KR 20090093880A
Authority
KR
South Korea
Prior art keywords
source
lead
gate
die pad
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020090016884A
Other languages
English (en)
Korean (ko)
Inventor
구니하루 무또
다다또시 단노
히로유끼 다까하시
Original Assignee
가부시끼가이샤 르네사스 테크놀로지
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가부시끼가이샤 르네사스 테크놀로지 filed Critical 가부시끼가이샤 르네사스 테크놀로지
Publication of KR20090093880A publication Critical patent/KR20090093880A/ko
Withdrawn legal-status Critical Current

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  • General Physics & Mathematics (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Wire Bonding (AREA)
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JP7649127B2 (ja) * 2020-11-04 2025-03-19 ローム株式会社 半導体装置
JP7653305B2 (ja) 2021-06-02 2025-03-28 ルネサスエレクトロニクス株式会社 半導体装置
CN113410217B (zh) * 2021-07-23 2025-10-17 苏州华太电子技术股份有限公司 一种双管芯合封的共源共栅SiC功率器件
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