JP6636846B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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- JP6636846B2 JP6636846B2 JP2016081468A JP2016081468A JP6636846B2 JP 6636846 B2 JP6636846 B2 JP 6636846B2 JP 2016081468 A JP2016081468 A JP 2016081468A JP 2016081468 A JP2016081468 A JP 2016081468A JP 6636846 B2 JP6636846 B2 JP 6636846B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 238000007747 plating Methods 0.000 claims description 63
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- 239000007769 metal material Substances 0.000 claims description 2
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- 238000007789 sealing Methods 0.000 claims description 2
- 230000000052 comparative effect Effects 0.000 description 11
- 239000010949 copper Substances 0.000 description 7
- 229910000679 solder Inorganic materials 0.000 description 5
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- 229910000881 Cu alloy Inorganic materials 0.000 description 2
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- 229910052802 copper Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
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- 239000013585 weight reducing agent Substances 0.000 description 1
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Description
そこで、本発明の一実施形態は、隣接するアイランド間に接合材がブリッジすることを防止することができる半導体装置およびその製造方法を提供する。
図1は、本発明の一実施形態に係る半導体装置1を示す斜視図である。図2は、半導体装置1の模式的な平面図である。図3Aおよび図3Bは、それぞれ、図2のA−A切断面およびB−B切断面における断面図である。図4は、半導体装置1におけるめっき膜17のパターンを示す図である。図4では、明瞭化のため、半導体チップ4およびワイヤ5を省略して示している。
複数の第1リード7は、アイランド2の第1リード側端面24に沿って間隔を空けて配列され、各アイランド2に同数ずつ設けられている。たとえば、この実施形態では、1つのアイランド2に対して第1リード7が2本ずつ設けられている。各第1リード7は、水平方向(アイランド2の上面21に平行な方向)にアイランド2と間隔を空けると共に、図3Aに示すように、鉛直方向(アイランド2の上面21の法線方向)において、高低差hを有して配置されている。この実施形態では、各第1リード7は、アイランド2の上方位置に配置されているが、アイランド2の下方位置に配置されていてもよい。むろん、第1リード7をアイランド2と同じ高さ位置に配置してもよい。
インナーリード9は、アイランド2の上方位置においてアイランド2の上面21と平行に配置され、ワイヤ5が接続されるランド部11およびランド部11から外側へ延びる端子としての延出部12を一体的に有している。ランド部11は、延出部12よりも幅広に形成されている。
複数の第2リード8は、アイランド2の第2リード側端面25に沿って間隔を空けて配列され、各アイランド2に同数ずつ設けられている。たとえば、この実施形態では、1つのアイランド2に対して第2リード8が2本ずつ設けられている。各第2リード8は、アイランド2に片持ち支持された一体型リードとして構成されている。
インナーリード15は、略一定幅の端子としてアイランド2の第2リード側端面25から外側へ延びている。
アウターリード16は、その全体がインナーリード15の延長部(インナーリード15と同じ幅)で構成されており、下方へ屈曲する屈曲部を有する略クランク形状に形成されている。アウターリード16は、半導体装置1をプリント配線基板に実装するときの外部接続部として機能する。
図4を参照して、めっき膜17はハッチングを施した領域であり、アイランド2のほぼ全域、第1リード7のランド部11および延出部12の基端部(ランド部11との境界部)、第2リード8のインナーリード15の基端部(アイランド2との境界部)、ならびにアイランドサポート部13の基端部(アイランド2との境界部)に形成されている。
つまり、対向端面22がめっき膜17で覆われていると、接合材32(後述)が対向端面22まで濡れ広がり、それが原因で、隣接するアイランド2に接合材32がブリッジするおそれがあるため好ましくない。これに対し、第1リード側端面24は、隣接する第1リード7との間に高低差h(図3A)が設けられている。そのため、めっき膜17で覆われることで接合材32が濡れ広がっても、第1リード7に接合材32がブリッジする可能性は低く、あまり問題とならない。外側端面23および第2リード側端面25に関しても同様に、これらの端面23,25に隣接する導電部材は、アイランドサポート部13および第2リード8であり、いずれもアイランド2と直接接続されているものであるから、これらの部材8,13に接合材32が触れても短絡の問題が生じない。したがって、外側端面23および第2リード側端面25については、めっき膜17で覆われていてもよい。
半導体装置1を製造するには、たとえば、まず図5Aおよび図5Bに示すように、アイランド2およびリード3を一体的に有するリードフレームが準備される。
次に、図8Aおよび図8Bに示すように、接合材32を介して、半導体チップ4がアイランド2にダイボンディングされる。
次に、図10Aおよび図10Bに示すように、複数のアイランド2、複数のリード3、半導体チップ4およびワイヤ5は、樹脂パッケージ6によって一括して封止される。封止後、各半導体装置1の個片に切り分けられる。そして、リード3のアウターリード10,16がクランク状に曲がるように加工されることによって、図1に示す半導体装置1が得られる。
たとえば、前述の実施形態では、素地領域27は、隣接するアイランド2の両方に形成されていたが、どちらか一方にだけ形成された態様であってもよい。この場合、他方のアイランド2の対向端面22には、めっき膜17が形成されていてもよい。このような構成であっても、少なくとも対向端面22に素地領域27が形成されたアイランド2に接合材32が濡れ広がることを防止できるので、上記の効果を達成することができる。
本発明の半導体装置は、パワーモジュール等のパワーデバイスの製造全般に利用可能であり、特に、小型・軽量化が求められている分野、車載、太陽電池、産業機器向けの装置等、温度変化が激しい環境下で使用される装置に良好に適用できる。
<実施例>
前述の実施形態に倣って、半導体装置1を作製した。この際、2つのアイランド2のうち、一方のアイランド2の対向端面22に素地領域27を形成し、他方の対向端面22にはめっき膜17を形成した。なお、主要な構成材料は次の通りである。
・アイランド2およびリード3:Cu合金
・めっき膜17:Agめっき膜
・接合材32:Pb−3Sn−1Ag半田
<比較例>
両方のアイランド2の対向端面22にめっき膜17を形成した(対向端面22に素地領域27なし)こと以外は、実施例と同様に半導体装置1を作製した。
<評価>
実施例および比較例で得られた半導体装置の内部の写真を、図12A、図12B、図13Aおよび図13Bに示す。図12Aおよび図12Bが比較例の写真で、図13Aおよび図13Bが実施例の写真である。
これに対して、実施例では、図13Aおよび図13Bに示すように、めっき膜17が形成された対向端面22に、接合材32が濡れ広がっていたものの、隣接するアイランド2へのブリッジは確認されなかった。これは、一方のアイランド2の対向端面22が素地領域27として露出しているところ、Cu合金からなる素地領域27に接合材32が濡れなかったためであると考えられる。
2 アイランド
3 リード
4 半導体チップ
6 樹脂パッケージ
7 第1リード
8 第2リード
13 アイランドサポート部
17 めっき膜
18 第1めっき膜
19 第2めっき膜
21 上面
22 対向端面
23 外側端面
24 第1リード側端面
25 第2リード側端面
26 第1外縁
27 素地領域
28 直線部
29 非直線部
30 第2外縁
31 周縁部
32 接合材
33 はみ出し部
34 マスク
Claims (16)
- 上面および端面を含む外表面を有する複数のアイランドと、
各前記アイランド上の半導体チップと、
前記アイランドと前記半導体チップとの間の接合材と、
前記アイランドの前記外表面に形成されためっき層とを含み、
前記複数のアイランドの少なくとも一つにおいて、当該一つのアイランドの前記端面のうち隣接する前記アイランドと対向する第1端面に、前記アイランドが素地領域として露出しており、
前記アイランドの前記上面において、前記第1端面から所定距離離れたライン上に、前記めっき層の第1外縁が設定されており、
前記素地領域は、前記アイランドの前記第1端面と前記めっき層の前記第1外縁との間にさらに設けられており、
前記アイランドは、4つの前記端面によって区画された平面視四角形状に形成されており、
前記アイランドの上面における前記素地領域は、前記アイランドの前記第1端面に対して一定幅の直線部と、前記直線部の少なくとも長手方向一端部に連なり、前記アイランドの角部において幅が狭くなる非直線部とを含む、半導体装置。 - 前記アイランドの前記第1端面と前記めっき層の前記第1外縁との距離が、150μm〜300μmである、請求項1に記載の半導体装置。
- 前記非直線部は、前記アイランドの内方に湾曲する弓形の前記めっき層の前記第1外縁によって区画されている、請求項1または2に記載の半導体装置。
- 前記アイランドの周囲に配置され、前記アイランドに対して高低差を有するリードを含み、
前記アイランドの前記上面において、前記リード側の第2端面に一致するライン上に、前記めっき層の第2外縁が設定されており、
前記アイランドの前記上面における前記第2端面側の周縁部は、前記めっき層で覆われている、請求項1〜3のいずれか一項に記載の半導体装置。 - 前記アイランドの前記第2端面は、前記めっき層で覆われている、請求項4に記載の半導体装置。
- 前記リードの外表面に形成された第2めっき層をさらに含む、請求項4または5に記載の半導体装置。
- 前記アイランドの前記第1端面とは異なる第3端面に一体的に接続され、前記第3端面から外側に延びるアイランドサポート部をさらに含む、請求項1〜6のいずれか一項に記載の半導体装置。
- 前記アイランドサポート部は、互いに隣接する前記アイランドの両方に設けられており、
一方の前記アイランドサポート部と他方の前記アイランドサポート部とが、同一直線上に延びている、請求項7に記載の半導体装置。 - 互いに隣接する前記アイランド間の距離が、100μm〜200μmである、請求項1〜8のいずれか一項に記載の半導体装置。
- 前記アイランドは、Cuを主成分とする金属材料からなる、請求項1〜9のいずれか一項に記載の半導体装置。
- 前記複数のアイランドおよび前記複数の半導体チップを一括して封止する樹脂パッケージを含む、請求項1〜10のいずれか一項に記載の半導体装置。
- 前記接合材は、前記複数のアイランドの前記上面において、前記上面の端縁の内方領域に収まっている、請求項1〜11のいずれか一項に記載の半導体装置。
- 前記接合材は、前記アイランドと前記半導体チップとの間の領域から外側のはみ出し部を含む、請求項1〜12のいずれか一項に記載の半導体装置。
- 上面および端面を含む外表面を有する複数のアイランド、および前記複数のアイランドの周囲のリードを有するリードフレームを準備する工程と、
前記複数のアイランドの少なくとも一つにおいて、当該一つのアイランドの前記端面のうち隣接する前記アイランドと対向する第1端面側の周縁部にマスクを形成する工程と、
前記マスクを残した状態で、前記アイランドの前記上面にめっき層を形成する工程と、
前記めっき層上に、接合材を介して半導体チップを設置する工程とを含み、
前記マスクを形成する工程は、互いに隣接する前記アイランドの両方の周縁部を一体的に覆うマスクを形成する工程を含む、半導体装置の製造方法。 - 前記マスクを形成する工程は、前記リードフレームにマスキングテープを貼着する工程を含む、請求項14に記載の半導体装置の製造方法。
- 前記マスキングテープは、ポリイミドテープを含む、請求項15に記載の半導体装置の製造方法。
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