KR20090038653A - Ｃｍｏｓ 소자 및 그 제조방법 - Google Patents

Ｃｍｏｓ 소자 및 그 제조방법 Download PDF

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Publication number
KR20090038653A
KR20090038653A KR1020070104062A KR20070104062A KR20090038653A KR 20090038653 A KR20090038653 A KR 20090038653A KR 1020070104062 A KR1020070104062 A KR 1020070104062A KR 20070104062 A KR20070104062 A KR 20070104062A KR 20090038653 A KR20090038653 A KR 20090038653A
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KR
South Korea
Prior art keywords
layer
semiconductor
cmos device
capping
epi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020070104062A
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English (en)
Korean (ko)
Inventor
강동훈
이상문
전중석
백광현
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Priority to KR1020070104062A priority Critical patent/KR20090038653A/ko
Priority to US12/073,308 priority patent/US20090095981A1/en
Priority to CNA2008101297787A priority patent/CN101414608A/zh
Priority to JP2008231438A priority patent/JP2009099956A/ja
Publication of KR20090038653A publication Critical patent/KR20090038653A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/798—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being provided in or under the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/08—Manufacture or treatment characterised by using material-based technologies using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
KR1020070104062A 2007-10-16 2007-10-16 Ｃｍｏｓ 소자 및 그 제조방법 Ceased KR20090038653A (ko)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020070104062A KR20090038653A (ko) 2007-10-16 2007-10-16 Ｃｍｏｓ 소자 및 그 제조방법
US12/073,308 US20090095981A1 (en) 2007-10-16 2008-03-04 Complementary metal oxide semiconductor device and method of manufacturing the same
CNA2008101297787A CN101414608A (zh) 2007-10-16 2008-08-18 互补金属氧化物半导体装置及其制造方法
JP2008231438A JP2009099956A (ja) 2007-10-16 2008-09-09 Ｃｍｏｓ素子及びその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070104062A KR20090038653A (ko) 2007-10-16 2007-10-16 Ｃｍｏｓ 소자 및 그 제조방법

Publications (1)

Publication Number Publication Date
KR20090038653A true KR20090038653A (ko) 2009-04-21

Family

ID=40533314

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070104062A Ceased KR20090038653A (ko) 2007-10-16 2007-10-16 Ｃｍｏｓ 소자 및 그 제조방법

Country Status (4)

Country Link
US (1) US20090095981A1 (https=)
JP (1) JP2009099956A (https=)
KR (1) KR20090038653A (https=)
CN (1) CN101414608A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8575705B2 (en) 2010-01-18 2013-11-05 Samsung Electronics Co., Ltd. Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7790542B2 (en) * 2008-06-18 2010-09-07 International Business Machines Corporation CMOS devices having reduced threshold voltage variations and methods of manufacture thereof
US8395216B2 (en) * 2009-10-16 2013-03-12 Texas Instruments Incorporated Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatus
JP2011114160A (ja) * 2009-11-26 2011-06-09 Sumitomo Chemical Co Ltd 半導体基板、電子デバイスおよび半導体基板の製造方法
JP2011146691A (ja) * 2009-12-15 2011-07-28 Sumitomo Chemical Co Ltd 半導体基板、半導体デバイスおよび半導体基板の製造方法
CN102664166B (zh) * 2012-05-31 2013-11-27 中国科学院上海微系统与信息技术研究所 一种cmos器件及其制作方法
KR102083495B1 (ko) * 2013-01-07 2020-03-02 삼성전자 주식회사 Ｃｍｏｓ 소자와 이를 포함하는 광학장치와 그 제조방법
KR102069275B1 (ko) * 2013-06-07 2020-01-22 삼성전자주식회사 변형된 채널층을 갖는 반도체 소자 및 그 제조 방법
KR102210325B1 (ko) * 2013-09-06 2021-02-01 삼성전자주식회사 Ｃｍｏｓ 소자 및 그 제조 방법
KR102104062B1 (ko) * 2013-10-31 2020-04-23 삼성전자 주식회사 기판 구조체, 이를 포함한 ｃｍｏｓ 소자 및 ｃｍｏｓ 소자 제조 방법
US9418841B2 (en) * 2014-12-30 2016-08-16 International Business Machines Corporation Type III-V and type IV semiconductor device formation
CN104992930A (zh) * 2015-07-07 2015-10-21 西安电子科技大学 应变Ge CMOS集成器件的制备方法及其CMOS集成器件
US9613871B2 (en) 2015-07-16 2017-04-04 Samsung Electronics Co., Ltd. Semiconductor device and fabricating method thereof
CN105118809A (zh) * 2015-08-28 2015-12-02 西安电子科技大学 应变Ge槽型栅CMOS集成器件制备方法及其CMOS集成器件
CN105244320A (zh) * 2015-08-28 2016-01-13 西安电子科技大学 基于SOI的应变Ge沟道倒梯形栅CMOS集成器件及制备方法
US10062693B2 (en) * 2016-02-24 2018-08-28 International Business Machines Corporation Patterned gate dielectrics for III-V-based CMOS circuits
US10593600B2 (en) 2016-02-24 2020-03-17 International Business Machines Corporation Distinct gate stacks for III-V-based CMOS circuits comprising a channel cap
CN108257916B (zh) * 2016-12-28 2020-07-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6254459A (ja) * 1985-09-02 1987-03-10 Seiko Epson Corp 相補型電界効果トランジスタ
JP2000216347A (ja) * 1999-01-20 2000-08-04 Toshiba Corp Ｃｍｏｓ半導体装置
JP4521542B2 (ja) * 1999-03-30 2010-08-11 ルネサスエレクトロニクス株式会社 半導体装置および半導体基板
US7662689B2 (en) * 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7244958B2 (en) * 2004-06-24 2007-07-17 International Business Machines Corporation Integration of strained Ge into advanced CMOS technology
JP4604637B2 (ja) * 2004-10-07 2011-01-05 ソニー株式会社 半導体装置および半導体装置の製造方法
US7282402B2 (en) * 2005-03-30 2007-10-16 Freescale Semiconductor, Inc. Method of making a dual strained channel semiconductor device
TWI258172B (en) * 2005-08-24 2006-07-11 Ind Tech Res Inst Transistor device with strained Ge layer by selectively grown and fabricating method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8575705B2 (en) 2010-01-18 2013-11-05 Samsung Electronics Co., Ltd. Semiconductor devices including MOS transistors having an optimized channel region and methods of fabricating the same

Also Published As

Publication number Publication date
JP2009099956A (ja) 2009-05-07
US20090095981A1 (en) 2009-04-16
CN101414608A (zh) 2009-04-22

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