KR20080043239A - 유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기 - Google Patents

유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기 Download PDF

Info

Publication number
KR20080043239A
KR20080043239A KR1020070114744A KR20070114744A KR20080043239A KR 20080043239 A KR20080043239 A KR 20080043239A KR 1020070114744 A KR1020070114744 A KR 1020070114744A KR 20070114744 A KR20070114744 A KR 20070114744A KR 20080043239 A KR20080043239 A KR 20080043239A
Authority
KR
South Korea
Prior art keywords
film
organic ferroelectric
forming
crystallinity
ferroelectric film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020070114744A
Other languages
English (en)
Korean (ko)
Inventor
히로시 다키구치
준이치 가라사와
Original Assignee
세이코 엡슨 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 세이코 엡슨 가부시키가이샤 filed Critical 세이코 엡슨 가부시키가이샤
Publication of KR20080043239A publication Critical patent/KR20080043239A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0415Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having ferroelectric gate insulators
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/689Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having ferroelectric layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90Thermal treatments, e.g. annealing or sintering

Landscapes

  • Semiconductor Memories (AREA)
  • Insulating Bodies (AREA)
  • Manufacture Of Macromolecular Shaped Articles (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)
KR1020070114744A 2006-11-13 2007-11-12 유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기 Withdrawn KR20080043239A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JPJP-P-2006-00307153 2006-11-13
JP2006307153 2006-11-13
JP2007290164A JP2008147632A (ja) 2006-11-13 2007-11-07 有機強誘電体膜の形成方法、記憶素子の製造方法、記憶装置、および電子機器
JPJP-P-2007-00290164 2007-11-07

Publications (1)

Publication Number Publication Date
KR20080043239A true KR20080043239A (ko) 2008-05-16

Family

ID=39480511

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070114744A Withdrawn KR20080043239A (ko) 2006-11-13 2007-11-12 유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기

Country Status (3)

Country Link
JP (1) JP2008147632A (https=)
KR (1) KR20080043239A (https=)
CN (1) CN101188198A (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101276560B1 (ko) * 2011-03-17 2013-06-24 한국과학기술원 강유전체 폴리머 나노도트 소자 및 그 제조를 위한 디웨팅 프로세스

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5957648B2 (ja) * 2009-09-14 2016-07-27 株式会社イデアルスター フッ化ビニリデンと、トリフルオロエチレン又はテトラフルオロエチレンとの共重合体とフラーレンとの混合膜及びその製造方法
JP2011159848A (ja) * 2010-02-02 2011-08-18 Toshiba Corp 固体撮像装置およびその製造方法
JP5926903B2 (ja) * 2011-08-22 2016-05-25 株式会社クレハ 所望のキュリー温度を有するポリマーの製造方法
CN103999207B (zh) * 2011-11-09 2017-07-28 国立研究开发法人科学技术振兴机构 固体电子装置
WO2014158956A1 (en) * 2013-03-14 2014-10-02 Saudi Basic Industries Corporation Ferroelectric capacitor with improved fatigue and breakdown properties
JP6229532B2 (ja) * 2014-02-21 2017-11-15 国立研究開発法人産業技術総合研究所 有機強誘電体薄膜の製造方法
JP2016171152A (ja) * 2015-03-12 2016-09-23 ペクセル・テクノロジーズ株式会社 ペロブスカイト化合物を用いた強誘電体メモリ素子およびその製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101276560B1 (ko) * 2011-03-17 2013-06-24 한국과학기술원 강유전체 폴리머 나노도트 소자 및 그 제조를 위한 디웨팅 프로세스

Also Published As

Publication number Publication date
CN101188198A (zh) 2008-05-28
JP2008147632A (ja) 2008-06-26

Similar Documents

Publication Publication Date Title
KR20080043239A (ko) 유기 강유전체막의 형성 방법, 기억 소자의 제조 방법,기억 장치, 및 전자 기기
TWI447980B (zh) A transistor, an organic semiconductor element, and the like
US7485576B2 (en) Method of forming conductive pattern, thin film transistor, and method of manufacturing the same
JP4867168B2 (ja) 有機薄膜トランジスタの製造方法
US7935961B2 (en) Multi-layered bipolar field-effect transistor and method of manufacturing the same
JP4938974B2 (ja) 有機薄膜トランジスター
KR20160112030A (ko) 듀얼게이트 박막트랜지스터
JP2007258282A (ja) 半導体装置、半導体装置の製造方法および記憶装置
US20090258443A1 (en) Nonvolatile memory devices and methods of fabricating the same
US20070281372A1 (en) Memory element, method for manufacturing memory element, memory device, electronic apparatus and method for manufacturing transistor
US20100022032A1 (en) Method of forming organic ferroelectric film, method of manufacturing memory element, memory device, and electronic apparatus
KR100889020B1 (ko) 다층 구조의 게이트 절연체를 포함하는 박막 트랜지스터
JP2003309265A (ja) 有機薄膜トランジスタ及び有機薄膜トランジスタの製造方法
JP2009295678A (ja) 半導体装置の製造方法、強誘電体素子の製造方法および電子機器の製造方法
JP2004055649A (ja) 有機薄膜トランジスタ及びその製造方法
JP2007173728A (ja) 有機強誘電体キャパシタの製造方法、有機強誘電体キャパシタ、有機強誘電体メモリ、および電子機器
WO2014136436A1 (ja) 有機薄膜トランジスタ及びその製造方法
JP2010141141A (ja) 薄膜トランジスタおよびその製造方法、並びに表示装置
JP2007134354A (ja) 有機強誘電体キャパシタの製造方法、有機強誘電体キャパシタ、有機強誘電体メモリ、および電子機器
JP5630364B2 (ja) 有機半導体素子の製造方法および有機半導体素子
JP5724529B2 (ja) 半導体装置の製造方法、強誘電体素子の製造方法および電子機器の製造方法
JP4345317B2 (ja) 有機薄膜トランジスタ素子
JP5223294B2 (ja) 有機薄膜トランジスタの製造方法
JP2008198804A (ja) 有機強誘電体メモリの製造方法、有機強誘電体キャパシタ、有機強誘電体メモリ、および電子機器
JP2008251575A (ja) 有機薄膜トランジスタの形成方法、及び有機薄膜トランジスタ

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

PC1203 Withdrawal of no request for examination

St.27 status event code: N-1-6-B10-B12-nap-PC1203

WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid
R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000