KR20080003706A - 액정표시장치의 기판 및 그 제조방법 - Google Patents
액정표시장치의 기판 및 그 제조방법 Download PDFInfo
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- KR20080003706A KR20080003706A KR1020070049174A KR20070049174A KR20080003706A KR 20080003706 A KR20080003706 A KR 20080003706A KR 1020070049174 A KR1020070049174 A KR 1020070049174A KR 20070049174 A KR20070049174 A KR 20070049174A KR 20080003706 A KR20080003706 A KR 20080003706A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
- H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Nonlinear Science (AREA)
- Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Crystallography & Structural Chemistry (AREA)
- Mathematical Physics (AREA)
- Manufacturing & Machinery (AREA)
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (20)
- (a) 기판을 제공하는 단계;(b) 복수의 노치들을 가진 패턴화된 제1 절연층을 상기 기판의 표면에 형성하는 단계;(c) 버퍼층을 형성하여 상기 제1 절연층과 상기 노치들의 표면을 덮는 단계;(d) 상기 버퍼층을 패터닝하여 상기 노치들의 표면 위에 패턴화된 버퍼층을 남기는 단계;(e) 제1 금속층을 디포지트하여 상기 제1 절연층의 노치들 내부에 소스와 드레인을 각각 형성하는 단계;(f) 상기 제1 절연층 위에 상기 소스 및 드레인과 접촉되는 패턴화된 반도체층을 형성하는 단계;(g) 상기 반도체층의 표면 위에 제2 절연층을 형성하는 단계; 및(h) 상기 제2 절연층 위에 제2 금속층을 패터닝하는 단계;를 포함하는 액정표시장치의 기판 제조방법.
- 제1항에 있어서,(i) 패턴화된 보호층을 형성하여 상기 제2 금속층의 표면을 덮는 단계;를 더 포함하는 액정표시장치의 기판 제조방법.
- 제1항에 있어서,상기 단계 (e) 이후에, 소스와 드레인의 표면을 어닐링하여 그 위에 장벽층을 형성하는 단계를 더 포함하는 액정표시장치의 기판 제조방법.
- 제3항에 있어서,상기 장벽층이 금속 규소 화합물을 포함하는 액정표시장치의 기판 제조방법.
- 제1항에 있어서,상기 반도체층이 비정질 실리콘층 또는 다결정 실리콘층을 형성하는 액정표시장치의 기판 제조방법.
- 제1항에 있어서,상기 단계 (f)는, 상기 제1 절연층의 표면 위에 비정질 실리콘층을 디포지트하고, 상기 비정질 실리콘층을 결정화하여 다결정 실리콘층으로 변환하고, 상기 다결정 실리콘층을 패터닝함으로써 수행되는 액정표시장치의 기판 제조방법.
- 제1항에 있어서,상기 반도체층은 단일층 구조 또는 다층 구조를 포함하는 액정표시장치의 기판 제조방법.
- 제1항에 있어서, 상기 단계 (g) 이후에,(g1) 이온 첨가물들을 반도체층에 주입하여 N형 또는 P형 반도체층을 형성하는 단계;를 더 포함하는 액정표시장치의 기판 제조방법.
- 제8항에 있어서,상기 이온 첨가물들은 붕소 이온 또는 인 이온을 포함하는 액정표시장치의 기판 제조방법.
- 제1항에 있어서,상기 버퍼층의 물질은 실리카(SiOx), 질화실리콘(SiNx), 질화티타늄(TiOx), 질화탄탈륨(TaN) 또는 이들의 조합인 것인 액정표시장치의 기판 제조방법.
- 제1항에 있어서, 상기 단계 (e)와 단계 (f) 사이에,(e1) 상기 제1 절연층의 표면 위에 패턴화된 투명 도전층을 형성하고, 상기 투명 도전층을 상기 드레인과 접촉시키는 단계;를 더 포함하는 액정표시장치의 기판 제조방법.
- 제1항에 있어서,상기 투명 전도층을 노출시키도록 상기 제2 절연층이 패턴화되는 액정표시장 치의 기판 제조방법.
- 제1항에 있어서,상기 제1 금속층이 구리, 은, 금 또는 이들의 조합을 포함하는 액정표시장치의 기판 제조방법.
- 제1항에 있어서,상기 단계 (e)가, 상기 소스와 드레인의 표면을 상기 제1 절연층과 동일한 높이로 형성함으로써 수행되는 액정표시장치의 기판 제조방법.
- 제14항에 있어서,상기 단계 (e)에서, 상기 제1 절연층과 상기 노치들의 표면 위에 상기 제1 금속층을 도금으로 디포지트하고, 상기 제1 절연층과 제1 금속층을 평탄화하는 화학적 기계적 연마나 습식식각이 수행되어 상기 소스와 드레인을 형성하는 액정표시장치의 기판 제조방법.
- 제15항에 있어서,상기 도금 공정은 전기도금, 무전해도금, 화학적 도금 또는 자동촉매 도금 공정을 포함하는 액정표시장치의 기판 제조방법.
- 기판;복수의 노치들을 가지고 상기 기판의 표면에 형성된 패턴화된 제1 절연층;상기 제1 절연층의 표면과 상기 노치들의 표면 위에 형성되되, 상기 노치들이 제1 금속층으로 채워져서 소스와 드레인을 각각 형성하는 패턴화된 버퍼층;상기 제1 절연층 위에서 상기 소스와 상기 드레인에 접촉되고, 이온 첨가물이 선택적으로 주입되어 N형 또는 P형 반도체층을 형성하는 패턴화된 반도체층;상기 반도체층의 표면 위에 형성된 제2 절연층; 및상기 제2 절연층 위에 형성된 제2 금속층;을 포함하는 액정표시장치의 기판.
- 제17항에 있어서,상기 버퍼층은 실리카(SiOx), 질화실리콘(SiNx), 질화티타늄(TiNx), 질화탄탈륨(TaN) 또는 이들의 조합을 포함하는 액정표시장치의 기판.
- 제17항에 있어서,상기 소스와 드레인의 표면 위에 형성된 장벽층을 더 포함하는 액정표시장치의 기판.
- 제19항에 있어서,상기 장벽층이 금속 규소 화합물을 포함하는 액정표시장치의 기판.
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