KR20070026630A - Ｄｒａｍ의 자동 히든 리프레시 및 그 방법 - Google Patents

Ｄｒａｍ의 자동 히든 리프레시 및 그 방법 Download PDF

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Publication number
KR20070026630A
KR20070026630A KR1020067026957A KR20067026957A KR20070026630A KR 20070026630 A KR20070026630 A KR 20070026630A KR 1020067026957 A KR1020067026957 A KR 1020067026957A KR 20067026957 A KR20067026957 A KR 20067026957A KR 20070026630 A KR20070026630 A KR 20070026630A
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KR
South Korea
Prior art keywords
memory
refresh
address
data
banks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020067026957A
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English (en)
Korean (ko)
Inventor
페리 에이치 펠리
Original Assignee
프리스케일 세미컨덕터, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프리스케일 세미컨덕터, 인크. filed Critical 프리스케일 세미컨덕터, 인크.
Publication of KR20070026630A publication Critical patent/KR20070026630A/ko
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40607—Refresh operations in memory devices with an internal cache or data buffer
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40618—Refresh operations over multiple banks or interleaving
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40626—Temperature related aspects of refresh operations
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Dram (AREA)
KR1020067026957A 2004-05-26 2005-04-28 Ｄｒａｍ의 자동 히든 리프레시 및 그 방법 Ceased KR20070026630A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/854,298 2004-05-26
US10/854,298 US7088632B2 (en) 2004-05-26 2004-05-26 Automatic hidden refresh in a dram and method therefor

Publications (1)

Publication Number Publication Date
KR20070026630A true KR20070026630A (ko) 2007-03-08

Family

ID=35460387

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020067026957A Ceased KR20070026630A (ko) 2004-05-26 2005-04-28 Ｄｒａｍ의 자동 히든 리프레시 및 그 방법

Country Status (8)

Country Link
US (1) US7088632B2 (enExample)
EP (2) EP1751762B1 (enExample)
JP (1) JP2008500675A (enExample)
KR (1) KR20070026630A (enExample)
CN (1) CN100568378C (enExample)
AT (1) ATE465492T1 (enExample)
DE (1) DE602005020772D1 (enExample)
WO (1) WO2005119687A2 (enExample)

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US6563746B2 (en) * 1999-11-09 2003-05-13 Fujitsu Limited Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode
US7313047B2 (en) * 2006-02-23 2007-12-25 Hynix Semiconductor Inc. Dynamic semiconductor memory with improved refresh mechanism
KR100850207B1 (ko) * 2006-12-29 2008-08-04 삼성전자주식회사 시스터메틱 코드 발생을 위한 듀얼 클럭킹 방법을 채용한메모리 장치
US8352772B2 (en) * 2007-05-25 2013-01-08 Rambus Inc. Reference clock and command word alignment
CN101404581B (zh) * 2007-10-11 2011-01-12 硅谷数模半导体（北京）有限公司 以太网物理层器件的控制方法
KR20110018947A (ko) * 2008-06-17 2011-02-24 엔엑스피 비 브이 전기 회로, 방법 및 동적 랜덤 액세스 메모리
EP2529374A4 (en) * 2010-01-28 2014-04-02 Hewlett Packard Development Co STORAGE ACCESS AND METHOD
US20110320699A1 (en) * 2010-06-24 2011-12-29 International Business Machines Corporation System Refresh in Cache Memory
JP2012038399A (ja) * 2010-08-11 2012-02-23 Elpida Memory Inc 半導体装置
JP6031745B2 (ja) 2011-10-17 2016-11-24 ソニー株式会社 送信装置、送信方法および受信装置
KR20130042236A (ko) * 2011-10-18 2013-04-26 에스케이하이닉스 주식회사 메모리 시스템
US9230046B2 (en) 2012-03-30 2016-01-05 International Business Machines Corporation Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
US9286423B2 (en) 2012-03-30 2016-03-15 International Business Machines Corporation Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator
JP5323238B1 (ja) * 2012-05-18 2013-10-23 株式会社東芝 信号送信装置及び信号送信方法
US9286964B2 (en) 2012-12-21 2016-03-15 Intel Corporation Method, apparatus and system for responding to a row hammer event
US20150003172A1 (en) * 2013-06-26 2015-01-01 Sua KIM Memory module including buffer chip controlling refresh operation of memory devices
KR102171260B1 (ko) * 2013-06-26 2020-10-28 삼성전자 주식회사 리프레쉬 동작을 제어하는 버퍼 칩을 장착하는 메모리 모듈
US8982654B2 (en) 2013-07-05 2015-03-17 Qualcomm Incorporated DRAM sub-array level refresh
US9842630B2 (en) * 2013-10-16 2017-12-12 Rambus Inc. Memory component with adjustable core-to-interface data rate ratio
KR102130611B1 (ko) 2013-12-31 2020-07-06 삼성전자주식회사 아날로그-디지털 변환 회로, 이를 포함하는 이미지 센서 및 이미지 센서의 동작 방법
KR20160132243A (ko) * 2015-05-08 2016-11-17 에스케이하이닉스 주식회사 반도체 메모리 장치
US9928895B2 (en) * 2016-02-03 2018-03-27 Samsung Electronics Co., Ltd. Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof
US9824742B1 (en) 2016-04-28 2017-11-21 Qualcomm Incorporated DRAM access in self-refresh state
EP3901952B1 (en) * 2016-10-31 2023-06-07 Intel Corporation Applying chip select for memory device identification and power management control
US10497420B1 (en) * 2018-05-08 2019-12-03 Micron Technology, Inc. Memory with internal refresh rate control
DE102020133713A1 (de) * 2020-02-27 2021-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Speicheraktualisierung
CN116862756B (zh) * 2023-09-05 2023-12-19 广东匠芯创科技有限公司 行数据处理方法、行缓存器、电子设备及存储介质
US12265732B1 (en) * 2023-09-29 2025-04-01 Advanced Micro Devices, Inc. Refresh during power state changes

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US4691303A (en) * 1985-10-31 1987-09-01 Sperry Corporation Refresh system for multi-bank semiconductor memory
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US5418920A (en) * 1992-04-30 1995-05-23 Alcatel Network Systems, Inc. Refresh control method and system including request and refresh counters and priority arbitration circuitry
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JPH08315569A (ja) * 1995-05-16 1996-11-29 Hitachi Ltd 半導体記憶装置、及びデータ処理装置
JPH09106674A (ja) * 1995-10-12 1997-04-22 Fujitsu Ltd 同期型ダイナミック半導体記憶装置
JPH10247384A (ja) * 1997-03-03 1998-09-14 Mitsubishi Electric Corp 同期型半導体記憶装置
US5870350A (en) * 1997-05-21 1999-02-09 International Business Machines Corporation High performance, high bandwidth memory bus architecture utilizing SDRAMs
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JPH11339469A (ja) * 1998-05-26 1999-12-10 Hitachi Ltd 半導体記憶装置
US6504780B2 (en) * 1998-10-01 2003-01-07 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a dram device using clock division
US6707743B2 (en) * 1998-10-01 2004-03-16 Monolithic System Technology, Inc. Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division
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JP3531592B2 (ja) * 2000-07-21 2004-05-31 セイコーエプソン株式会社 半導体装置及び電子機器
CN1184644C (zh) * 2001-03-16 2005-01-12 矽统科技股份有限公司 存储器刷新系统
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DE10214102B4 (de) * 2002-03-28 2007-08-09 Infineon Technologies Ag Digitale Begrenzung der Selfrefreshfrequenz für temperaturabhängige Selfrefreshoszillatoren

Also Published As

Publication number Publication date
CN1957422A (zh) 2007-05-02
EP2207184A1 (en) 2010-07-14
EP1751762B1 (en) 2010-04-21
US7088632B2 (en) 2006-08-08
WO2005119687A2 (en) 2005-12-15
JP2008500675A (ja) 2008-01-10
DE602005020772D1 (de) 2010-06-02
WO2005119687A3 (en) 2006-05-26
ATE465492T1 (de) 2010-05-15
EP1751762A4 (en) 2008-05-14
EP1751762A2 (en) 2007-02-14
CN100568378C (zh) 2009-12-09
US20050276142A1 (en) 2005-12-15

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