ATE465492T1 - Automatisches verborgenes auffrischen in einem dram und verfahren dafür - Google Patents
Automatisches verborgenes auffrischen in einem dram und verfahren dafürInfo
- Publication number
- ATE465492T1 ATE465492T1 AT05742846T AT05742846T ATE465492T1 AT E465492 T1 ATE465492 T1 AT E465492T1 AT 05742846 T AT05742846 T AT 05742846T AT 05742846 T AT05742846 T AT 05742846T AT E465492 T1 ATE465492 T1 AT E465492T1
- Authority
- AT
- Austria
- Prior art keywords
- memory
- dram
- burst operation
- hidden refresh
- automatic hidden
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40618—Refresh operations over multiple banks or interleaving
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40607—Refresh operations in memory devices with an internal cache or data buffer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40626—Temperature related aspects of refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/854,298 US7088632B2 (en) | 2004-05-26 | 2004-05-26 | Automatic hidden refresh in a dram and method therefor |
PCT/US2005/014786 WO2005119687A2 (en) | 2004-05-26 | 2005-04-28 | Automatic hidden refresh in a dram and method therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE465492T1 true ATE465492T1 (de) | 2010-05-15 |
Family
ID=35460387
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT05742846T ATE465492T1 (de) | 2004-05-26 | 2005-04-28 | Automatisches verborgenes auffrischen in einem dram und verfahren dafür |
Country Status (8)
Country | Link |
---|---|
US (1) | US7088632B2 (de) |
EP (2) | EP1751762B1 (de) |
JP (1) | JP2008500675A (de) |
KR (1) | KR20070026630A (de) |
CN (1) | CN100568378C (de) |
AT (1) | ATE465492T1 (de) |
DE (1) | DE602005020772D1 (de) |
WO (1) | WO2005119687A2 (de) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6563746B2 (en) * | 1999-11-09 | 2003-05-13 | Fujitsu Limited | Circuit for entering/exiting semiconductor memory device into/from low power consumption mode and method of controlling internal circuit at low power consumption mode |
US7313047B2 (en) * | 2006-02-23 | 2007-12-25 | Hynix Semiconductor Inc. | Dynamic semiconductor memory with improved refresh mechanism |
KR100850207B1 (ko) * | 2006-12-29 | 2008-08-04 | 삼성전자주식회사 | 시스터메틱 코드 발생을 위한 듀얼 클럭킹 방법을 채용한메모리 장치 |
WO2008153652A2 (en) * | 2007-05-25 | 2008-12-18 | Rambus Inc. | Reference clock and command word alignment |
CN101404581B (zh) * | 2007-10-11 | 2011-01-12 | 硅谷数模半导体(北京)有限公司 | 以太网物理层器件的控制方法 |
WO2009153736A1 (en) * | 2008-06-17 | 2009-12-23 | Nxp B.V. | Electrical circuit comprising a dynamic random access memory (dram) with concurrent refresh and read or write, and method to perform concurrent refresh and read or write in such a memory |
EP2529374A4 (de) * | 2010-01-28 | 2014-04-02 | Hewlett Packard Development Co | Speicherzugangsverfahren und -vorrichtung |
US20110320699A1 (en) * | 2010-06-24 | 2011-12-29 | International Business Machines Corporation | System Refresh in Cache Memory |
JP2012038399A (ja) * | 2010-08-11 | 2012-02-23 | Elpida Memory Inc | 半導体装置 |
JP6031745B2 (ja) * | 2011-10-17 | 2016-11-24 | ソニー株式会社 | 送信装置、送信方法および受信装置 |
KR20130042236A (ko) * | 2011-10-18 | 2013-04-26 | 에스케이하이닉스 주식회사 | 메모리 시스템 |
US9286423B2 (en) | 2012-03-30 | 2016-03-15 | International Business Machines Corporation | Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator |
US9230046B2 (en) | 2012-03-30 | 2016-01-05 | International Business Machines Corporation | Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator |
JP5323238B1 (ja) * | 2012-05-18 | 2013-10-23 | 株式会社東芝 | 信号送信装置及び信号送信方法 |
US9286964B2 (en) | 2012-12-21 | 2016-03-15 | Intel Corporation | Method, apparatus and system for responding to a row hammer event |
KR102171260B1 (ko) * | 2013-06-26 | 2020-10-28 | 삼성전자 주식회사 | 리프레쉬 동작을 제어하는 버퍼 칩을 장착하는 메모리 모듈 |
US20150003172A1 (en) * | 2013-06-26 | 2015-01-01 | Sua KIM | Memory module including buffer chip controlling refresh operation of memory devices |
US8982654B2 (en) | 2013-07-05 | 2015-03-17 | Qualcomm Incorporated | DRAM sub-array level refresh |
US9842630B2 (en) * | 2013-10-16 | 2017-12-12 | Rambus Inc. | Memory component with adjustable core-to-interface data rate ratio |
KR102130611B1 (ko) | 2013-12-31 | 2020-07-06 | 삼성전자주식회사 | 아날로그-디지털 변환 회로, 이를 포함하는 이미지 센서 및 이미지 센서의 동작 방법 |
KR20160132243A (ko) * | 2015-05-08 | 2016-11-17 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
US9928895B2 (en) * | 2016-02-03 | 2018-03-27 | Samsung Electronics Co., Ltd. | Volatile memory device and electronic device comprising refresh information generator, information providing method thereof, and refresh control method thereof |
US9824742B1 (en) | 2016-04-28 | 2017-11-21 | Qualcomm Incorporated | DRAM access in self-refresh state |
EP3901952B1 (de) * | 2016-10-31 | 2023-06-07 | Intel Corporation | Anwendung einer chipauswahl zur identifizierung einer speichervorrichtung und leistungsverwaltungssteuerung |
US10497420B1 (en) * | 2018-05-08 | 2019-12-03 | Micron Technology, Inc. | Memory with internal refresh rate control |
DE102020133713A1 (de) * | 2020-02-27 | 2021-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Speicheraktualisierung |
CN116862756B (zh) * | 2023-09-05 | 2023-12-19 | 广东匠芯创科技有限公司 | 行数据处理方法、行缓存器、电子设备及存储介质 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4691303A (en) * | 1985-10-31 | 1987-09-01 | Sperry Corporation | Refresh system for multi-bank semiconductor memory |
US5193165A (en) * | 1989-12-13 | 1993-03-09 | International Business Machines Corporation | Memory card refresh buffer |
JP3532932B2 (ja) | 1991-05-20 | 2004-05-31 | モトローラ・インコーポレイテッド | 時間重複メモリ・アクセスを有するランダムにアクセス可能なメモリ |
JPH0589672A (ja) | 1991-09-30 | 1993-04-09 | Casio Comput Co Ltd | リフレツシユ信号発生回路 |
US5418920A (en) * | 1992-04-30 | 1995-05-23 | Alcatel Network Systems, Inc. | Refresh control method and system including request and refresh counters and priority arbitration circuitry |
JPH07169266A (ja) * | 1993-12-15 | 1995-07-04 | Matsushita Electric Ind Co Ltd | 半導体メモリ |
KR0171930B1 (ko) * | 1993-12-15 | 1999-03-30 | 모리시다 요이치 | 반도체 메모리, 동화기억 메모리, 동화기억장치, 동화표시장치, 정지화기억 메모리 및 전자노트 |
JPH08315569A (ja) * | 1995-05-16 | 1996-11-29 | Hitachi Ltd | 半導体記憶装置、及びデータ処理装置 |
JPH09106674A (ja) * | 1995-10-12 | 1997-04-22 | Fujitsu Ltd | 同期型ダイナミック半導体記憶装置 |
JPH10247384A (ja) * | 1997-03-03 | 1998-09-14 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
US5870350A (en) * | 1997-05-21 | 1999-02-09 | International Business Machines Corporation | High performance, high bandwidth memory bus architecture utilizing SDRAMs |
US6442644B1 (en) | 1997-08-11 | 2002-08-27 | Advanced Memory International, Inc. | Memory system having synchronous-link DRAM (SLDRAM) devices and controller |
JPH11339469A (ja) * | 1998-05-26 | 1999-12-10 | Hitachi Ltd | 半導体記憶装置 |
US6707743B2 (en) * | 1998-10-01 | 2004-03-16 | Monolithic System Technology, Inc. | Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division |
US6504780B2 (en) * | 1998-10-01 | 2003-01-07 | Monolithic System Technology, Inc. | Method and apparatus for completely hiding refresh operations in a dram device using clock division |
US6226755B1 (en) | 1999-01-26 | 2001-05-01 | Compaq Computer Corp. | Apparatus and method for enhancing data transfer to or from a SDRAM system |
JP2000260180A (ja) * | 1999-03-08 | 2000-09-22 | Nec Corp | 半導体メモリ |
US6188627B1 (en) * | 1999-08-13 | 2001-02-13 | International Business Machines Corporation | Method and system for improving DRAM subsystem performance using burst refresh control |
JP3398098B2 (ja) * | 1999-09-03 | 2003-04-21 | 株式会社小池メディカル | 液状廃棄物の処理装置用フロ―ト |
JP3531592B2 (ja) * | 2000-07-21 | 2004-05-31 | セイコーエプソン株式会社 | 半導体装置及び電子機器 |
JP2003030983A (ja) * | 2001-07-13 | 2003-01-31 | Mitsubishi Electric Corp | ダイナミック型半導体記憶装置 |
DE10214102B4 (de) * | 2002-03-28 | 2007-08-09 | Infineon Technologies Ag | Digitale Begrenzung der Selfrefreshfrequenz für temperaturabhängige Selfrefreshoszillatoren |
-
2004
- 2004-05-26 US US10/854,298 patent/US7088632B2/en active Active
-
2005
- 2005-04-28 WO PCT/US2005/014786 patent/WO2005119687A2/en not_active Application Discontinuation
- 2005-04-28 DE DE602005020772T patent/DE602005020772D1/de active Active
- 2005-04-28 EP EP05742846A patent/EP1751762B1/de active Active
- 2005-04-28 EP EP10155879A patent/EP2207184A1/de not_active Withdrawn
- 2005-04-28 KR KR1020067026957A patent/KR20070026630A/ko not_active Application Discontinuation
- 2005-04-28 CN CNB2005800168872A patent/CN100568378C/zh active Active
- 2005-04-28 JP JP2007515104A patent/JP2008500675A/ja active Pending
- 2005-04-28 AT AT05742846T patent/ATE465492T1/de not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP2008500675A (ja) | 2008-01-10 |
EP1751762B1 (de) | 2010-04-21 |
US20050276142A1 (en) | 2005-12-15 |
DE602005020772D1 (de) | 2010-06-02 |
WO2005119687A2 (en) | 2005-12-15 |
CN1957422A (zh) | 2007-05-02 |
EP1751762A4 (de) | 2008-05-14 |
EP1751762A2 (de) | 2007-02-14 |
EP2207184A1 (de) | 2010-07-14 |
KR20070026630A (ko) | 2007-03-08 |
WO2005119687A3 (en) | 2006-05-26 |
US7088632B2 (en) | 2006-08-08 |
CN100568378C (zh) | 2009-12-09 |
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Legal Events
Date | Code | Title | Description |
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RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |