KR20040047835A - 이진모드에서 다중상태 비휘발성 메모리 시스템의 선택적작동 - Google Patents
이진모드에서 다중상태 비휘발성 메모리 시스템의 선택적작동 Download PDFInfo
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- KR20040047835A KR20040047835A KR10-2004-7003923A KR20047003923A KR20040047835A KR 20040047835 A KR20040047835 A KR 20040047835A KR 20047003923 A KR20047003923 A KR 20047003923A KR 20040047835 A KR20040047835 A KR 20040047835A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5628—Programming or writing circuits; Data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/5641—Multilevel memory having cells with different number of storage levels
Abstract
Description
Claims (12)
- 적어도 4개의 문턱레벨 상태들이나 정확히 2개의 문턱레벨 상태들에서 비휘발성 메모리 셀들의 다수의 블록들을 제어 가능하게 작동시키는 방법으로서, 상기 적어도 4개의 문턱레벨 상태들은 메모리 셀 작동 문턱 윈도우를 가로질러 이격되고, 상기 정확히 2개의 문턱레벨 상태들은 4개의 문턱레벨 상태들 중 상기 작동 문턱 윈도우 내에서 서로 최대한으로 떨어진 것들인 것을 특징으로 하는 작동 방법.
- 제1항에 있어서, 상기 다수의 블록들 중 적어도 하나 내의 상기 메모리 셀들은 상기 정확히 2개의 문턱레벨 상태들에서 작동되고, 상기 다수의 블록들 중 적어도 다른 하나 내의 메모리 셀들은 상기 적어도 4개의 문턱레벨 상태들에서 작동되는 것을 특징으로 하는 작동 방법.
- 제2항에 있어서, 사용자 데이터가 저장되는 메모리 블록들의 표가 상기 정확히 2개의 문턱레벨에서 작동되는 상기 다수의 블록들 중 상기 적어도 하나 내의 메모리 셀들에 기록되고, 상기 사용자 데이터는 상기 적어도 4개의 문턱레벨 상태들에서 작동되는 상기 다수의 블록들 중 상기 적어도 다른 하나 내의 메모리 셀들에 저장되는 것을 특징으로 하는 작동 방법.
- 제1항에 있어서, 메모리 셀들의 상기 다수의 블록들 중 적어도 하나는 상기적어도 하나의 블록의 다수의 삭제/프로그래밍 사이클이 예정된 양에 도달하여 상기 적어도 하나의 블록이 상기 적어도 2개의 문턱레벨 상태들에서 작동될 때까지 상기 적어도 4개의 문턱레벨 상태들에서 처음으로 작동되는 것을 특징으로 하는 작동 방법.
- 작동 문턱 윈도우를 가로질러 이격되는 적어도 4개의 문턱레벨 상태들 중 하나에서 1 비트 이상의 데이터를 개별적으로 저장하는 비휘발성 메모리 셀들의 다수의 블록들을 가진 메모리 시스템에서, 작동 문턱 윈도우 내에서 서로 가장 멀리 환치되는 상기 적어도 4개의 문턱레벨 상태들 중 단지 2개에서 적어도 하나의 블록들의 메모리 셀들에 1 비트의 데이터를 저장하는 것을 포함하는 메모리 시스템을 작동하는 방법.
- 제5항에 있어서, 상기 방법은 서로 가장 멀리 환치된 상기 단지 2개의 문턱레벨 상태들보다 상기 적어도 4개의 문턱레벨 상태들 중 다른 것들의 중간 값을 가진 문턱기준을 사용하여 4개의 문턱레벨 상태들 중 상기 단지 2개에 저장되는 상기 적어도 일부의 블록들의 개개의 셀들로부터 데이터를 읽는 것을 추가적으로 포함하는 작동 방법.
- 제6항에 있어서, 서로 가장 멀리 환치된 상기 단지 2개의 문턱레벨 상태들 중 하나는 작동 문턱 윈도우의 음(negative) 영역 내에서 삭제된 상태이고, 상기읽기 문턱 기준은 영이 아닌 양(positive) 전압인 것을 특징으로 하는 작동 방법.
- 제5항에 있어서, 상기 메모리 시스템은 NAND 시스템인 것을 특징으로 하는 작동 방법.
- NAND 배열에서 연결된 메모리 셀들을 가진 플래시 비휘발성 메모리 시스템에서, 적어도 2개의 비트가 적어도 2개의 서로 다른 데이터의 페이지들로부터 메모리 셀들 중 개개의 것들로 정규로 프로그램되고, 한 비트만을 시스템의 메모리 셀들의 일부로 프로그래밍하는 방법은 상기 적어도 2개의 페이지들 중 하나로부터 한 비트를, 상기 적어도 2개의 페이지들 중 다른 것으로부터 두 번째 비트를 프로그래밍하지 않고 2개의 비트 중 하나로서 정규로 프로그램될 때와 같은 방식으로, 상기 시스템의 메모리의 상기 일부 중 개개의 것들로 프로그래밍하는 것을 포함하는 것을 특징으로 하는 메모리 시스템.
- 제9항에 있어서, 상기 적어도 2개의 비트는 메모리 셀들의 작동 문턱 윈도우를 가로지르는 적어도 4개의 문턱레벨 상태들에서 정규로 프로그램되고, 한 비트만을 메모리 셀들의 상기 일부 중 개개의 것들로 프로그래밍하는 방법은 개개의 메모리 셀들의 작동 문턱 윈도우 내에서 서로 최대로 이격되는 4개의 문턱레벨 상태들 중 2개만을 이용하는 것을 추가적으로 포함하는 것을 특징으로 하는 메모리 시스템.
- 제10항에 있어서, 상기 적어도 2개의 비트는 작동 문턱 윈도우를 가로질러 연장되는 검증레벨들과 관련하여 상기 4개의 문턱레벨 상태들 중 적어도 일부로 정규로 프로그램되고, 한 비트만을 메모리 셀들의 상기 일부 중 개개의 것들로 프로그래밍하는 방법은 상기 검즐레벨들의 최대값을 사용하여 그렇게 하는 것을 추가적으로 포함하는 것을 특징으로 하는 메모리 시스템.
- 제1항에 있어서, 개개의 블록들의 메모리 셀들은 작동 문턱 윈도우를 가로지르는 문턱레벨 상태들의 한 극단으로 삭제되고, 그 다음에 상기 삭제된 메모리 셀들 중 적어도 일부는 작동 문턱 윈도우를 가로질러 연장되는 검증레벨들을 사용하여 상기 한 극단 문턱레벨 상태로부터 상기 적어도 4개의 문턱레벨 상태들 중 다른 것들로 프로그램되고, 적어도 4개의 문턱레벨 상태들에서 작동될 때 및 정확히 2개의 문턱레벨 상태들에서 작동될 때, 상기 삭제된 메모리 셀들 중 적어도 일부는 상기 한 극단 문턱레벨 상태로부터 최대로 이동된 검증레벨들 중 하나를 사용하여 상기 한 극단 문턱레벨 상태로부터 상기 적어도 4개의 문턱레벨 상태 중 다른 하나로 프로그램되는 것을 특징으로 하는 작동 방법.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
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US09/956,340 | 2001-09-17 | ||
US09/956,340 US6456528B1 (en) | 2001-09-17 | 2001-09-17 | Selective operation of a multi-state non-volatile memory system in a binary mode |
US10/229,258 | 2002-08-26 | ||
US10/229,258 US6717847B2 (en) | 2001-09-17 | 2002-08-26 | Selective operation of a multi-state non-volatile memory system in a binary mode |
PCT/US2002/029177 WO2003025949A1 (en) | 2001-09-17 | 2002-09-13 | Selective operation of a multi-state non-volatile memory system in a binary mode |
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KR20040047835A true KR20040047835A (ko) | 2004-06-05 |
KR100918591B1 KR100918591B1 (ko) | 2009-09-24 |
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KR1020047003923A KR100918591B1 (ko) | 2001-09-17 | 2002-09-13 | 이진모드에서 다중상태 비휘발성 메모리 시스템의 선택적작동 |
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US (3) | US6717847B2 (ko) |
EP (1) | EP1433182B1 (ko) |
JP (1) | JP2005503640A (ko) |
KR (1) | KR100918591B1 (ko) |
CN (1) | CN1555559B (ko) |
AT (1) | ATE336788T1 (ko) |
DE (1) | DE60214023T2 (ko) |
TW (1) | TW574696B (ko) |
WO (1) | WO2003025949A1 (ko) |
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- 2002-09-13 JP JP2003529480A patent/JP2005503640A/ja active Pending
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- 2002-09-16 TW TW91121164A patent/TW574696B/zh not_active IP Right Cessation
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
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KR100830580B1 (ko) * | 2006-10-20 | 2008-05-21 | 삼성전자주식회사 | 플래시 메모리 장치를 포함한 메모리 시스템의 데이터 복원방법 |
US7542350B2 (en) | 2006-10-20 | 2009-06-02 | Samsung Electronics Co., Ltd. | Methods of restoring data in flash memory devices and related flash memory device memory systems |
US7970981B2 (en) | 2006-10-30 | 2011-06-28 | Samsung Electronics Co., Ltd. | Flash memory device with multi-level cells and method of writing data therein |
US8843699B2 (en) | 2006-10-30 | 2014-09-23 | Samsung Electronics Co., Ltd. | Flash memory device with multi-level cells and method of writing data therein |
US9122592B2 (en) | 2006-10-30 | 2015-09-01 | Samsung Electronics Co., Ltd. | Flash memory device with multi-level cells and method of writing data therein |
US9886202B2 (en) | 2006-10-30 | 2018-02-06 | Samsung Electronics Co., Ltd. | Flash memory device with multi-level cells and method of performing operations therein according to a detected writing patter |
Also Published As
Publication number | Publication date |
---|---|
CN1555559A (zh) | 2004-12-15 |
TW574696B (en) | 2004-02-01 |
US20030053334A1 (en) | 2003-03-20 |
WO2003025949A1 (en) | 2003-03-27 |
DE60214023T2 (de) | 2007-03-29 |
US20040190337A1 (en) | 2004-09-30 |
US7177184B2 (en) | 2007-02-13 |
CN1555559B (zh) | 2012-05-30 |
KR100918591B1 (ko) | 2009-09-24 |
EP1433182B1 (en) | 2006-08-16 |
EP1433182A1 (en) | 2004-06-30 |
US6717847B2 (en) | 2004-04-06 |
DE60214023D1 (de) | 2006-09-28 |
ATE336788T1 (de) | 2006-09-15 |
US20070109864A1 (en) | 2007-05-17 |
EP1433182A4 (en) | 2004-12-29 |
US7385854B2 (en) | 2008-06-10 |
JP2005503640A (ja) | 2005-02-03 |
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