KR20040025625A - Optoelectronic-device substrate, method for driving same, digitally-driven liquid-crystal-display, electronic apparatus, and projector - Google Patents

Abstract

PURPOSE: A substrate for an electro-optical device, a method for driving the same, a digitally-driven LCD(Liquid Crystal Display), an electronic apparatus and a projector are provided to display an image with high quality and high contrast. CONSTITUTION: The substrate(100) has a memory-cell array including a plurality of memory cells(101) that are arranged in matrix form and are digitally driven. Each memory cell has an analog switch(SW1). The analog switch(SW1) inverts the phase of data transmitted thereto. Data having an inverted phase are transmitted to the memory cell.

Description

Substrate for electro-optical devices, driving method of the substrate, digital drive liquid crystal display, electronic device, and projector {OPTOELECTRONIC-DEVICE SUBSTRATE, METHOD FOR DRIVING SAME, DIGITALLY-DRIVEN LIQUID-CRYSTAL-DISPLAY, ELECTRONIC APPARATUS, AND PROJECTOR}

TECHNICAL FIELD This invention relates to the board | substrate for electro-optical devices, the driving method of this board | substrate, a digital drive liquid crystal display device, an electronic device, and a projector.

The electro-optical panel which is used abundantly in a display apparatus is common in a structure which has a liquid crystal part, for example between a pair of board | substrates joined via the sealing material. In this kind of electro-optical panel, electrodes are formed on the surface of the respective substrates facing the other substrate. A voltage corresponding to an image to be displayed is applied to this electrode via routing wiring connected to the electrode.

Conventionally, an analog voltage is applied to the liquid crystal unit or a voltage is digitally applied to each frame or subframe (see Patent Document 1, for example). Then, after applying a positive effective voltage to prevent the accumulation of charge in the liquid crystal molecules, a negative effective voltage of substantially the same magnitude is applied. As a result, the charge remaining in the liquid crystal portion is canceled out.

(Patent Document 1) Japanese Unexamined Patent Publication No. 2001-100707

However, when positive or negative voltages are applied analogously or digitally every frame, it is difficult to completely offset the charges. For this reason, electric charges accumulate in a liquid crystal part over time, and it becomes a cause of liquid crystal molecular deterioration, and is a problem. In addition, the accumulation of this charge is a problem because it may also cause sticking of the liquid crystal unit.

Disclosure of Invention The present invention has been made in view of the above problems, and includes a substrate for an electro-optical device for a display panel capable of displaying a high-quality, high-contrast image by digital driving, a driving method of the substrate, a digital driving liquid crystal display device, An object of the present invention is to provide an electronic device and a projector.

1 is a schematic configuration diagram of a reflective liquid crystal display panel according to Embodiment 1 of the present invention.

FIG. 2 is a diagram showing a schematic configuration of a substrate for an electro-optical device in Example 1;

3A and 3B are schematic diagrams of the memory cell according to the first embodiment.

4 is an explanatory diagram of a voltage form applied to a liquid crystal layer.

5 (a) and 5 (b) are explanatory diagrams of a subframe driving method.

(A), (b), (c) is explanatory drawing of PWM.

7 is a schematic configuration diagram of a modification of the substrate for an electro-optical device according to the first embodiment.

8 is a schematic configuration diagram of a row line driver of the first embodiment;

9 is a schematic configuration diagram of a column line driver of the first embodiment;

Fig. 10 is a timing chart of the column line driver of the first embodiment.

Fig. 11 is a timing chart of the row line driver of the first embodiment.

Fig. 12 is a timing chart of data transmission of the first embodiment.

Fig. 13 is a timing chart showing the relationship between the row line driver and the column line driver of the first embodiment.

Fig. 14 is a schematic configuration diagram of the phase inversion driver of the first embodiment.

Fig. 15 is a timing chart of the phase inversion signal shift driver in the first embodiment.

16 is a timing chart sequentially displaying subframes of the first embodiment;

17A and 17B are diagrams showing the configuration of a memory cell according to the second embodiment of the present invention.

18 is a schematic configuration diagram of a substrate for an electro-optical device according to Embodiment 3 of the present invention.

19 is a schematic structural diagram of a projector according to Embodiment 5 of the present invention;

20 (a), 20 (b) and 20 (c) are external views each showing an example of the electronic apparatus according to the sixth embodiment of the present invention.

Fig. 21 is a schematic configuration diagram of a substrate for an electro-optical device according to Embodiment 4 of the present invention.

Fig. 22 is a schematic configuration diagram of a phase inversion signal driver of Example 4;

Explanation of symbols for the main parts of the drawings

10 reflective liquid crystal display panel 11 silicon substrate

12 circuit forming layer 13 sealing material

14 opposing transparent substrate 15 liquid crystal layer

16: counter electrode 17: pixel electrode

18: light shielding film 19: terminal pad

20: anisotropic conductive adhesive 21: flexible tape wiring

100, 300: substrate for electro-optical device 110: row line driver

110a, 130a: shift register circuit 110b, 130b: AND logic circuit

120: column line driver

130: phase inversion signal shift driver 101, 400: memory cell

111: address signal lines 120a, 120b: data signal lines

131: phase inversion signal line 140: memory cell group

T1 to T10: transistor 200, 401: storage unit

500a, 500b: Partial Column Line Driver

600: projector 610: main body

611: light source unit 612: control circuit

613: digital liquid crystal drive display device 620: projection lens system

630 screen 1000: mobile phone body

1100: clock body 1200: information processing device

1310: row address decode driver

1320: column address decode driver 1330: phase inversion driver

RAD: column address data LAD: row address data

101P: memory cell 1340: buffer amplifier

In order to solve the above problems and to achieve the object, the present invention provides a substrate for an electro-optical device having a memory cell array including a plurality of memory cells arranged in a matrix and digitally driven, the memory cells being supplied Provided is a substrate having an inversion circuit for inverting the phase of data, or data whose phase is already inverted is supplied to the memory cell. Thus, the charge remaining in the memory cell, for example, in the liquid crystal layer, can be canceled. Then, digital driving can display a high quality image and high contrast image.

According to a preferred aspect of the present invention, the memory cell includes a storage unit for storing the data, a first analog switch unit for generating a data inversion signal based on a phase inversion signal, and the first analog switch. And a second analog switch section for switching the data inversion signal from the section and a zero data signal. When the data is stored in the storage section, the data inversion signal is selected and the storage section is selected. When the data is not stored in the memory, it is preferable to select the zero data signal. As a result, since the memory cell has a data inversion function, the drive capability of the phase inversion signal shift driver described later can be reduced.

According to a preferred embodiment of the present invention, it is preferable that the storage section has an SRAM structure. As a result, data can be reliably maintained digitally.

According to a preferred aspect of the present invention, the memory cell array includes a plurality of first signal lines for connecting in parallel a set of address terminal groups included in a set of memory cell groups arranged along a row direction, and a column direction. Therefore, a plurality of second signal lines for connecting in parallel a set of data terminal groups included in a set of memory cell groups arranged and a set of phases included in the set of memory cell groups arranged along the row direction or the column direction And a plurality of third signal lines for connecting the inverted terminal groups in parallel, wherein the substrate for the electro-optical device is addressed to each group of memory cell groups arranged along the row direction via the plurality of first signal lines. Angles arranged along the column direction via a first driver circuit for sequentially supplying signals and the plurality of second signal lines A phase inversion signal is supplied to each group of memory cell groups arranged along the row direction or the column direction via a second driver circuit for simultaneously supplying the data signal to a group of memory cell groups and the plurality of third signal lines. It is preferable to further provide a 3rd driver circuit for doing this. Accordingly, two-dimensional data such as image data can be stored in the plurality of memory cell arrays.

According to a preferred aspect of the present invention, it is preferable that the third driver circuit has a phase inversion circuit for inverting the phase of the data, and the phase inversion circuit inverts the phase of the data before supplying it to the memory cell. Do. As a result, the number of transistors constituting the memory cell can be reduced. As a result, the pixel size can be reduced.

According to a preferred aspect of the present invention, the memory cell array includes a plurality of first signal lines for connecting in parallel a set of address terminal groups included in a set of memory cell groups arranged along a row direction, and a column direction. A plurality of second signal lines for connecting in parallel a set of data terminal groups included in the set of memory cell groups arranged along the line, and 1 included in the set of memory cell groups arranged along the row direction or the column direction A plurality of third signal lines for connecting a group of phase inversion terminal groups in parallel, wherein the substrate for an electro-optical device is any one of the memory cell groups arranged along the row direction via the plurality of first signal lines A row address decode driver circuit for supplying row address data for selecting a row of the plurality of second signal lines Supplying column address data for selecting one column of the memory cell group arranged along the column direction, and the pixel data signal outputted to the memory cell specified by the row address data and the column address data And a phase inversion driver circuit for supplying a phase inversion signal to each group of memory cell groups arranged along the row direction or the column direction via the column address decode driver circuit and the plurality of third signal lines. desirable. In this configuration, a specific memory cell located at the intersection of any row and column by row address data for selecting any row in the memory cell group and column address data for selecting any row in the column Can be selected. The pixel data of the selected arbitrary memory cell may be randomly rewritten regardless of the arrangement of the memory cells. As a result, the transfer of the pixel data to be displayed can be omitted for memory cells that do not need to be rewritten. As a result, power consumption required for the rewrite operation can be reduced. Therefore, the power saving of image display apparatuses, such as a digital drive liquid crystal display device, an electronic device, and a projector provided with the board | substrate for this electro-optical device, can be aimed at.

According to a preferred aspect of the present invention, the phase inversion driver circuit includes a phase inversion circuit for inverting the phase of the pixel data, and the phase inversion circuit includes the above-described display contents rewritten by the pixel data signal. Regardless of the number of memory cell groups, it is preferable to invert the phase of the pixel data at regular intervals. For example, when the substrate for the electro-optical device is applied to a liquid crystal display device, the refresh operation (phase inversion process operation) of the display data applied to the liquid crystal layer of the liquid crystal display device is performed regardless of whether or not the pixel data to be displayed is changed. Can be run at intervals depending on the performance of the. When the image display apparatus is displaying a still image, rewriting of display data is unnecessary. In this embodiment, for example, when a still image is displayed, the refresh operation (phase inversion process operation) necessary for a moving image can be omitted. As a result, in order to prevent sticking of the liquid crystal, the required minimum refresh operation can be performed in view of the characteristics of the liquid crystal. Therefore, the power saving of image display apparatuses, such as a digital drive liquid crystal display device, an electronic device, and a projector provided with the board | substrate for this electro-optical device, can be aimed at.

Moreover, this invention provides the electronic device characterized by having the electro-optical device board | substrate described above, and the display part which displays an image with the said electro-optical device board | substrate. As a result, it is possible to display an image having high quality and high contrast.

The present invention also provides a light source unit for supplying illumination light, a substrate for an electro-optical device described above, a display unit for displaying an image by the electro-optical device substrate, and a projection lens system for projecting an image of the display unit. Provided is a projector. As a result, it is possible to project an image of high quality and high contrast.

According to a preferred aspect of the present invention, there is provided a driving method of a substrate for an electro-optical device having a memory cell array including a plurality of memory cells arranged in a matrix in a row direction and a column direction and digitally driven. It is preferable to include a phase inversion process of inverting the phase of the data supplied to the. Thus, the charge remaining in the memory cell, for example, in the liquid crystal layer, can be canceled. Then, digital driving can display a high quality image and high contrast image.

According to a preferred aspect of the present invention, the phase reversal step includes a step of pulse-modulating the data, dividing one frame into a plurality of subframes, and adding display data in the subframes by approximately 1/2. It is preferable to convert to a phase of and a negative phase of. Thereby, the deterioration of the liquid crystal molecules of a liquid crystal display panel can be reduced by canceling out electric charges, for example. As a result, the sticking of the liquid crystal part can be prevented.

According to a preferred embodiment of the present invention, the phase inversion step preferably selects the memory cell array arranged in the row direction and inverts the phase of the data. Thereby, the subframe can be rewritten efficiently without wasting time.

According to a preferred embodiment of the present invention, the phase inversion step changes the period of the phase inversion signal supplied to the memory cell array in the row direction and the period of the data signal supplied to the memory cell array in the row direction. Therefore, it is preferable to include a subframe period varying step of making the period of the subframe variable. Accordingly, the period of the subframe can be arbitrarily changed.

(Example of the invention)

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention will be described in detail.

(Example 1)

(Reflective liquid crystal display panel)

FIG. 1: is a figure which shows the cross-sectional structure of the reflective liquid crystal display panel 10 provided with the board | substrate for electro-optical devices concerning Example 1 of this invention. The circuit forming layer 12 having the pixel electrode 17 is formed on the silicon substrate 11. The pixel electrode 17 is formed in matrix form. In addition, the transparent substrate 14 is provided to face the silicon substrate 11. The liquid crystal layer 15 is formed between the silicon substrate 11 and the transparent substrate 14. The liquid crystal layer 15 is sealed by the sealing material 13.

An opposing COM electrode 16 is formed on the silicon substrate 11 side of the transparent substrate 14. In addition, a terminal pad 19 is provided at an end portion of the silicon substrate 11. The flexible tape wiring 21 is bonded to the terminal pad 19 via the anisotropic conductive adhesive 20.

In the reflective liquid crystal display panel 10, all the components are provided in the circuit forming layer 12 on the silicon substrate 11. In addition, a driving circuit for driving the pixel electrode 17, a row line driver, a column line driver, and a phase inversion signal shift driver in the peripheral portion of the substrate are also formed in the peripheral portion of the pixel on the same substrate.

This reflective liquid crystal display panel 10 has two characteristics. The first feature is that the voltage is digitally applied to the liquid crystal layer 15 and a pair of positive / negative inverted voltages are applied within one frame (or one subframe described later). to be. Moreover, the 2nd characteristic is that the image display WHEREIN: The subframe drive system mentioned later is employ | adopted, and it displays sequentially while rewriting for every line. Details of these features will be described later.

(Schematic Configuration of Substrate for Electro-optical Device)

Fig. 2 is a block diagram showing the internal structure of the circuit forming layer 12 including the above drive circuit and each driver. The circuit formation layer 12 includes a memory cell array (digital memory device) 140, a row line driver 110, a column line driver 120, and a phase inversion signal shift driver 130. The drivers 110, 120, and 130 are supplied with signals DY, DATA, and DFC from control circuits (not shown), respectively, and clock signals CLY, #CLY, CLX, #CLX, CLFC, and #CLFC are supplied. Supplied.

In addition, in this specification, the signal with "#" attached to the head of a code | symbol corresponds to the signal with a bar in the upper part of a code | symbol in a figure, These signals have "#" and a bar. For a signal that does not exist, this means that the logic level is an inverted signal.

The memory cell array 140 includes a plurality of memory cells 101 arranged in a two-dimensional matrix shape (array shape), and can store one screen of image data. Each memory cell 101 has a pair of data terminals 102d1 and 102d2, an address terminal 102a, a phase inversion terminal 102f, and an output terminal (not shown).

In addition, the memory cell array 140 includes a plurality of address lines (first signal lines) 111 and column line drivers (second driver circuits) electrically connected to the row line drivers (first driver circuits) 110 ( A plurality of pairs of data lines (second signal lines) 120a and 120b electrically connected to 120 and a plurality of phase inversion signal lines electrically connected to a phase inversion signal shift driver (third driver circuit) 130 Three signal lines) 131.

Each address line 111 connects the address terminals 102a of a plurality of memory cells arranged in a row direction (first direction) in parallel. Each data line 120a connects the data terminal groups 102d1 of a plurality of memory cells arranged in a column direction (a second direction orthogonal to the first direction) in parallel. Similarly, each data line 120b connects the data terminal groups 102d2 of a plurality of memory cells arranged along the column direction in parallel. Each phase inversion signal line 131 connects the phase inversion terminals 102f of a plurality of memory cells arranged in a row direction (first direction) in parallel.

(Configuration of Memory Cells)

FIG. 3A is a diagram illustrating a schematic configuration of the memory cell 101. The memory cell 101 has a storage unit 200 and two analog switches SW1 and SW2. The storage unit 200 is an SRAM and stores data DATA and #DATA supplied from Dn and #Dn of the column line driver 120. In addition, the first analog switch SW1 supplies the data inversion potential Dout to the second analog switch SW2 based on the phase inversion signal FC. The second analog switch SW2 applies either the data inversion potential Dout from the first analog switch SW1 and the reference potential COM to the pixel electrode 14 in accordance with the data stored in the storage unit 200. The reference potential COM is equal to the potential applied to the counter electrode 16 in FIG. 1. In the case where data DATA is stored in the storage unit 200, since the data inversion potential Dout is applied to the pixel electrode 14, the voltage of the difference between the data inversion potential and the reference potential is applied to the liquid crystal layer 15. Is approved. On the other hand, when data DATA is not stored in the storage unit 200, the reference potential C0M is applied to the pixel electrode 14, and as a result, the potential difference between the pixel electrode and the common electrode becomes zero, so that the liquid crystal layer ( 15) no voltage is applied.

FIG. 3B is a diagram showing the configuration of the memory cell 101 at the transistor level. The transistors T1 to T6 correspond to the storage unit 200. The transistors T7 to T10 correspond to the analog switch SW2, and the transistors T11 and T12 correspond to the analog switch SW1, respectively. In this way, by forming the analog switch SW1 in the pixel, the drive capability of the FC line can be reduced.

The column line driver 120 gives #Dj (j is an integer from 0 to m. M is the number of columns in the pixel array) to the memory array because the memory cell 101 has a memory having an SRAM structure. to be. Although only Dj may be provided, it is preferable to assign Dj and #Dj because the speed of data confirmation is faster. The memory in the memory array may be memory that does not require #Dj. In this case, the column line driver 120 may not output #Dj to the memory array. However, the memory of the SRAM structure is suitable for the memory in the memory array in this embodiment for at least the following 1) and 2) reasons. 1) The structure is simple, and for this reason, it is easy to provide for every pixel area of a spatial light modulation device. 2) Because of its high speed, it is suitable for processing image data.

(Applied voltage to the liquid crystal)

4 is an explanatory diagram of a voltage applied to the liquid crystal unit 15. Fig. 4 focuses on the description of the applied voltage, which is a feature of the present application, and details of the operations of the drivers 110, 120, and 130, and the description of the subframes will be described later. First, the address signal Yi (i is an integer from 1 to n. N is the number of rows of the pixel array) from the row line driver 110 is supplied to the memory cells 101 in the row direction. In addition, the phase inversion signal FCi (where i is an integer from 1 to n) from the phase inversion signal shift driver 130 repeats the H level and the L level in 1/2 cycles in the subframe. In addition, the data Dj of the column line driver 120 is supplied in accordance with the address signal Yi from the row line driver 110.

As described with reference to Fig. 3A, the first analog switch SW1 generates the data inversion potential Douti based on the phase inversion signal FCi. The second analog switch SW2 switches the data inversion potential Douti and the reference potential COM from the first analog switch SW1. Accordingly, a voltage is applied to the liquid crystal layer 15 in the frame into which the data signal Di of the column line driver 120 is input. In this case, the potential applied to the pixel electrode becomes the potential Vcc and the potential GND every 1/2 cycle in the subframe. Here, the potential difference between the reference potential COM and the potential Vcc and the potential difference between the reference potential COM and the potential GND are equal. For this reason, the effective voltages Va and Vb based on the reference potential C0M are opposite in phase, and a voltage having the same magnitude is applied to the liquid crystal layer 15.

If the magnitude | size (effective voltage) of the voltage applied is the same, the liquid crystal layer 15 operates similarly regardless of the positive part / phase part. Further, the positive voltage and the voltage of the digital part having the same magnitude are applied at the time of displaying an image of one frame at the same ratio. As a result, charges do not remain in the liquid crystal molecules and are almost completely canceled out. For this reason, electrification of the liquid crystal layer 15 over time can be reduced, and sticking can be prevented.

(Sub-frame driving method)

Next, the principle of the sub frame driving method will be described. Conventionally, a voltage corresponding to the gray level of an image is applied analog to the liquid crystal layer. The gray level can be expressed by the magnitude of the applied voltage. In contrast, in the reflective liquid crystal display panel 10 according to the present embodiment, the ON / OFF voltage is digitally applied to the liquid crystal layer 15 as described above. Therefore, as in the prior art, it is impossible to express the gray level of the image by the magnitude of the applied voltage. For this reason, the gray level of the image is expressed by a subframe driving method using pulse width modulation (hereinafter, referred to as "PWM").

First, the subframe driving method will be described. Here, for the sake of simplicity, a case where an image is represented by eight gray levels (3 bits) is considered. In this case, one frame is composed of three subframes from the first subframe 1SF to the third subframe 3SF.

FIG. 5A is a diagram illustrating a configuration of a pixel array. As shown in Fig. 5A, an image of one frame consists of a pixel array of 1024 rows. One frame is configured from the first line to the nth line. One subframe includes an address period Ta for writing data into a memory cell and a display period for displaying an image in accordance with the written data. In one sub frame period, data DATA to be displayed in each memory cell (pixel) is stored ON when the weighted sub frame is required for display of the frame. The weighting of the subframes will be described later in the description of the PWD. The display period of the stored data DATA corresponds to the lit state. FIG. 5B is a diagram illustrating a relationship between one entire frame and a subframe. One frame consists of three subframes 1SF to 3SF. Here, the address period Ta of each subframe is common. In contrast, the display period of each subframe is different. The number of each subframe is increased or decreased by the number of gray levels of the image to be displayed. In the subframe with a long display period such as the subframe 3SF, it is preferable to further divide one subframe 3SF. Thereby, virtual outline etc. can be reduced and the quality of the image displayed can be improved.

(PWM)

Next, the PWM will be described based on FIG. First, the case where one image is represented by 16 gray levels (4 bits) is described as an example. In the case of 4 bits, as shown in Fig. 6A, four sub-frame pulses P0 (= 2 ⁰ ), P ¹ (= 2 ¹ ), each having a weight corresponding to each bit of the 4-bit gradation display, P2 (= 2 ² ) and P3 (= 2 ³ ) are used. 6B is a timing chart of the sub frame pulses P0, P1, P2, and P3. As shown in Fig. 6C, for example, when the image has a gradation of 10 levels, it is turned on when the sub frame pulses P1 and P3 are displayed in one frame display period. As a result, the integrated value of the lighting failure time in one frame becomes the gradation of the display image actually observed. Similarly, when the image gradation changes from 10 levels to 6 levels, it is lit when the sub frame pulses P1 and P2. As described above, in the reflective liquid crystal display panel according to the present embodiment, the gray level of the display image is expressed using the subframe driving method and the PWM.

(Modified example of the substrate for the electro-optical device)

In the board | substrate for electro-optical devices shown in FIG. 2, the principle of the characteristic technical matters of this application was demonstrated. Here, a configuration in which an AND circuit and a signal WE are added in order to align the rewrite periods of the data signal DATA is shown in FIG. The configuration shown in FIG. 7 differs in that the AND circuit and the signal WE are added to the address signal Y from the row line driver with respect to the configuration shown in FIG. 2. Since the structure other than that is the same as that shown in FIG. 2, the same code | symbol is attached | subjected to the same part and the overlapping description is abbreviate | omitted.

Hereinafter, the structure and function of each driver are demonstrated based on the structure shown in FIG.

(Configuration of the Line Line Driver)

8 is a block diagram illustrating an example of an internal configuration of the row line driver 110. The row line driver 110 sequentially supplies an address signal (scan signal) Yi from top to bottom in FIG. 7 to each group of memory cell groups arranged along the row direction via each address line 111. do.

The row line driver 110 includes a shift register circuit 110a including a plurality of registers composed of three inverters, and an AND logic circuit 110b including a plurality of AND gates. The shift register circuit 110a has a serial parallel conversion function, and the pulse-shaped address signal DY applied to the first register is sequentially transferred to the second and subsequent registers according to the clock signals CLY and #CLY. At the same time, it is output from each register. Each AND gate of the AND logic circuit 110b outputs the logical product of the data supplied from two adjacent registers as an address signal Yi or the like. As a result, the AND logic circuit 110b has an address signal Yi having a relatively high temporal resolution, in other words, a short time for which the address signal DY is shifted by the clock signals CLY and #CLY (1 / clock of the clock signals CLY and #CLY). The address signal Yi which becomes H level by 2 cycles) can be output.

(Configuration of Thermal Line Driver)

9 is a block diagram illustrating an example of an internal configuration of the column line driver 120. The column line driver 120 simultaneously supplies a pair of data signals D and #D to each group of memory cell groups arranged along the column direction via each pair of data lines 120a and 120b. The column line driver 120 has a shift register circuit 120a including a plurality of registers composed of six inverters. The shift register circuit 120a has a serial parallel conversion function, and the image data signal DATA applied to the first register is sequentially transmitted to the second and subsequent registers and output from each register. The pair of output signals Q and #Q corresponds to the signals D and #D in FIG.

(Timing chart of the column line driver)

10 is a timing chart showing the operation of the column line driver 120. As shown in the figure, each register composed of six inverters sequentially transfers data to the falling edge of the clock signal CL.

In this manner, when the enable signal WE becomes H level, the H signal address signal Y is supplied to the group of memory cells in which the data signals D and #D are to be supplied.

Accordingly, each memory cell 101 can store data in a state where crosstalk or the like does not occur.

(Timing chart of row line driver)

11 is a timing chart showing the operation of the row line driver 110. At time t1, the address signal DY indicating the start of the first subframe 1SF period is supplied to the row line driver 110 from a control circuit (not shown). The row line driver 110 supplies the shifted address signal Yi to the memory cells 101 group in each row in order through the plurality of address lines 111 in accordance with the address signal DY. For example, at time t2, the address signal Y0 is supplied to the first group of memory cells 101 via the first address line 111. Then, in the falling WY0 of the address signal Y0, the memory cell group of the first row latches the data signals D and #D supplied through the pair of data lines 120a and 120b. 12 is a timing chart showing timing of transferring the data signal DATA in accordance with the clock CLX in the row direction.

(Timing chart of row line and column line)

Fig. 13 shows the relationship between the timing of the address signal DY of the row line and the writing of the data signal DATA in one timing chart. For example, in the first subframe 1SF, after selecting a row by the address signal Y1, data DATA in the column direction is written into the memory cell 101 group at one time.

(Configuration of Phase Reverse Shift Driver)

14 is a diagram illustrating a schematic configuration of the phase inversion shift driver 130. The phase inversion shift driver 130 includes a shift register circuit 130a including a plurality of registers composed of three inverters, and an AND logic circuit 130b including a plurality of AND gates. The shift register circuit 130a has a serial parallel conversion function, and the pulse-shaped phase inversion signal DFC applied to the first register is sequentially transferred to the second and subsequent registers according to the clock signals CLFC and #CLFC. At the same time, it is output from each register. Each AND gate of the AND logic circuit 130b outputs the logical product of the data supplied from two adjacent registers as the phase inversion signal FC0 or the like.

(Timing chart of phase inversion shift driver)

15 is a timing chart of a phase inversion shift driver. As apparent by comparing the configuration of the row line driver 110 (FIG. 8) and the configuration of the phase inversion shift driver 130 (FIG. 14), both drivers have the same configuration. For this reason, the timing chart shown in FIG. 15 also shows the same operation as the timing chart of the row line driver shown in FIG. Here, since the output Ym0 ... of the shift register and the phase inversion signal FCm0 ... correspond to equivalent operation contents, redundant description is omitted.

(Timing chart of video display)

FIG. 16 is a timing chart when an image is displayed in the electro-optical circuit board 100. In Fig. 16, the phase inversion signal FC0 ... is sequentially shifted in accordance with the address signal Yi ... For example, even when the period of the second subframe 2SF is started in the first row line, the video of the first subframe 1SF is displayed in the second and subsequent row lines. With this video display method, subframes can be continuously written without wasting time. By changing the appearance rate of the signal DY, even if the clock signal CLY (CLFC) is the same, the period of the signal DFC can be changed.

(Example 2)

FIG. 17A is a diagram illustrating a schematic configuration of a memory cell 400 of a substrate for an electro-optical device according to Embodiment 2 of the present invention. The memory cell 101 according to the first embodiment has two analog switches SW1 and SW2, whereas in this embodiment, only one analog switch SW2 is different. Since the other structure is the same as that of Example 1, the same code | symbol is attached | subjected to the same part and the overlapping description is abbreviate | omitted. In addition, since the structure of the board | substrate for electro-optical devices is the same as that shown in FIG. 2, it abbreviate | omits. In this embodiment, the phase inversion shift driver 130 has a function of generating a data inversion potential based on the phase inversion signal FC.

FIG. 17B is a diagram showing the configuration of the memory cell 400 at the transistor level. The transistors T1 to T6 correspond to the storage unit 401. In addition, transistors T7 to T10 correspond to analog switch SW2. In this way, the transistor constituting the pixel can be reduced by giving the function of the analog switch SW1 to the phase inversion signal shift driver. As a result, the pixel size can be made smaller.

(Example 3)

18 is a diagram showing a schematic configuration of a substrate for an electro-optical device according to Embodiment 3 of the present invention. This embodiment differs from the first embodiment in that it has two partial column line drivers 500a and 500b. Since other configurations are the same as those of the first embodiment, the same reference numerals are given to the same parts, and redundant descriptions are omitted.

By providing the two partial column line drivers 500a and 500b in this manner, data can be developed in parallel and transferred to each memory cell, thereby reducing the amount of data that the line driver performs serial parallel conversion. As a result, even when the number of pixels is large, an image can be displayed at high speed. The number of partial column line drivers is not limited to two, but three or more may be provided. When three or more partial column line drivers are provided, it can respond also to the case of more pixel structure.

(Example 4)

21 is a diagram showing a schematic configuration of a substrate for an electro-optical device according to Embodiment 4 of the present invention. This embodiment changes the column line driver 120 to the column address decode driver 1320 and the row line driver 110 to the row address decode driver 1310 in comparison with the first embodiment. And the phase inversion shift driver 130 is changed to the phase inversion signal driver 1330. Since other configurations are the same as those of the first embodiment, the same reference numerals are given to the same parts, and redundant descriptions are omitted.

By the row address data LAD and the column address data RAD, memory cells of arbitrary addresses can be specified and selected. The column address decode driver 1320 outputs pixel data stored in the selected address memory cell 101 from the data lines (second signal lines) 120a and 120b.

For example, a case of rewriting pixel data of the memory cell 101P indicated by diagonal lines among the plurality of memory cells 101 in FIG. 21 is considered. In this case, the row address decode driver 1310 is supplied with row address data LAD for selecting the output of the address signal Y1. In addition, the column address decode driver 1320 simultaneously transmits the column address data RAD for selecting the output D1 and the pixel data written in the memory cell 101P to the display data terminal. From this, the pixel data of any one of the memory cells 101P selected from the plurality of memory cells 101 can be rewritten at random regardless of the arrangement of the memory cells 101. As a result, the transfer of the pixel data to be displayed can be omitted for the memory cell 101 which does not need rewriting of the pixel data to be displayed. Therefore, power consumption required for the rewrite operation can be reduced.

Next, the schematic structure of the phase inversion signal driver 1330 is shown in FIG. The phase inversion signal driver 1330 has a plurality of buffer amplifiers 1340. The buffer amplifier 1340 amplifies and generates the data inversion potential (corresponding to the Vcc or GND potential in FIG. 3) according to the phase inversion signal DFC. The phase inversion signal driver 1330 supplies the generated data inversion potential to all the memory cells 101 from the outputs FC0 to FCn. Accordingly, regardless of the amount of rewrite of all the memory cells 101, that is, the number of memory cells 101 to be rewritten, the phase inversion operation of the potential of the liquid crystal applied voltage output from the pixel electrode can be performed. As a result, irrespective of whether or not there is a change in the display data, the refresh operation (phase inversion process operation) of the display data applied to the liquid crystal layer 15 (FIG. 1) can be performed at intervals corresponding to the liquid crystal performance. Therefore, in order to prevent sticking of the liquid crystal, the required minimum refresh operation can be performed in view of the characteristics of the liquid crystal. In addition, power saving of an image display device such as a digital drive liquid crystal display device, an electronic device, a projector, and the like, which is provided with the substrate 1300 for the electro-optical device, for example, can be achieved.

(Example 5)

19 is a diagram showing a schematic configuration of a projector 600 according to a fifth embodiment of the present invention. The projector 600 has a main body 610 and a projection lens system 620. The main body 610 includes a digital liquid crystal drive display device 613 and a digital liquid crystal drive display device 613 including a light source unit 611 for supplying illumination light, a substrate for an electro-optical device described in each of the above embodiments. The control circuit 612 for controlling is provided. The projection lens system 620 enlarges and projects an image displayed on the digital liquid crystal drive display device 613 on the screen 630. Since the projector 600 is provided with the board | substrate for electro-optical devices described in each said Example, it can project an image of high quality and high contrast by digital drive. In addition, the power saving of the projector 600 can be achieved.

(Example 6)

20A, 20B, and 20C are examples of electronic devices according to Embodiment 6 of the present invention, respectively. 20A is a perspective view illustrating an example of the mobile telephone 1000. The mobile telephone 1000 has a liquid crystal display device 1001 using the electrooptical device substrate of the present invention. 20B is a perspective view illustrating an example of the wrist watch type electronic device 1100. The wristwatch type electronic device 1100 has a liquid crystal display device 1101 using the substrate for an electro-optical device of the present invention. 20C is a perspective view illustrating an example of a portable information processing apparatus 1200 such as a word processor or a personal computer. The information processing apparatus 1200 includes an input unit 1202 such as a keyboard, an information processing apparatus main body 1204, and a liquid crystal display device 1206 using the substrate for an electro-optical device of the present invention. Since these electronic devices are provided with the board | substrate for electro-optical devices described in the said each Example, the image of high quality and high contrast can be obtained by digital drive. In addition, it is possible to reduce the power consumption of the electronic device. In addition, this invention is not limited to each said Example, A various deformation | transformation can be taken in the range which does not deviate from the meaning.

According to the present invention as described above, an image of high quality and high contrast can be displayed by digital driving by canceling out the charge remaining in the memory cell, for example, in the liquid crystal layer.

In addition, according to the present invention, since the memory cell has a data inversion function, the drive capability of the phase inversion signal shift driver can be reduced.

In addition, according to the present invention, the number of transistors constituting the memory cell can be reduced, and the pixel size can be reduced.

According to the present invention, transfer of pixel data to be displayed can be omitted for memory cells that do not need to be rewritten of the pixel data to be displayed, and power consumption required for the rewrite operation can be reduced.

Claims (15)

A substrate for an electro-optical device having a memory cell array including a plurality of memory cells arranged in a matrix and digitally driven, and a pixel electrode for extracting pixel data stored in the memory cells as an electrical signal, And the memory cell has a phase inversion circuit for inverting the phase of the supplied pixel data, and a data inversion signal whose phase is inverted by the phase inversion circuit is supplied to the pixel electrode. The method of claim 1, The memory cell includes a storage unit for storing the pixel data; A first analog switch unit for generating the data inversion signal based on a phase inversion signal; A second analog switch unit for switching the data inversion signal from the first analog switch unit and a zero data signal, When the pixel data is stored in the storage unit, the data inversion signal is selected. When the pixel data is not stored in the storage unit, the zero data signal is selected and supplied to the pixel electrode. A substrate for electro-optical devices. The method of claim 2, And said data inversion signal shifts in phase between a positive side potential and a negative side potential with the potential of the zero data signal approximately at the center. The method of claim 2, The storage unit is an electro-optical device substrate, characterized in that the SRAM structure. The method of claim 1, The memory cell array includes a plurality of first signal lines for connecting in parallel a set of address terminal groups included in a set of memory cell groups arranged along a row direction; A plurality of second signal lines for connecting in parallel a set of data terminal groups included in a set of memory cell groups arranged along a column direction; A plurality of third signal lines for connecting in parallel a set of phase inversion terminal groups included in the set of memory cell groups arranged along the row direction or the column direction, The substrate for the electro-optical device, A first driver circuit for sequentially supplying an address signal to the memory cell group arranged along the row direction via the plurality of first signal lines; A second driver circuit for simultaneously supplying the pixel data signal to the memory cell group arranged along the column direction via the plurality of second signal lines; Further comprising a third driver circuit for supplying a phase inversion signal to each group of memory cell groups arranged along the row direction or the column direction via the plurality of third signal lines A substrate for an electro-optical device, characterized by the above-mentioned. The method of claim 4, wherein The third driver circuit has a phase inversion circuit for inverting the phase of the pixel data, and the phase inversion circuit inverts the phase of the pixel data before supplying it to the memory cell. . The method of claim 1, The memory cell array, A plurality of first signal lines for connecting in parallel a set of address terminal groups included in a set of memory cell groups arranged along a row direction; A plurality of second signal lines for connecting in parallel a set of data terminal groups included in a set of memory cell groups arranged along a column direction; A plurality of third signal lines for connecting in parallel a set of phase inversion terminal groups included in the set of memory cell groups arranged along the row direction or the column direction, The substrate for the electro-optical device, A row address decode driver circuit for supplying row address data for selecting any one row of the memory cell groups arranged along the row direction via the plurality of first signal lines; Outputted to the memory cell specified by the row address data and the column address data, the column address data for selecting any one column of the memory cell group arranged along the column direction via the plurality of second signal lines; A column address decode driver circuit for supplying the pixel data signal; Further comprising a phase inversion driver circuit for supplying a phase inversion signal to each group of memory cell groups arranged in the row direction or the column direction via the plurality of third signal lines A substrate for an electro-optical device, characterized by the above-mentioned. The method of claim 7, wherein The phase inversion driver circuit has a phase inversion circuit for inverting the phase of the pixel data, And said phase inversion circuit inverts the phase of said pixel data at a predetermined period irrespective of the quantity of said memory cell group whose display contents are rewritten by said pixel data signal. Between the board | substrate for electro-optical devices of any one of Claims 1-8, and the opposing board | substrate which has a common electrode for supplying the voltage of the same potential as the potential of the said zero data supplied to the said board | substrate for electro-optical devices. And a digital drive liquid crystal display device configured to drive a liquid crystal layer sandwiched therein. An electronic apparatus comprising a display unit for displaying an image by the digital drive liquid crystal display device according to claim 9. A light source unit for supplying projection light, The digital drive liquid crystal display device of Claim 9, A control circuit for controlling the digital drive liquid crystal display device; And a projection lens system for magnifying and projecting an image of the digital drive liquid crystal display. A substrate for an electro-optical device having a memory cell array including a plurality of memory cells arranged in a matrix in a row direction and a column direction and digitally driven, and a pixel electrode for extracting pixel data stored in the memory cells as an electrical signal. In the driving method of, And a phase inversion step of inverting a phase of pixel data before supplying to the memory cell or pixel data after supplying to the memory cell. The method of claim 12, The phase inversion process includes: pulse width modulating the pixel data, dividing one frame into a plurality of subframes, and roughly centering the potential of the zero data signal by half of the display data in the subframe. A method of driving a substrate for an electro-optical device, characterized by converting a potential and a phase of the pixel data into one positive side potential and a negative side potential. The method of claim 12, And wherein the phase inversion step sequentially selects the memory cell arrays arranged in the row direction and inverts the phase of the pixel data. The method of claim 14, The phase inversion process is performed by synchronously varying a period of a phase inversion signal supplied to the memory cell array in the row direction and a pixel data signal supplied to the memory cell array in the row direction, thereby giving a period of the subframe. A method of driving a substrate for an electro-optical device, characterized by varying the degree of gray scale expression.