JP2002049346A - Driving method and driving circuit for electro-optical device, electro-optical device, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electro-optical device capable of performing high-quality and high-definition gray display, and to provide its driving method, its driving circuit and an electronic equipment using the electro-optical device. SOLUTION: In this driving method for driving pixels arranged in a matrix shape according to gray scale data, each field is divided into an all-pixel OFF period and plural sub-fields, and in the all-pixel OFF period, all pixels are made into OFF state simultaneously, besides respective pixels are made into ON state or OFF state respectively in a sub-field unit so that the radio of hours for making respective pixels into the ON state to hours for making the pertinent pixels into the OFF state in one field becomes the ratio corresponding to the gray scale data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method, a driving circuit, an electro-optical device, and an electronic apparatus for an electro-optical device that performs gradation display control by performing modulation on a time axis.

[0002]

2. Description of the Related Art An electro-optical device, for example, a liquid crystal display device using liquid crystal as an electro-optical material is a cathode ray tube (CRT).
It is widely used in display units of various information processing devices, liquid crystal televisions, and the like.

Here, a conventional electro-optical device is, for example,
It is configured as follows. That is, the conventional electro-optical device includes a pixel electrode arranged in a matrix, an element substrate provided with a switching element such as a TFT (Thin Film Transistor) connected to the pixel electrode, and a pixel electrode. It comprises an opposing substrate on which opposing opposing electrodes are formed, and a liquid crystal as an electro-optical material filled between the two substrates. In such a configuration, when a scanning signal is applied to a switching element via a scanning line, the switching element is turned on. In this conductive state, when an image signal of a voltage corresponding to the gradation is applied to the pixel electrode via the data line, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Stored. After the charge accumulation, even if the switching element is turned off, the accumulation of charge in the liquid crystal layer is maintained by the capacitance of the liquid crystal layer itself, the storage capacitance, and the like. As described above, when the switching elements are driven and the amount of charge to be stored is controlled according to the gradation, the alignment state of the liquid crystal changes for each pixel, so that the density changes for each pixel. Therefore, it is possible to perform gradation display.

[0004] At this time, it is sufficient to accumulate electric charges in the liquid crystal layer of each pixel during a part of the period. First, each scanning line is sequentially selected by a scanning line driving circuit, and secondly,
In the scanning line selection period, the data lines are sequentially selected by the data line driving circuit, and thirdly, the selected data lines are sampled with an image signal of a voltage corresponding to a gray scale. Time-division multiplex driving in which a line is shared by a plurality of pixels becomes possible.

[0005]

However, the image signal applied to the data line is a voltage corresponding to the gradation, that is, an analog signal. For this reason, a peripheral circuit of the electro-optical device requires a D / A conversion circuit, an operational amplifier, and the like, thereby increasing the cost of the entire device. Furthermore, display unevenness occurs due to the characteristics of the D / A conversion circuit and the operational amplifier, and the non-uniformity of various wiring resistances, so that high-quality display is extremely difficult.
This problem is particularly noticeable when performing high-definition display.

The present invention has been made in view of the above circumstances, and has as its object to provide an electro-optical device capable of high-quality and high-definition gradation display, a driving method thereof,
Another object of the present invention is to provide an electronic apparatus using the electro-optical device.

[0007]

In order to achieve the above object, a first aspect of the present invention is to provide a memory and a pixel electrode provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines. Is a driving method of an electro-optical device that drives pixels according to gradation data, wherein each field is divided into an all-pixel off period and a plurality of subfields, and all the pixels are simultaneously turned on during the all-pixel off period. Each pixel in each subfield is set so that the ratio between the time in which the pixel is turned off and the time in which each pixel is turned on in one field and the time in which the pixel is turned off is a ratio corresponding to the gradation data. A driving method of the electro-optical device, wherein the driving method is for turning on or off the device.

[0008] Also, a driving method of an electro-optical device for driving a pixel, which is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and includes a memory and a pixel electrode in accordance with gradation data, is provided. And dividing each field into an all-pixels off period and a plurality of subfields, all the pixels are simultaneously turned off in the all-pixels off period, and the plurality of scans are performed in each of the plurality of subfields. Another object of the present invention is to provide a method for driving an electro-optical device, which sequentially selects lines and turns on or off pixels corresponding to the selected scanning lines.

According to the driving method of the electro-optical device,
In one field, the application time of the voltage for turning on (or off) the pixel is pulse-width modulated according to the gradation of the pixel, so that gradation display by effective value control is performed. At this time, in each subfield, it is only necessary to instruct the ON or OFF of the pixel. Therefore, as the instruction signal to the pixel, a binary signal (that is, H level or L level) is used.
Digital signal that can only take on a level). Therefore, according to the present invention, since the signal applied to the pixel is a digital signal, display unevenness due to non-uniformity such as element characteristics and wiring resistance is suppressed, so that high-quality and high-definition display is possible.

Further, according to the present invention, since the all-pixel off period in which all the pixels are simultaneously turned off at the beginning of one field is provided, the all pixel off period is caused by the difference in the on-voltage or off-voltage application start timing of each pixel. Thus, it is possible to prevent the applied voltage effective value from becoming non-uniform.

[0011] In this specification, terms such as "all pixels" or "all pixels" refer to all of the pixels included in the electro-optical device which are to be driven to perform image display. Say. Similarly, “all data lines” in the present specification refers to all of the data lines connected to the pixel to be driven to perform image display, out of all the data lines included in the electro-optical device. means. That is, words such as “all pixels” or “all pixels” mean exactly all the pixels when an image is displayed using all the pixels included in the electro-optical device. On the other hand, when an image is displayed using some of the pixels included in the electro-optical device, it means all of the partial pixels to be displayed. That is, even if the pixel is included in the electro-optical device, a pixel that is not a display target is not included in “all pixels” or “all pixels” in this specification. The same applies to “all data lines” in this specification.

In the first aspect of the present invention, a pixel may be turned off in a last subfield of a plurality of subfields included in each field. This makes it possible to more reliably avoid a situation where the effective voltage value applied to each pixel becomes non-uniform.

According to a second aspect of the present invention, there is provided an electric device for driving a pixel comprising a memory and a pixel electrode disposed corresponding to each intersection of a plurality of scanning lines and a plurality of data lines in accordance with gradation data. A drive circuit for an optical device, wherein each field is divided into an all-pixels off period and a plurality of subfields, and a voltage for turning off the pixels is applied to all the pixels simultaneously during the all-pixels off period. A data conversion circuit for generating a binary signal for instructing application of a voltage for turning on each pixel or a voltage for turning off each pixel in each of the plurality of subfields. A data conversion circuit that generates the binary signal corresponding to each pixel for each field from gradation data corresponding to each pixel, and can supply a signal from a data line to a pixel for each subfield A scanning line driving circuit for sequentially supplying a scanning signal to each of the scanning lines, and for turning a pixel on or off according to a binary signal from the data conversion circuit while the scanning signal is supplied. And a data line drive circuit for supplying the data signal to each data line.

The second aspect of the present invention embodies the first aspect of the present invention as a drive circuit for an electro-optical device, and can provide effects similar to those of the first aspect of the present invention.

In the second invention, the all-pixels off circuit simultaneously supplies an all-pixels selection signal enabling supply of a signal from a data line to the pixels to all the pixels during the all-pixels off period. And a signal supply circuit for simultaneously supplying a signal for turning off the pixel to all data lines while the all pixel selection signal is supplied. It is preferable that the driving circuit is a driving circuit for an electro-optical device.

By doing so, due to the difference in the application start timing of the ON voltage or the OFF voltage of each pixel,
The applied voltage effective value can be prevented from becoming non-uniform.

Further, in the second invention, the data conversion circuit instructs, in a last subfield among a plurality of subfields included in each field, application of a voltage for turning off a pixel. A driving circuit for an electro-optical device characterized by generating a binary signal may be used.

By doing so, it is possible to more reliably avoid the situation where the effective value of the voltage applied to each pixel becomes non-uniform.

Further, in the second invention, the data line driving circuit includes: a shift register for sequentially shifting and outputting a latch pulse signal supplied at the beginning of a horizontal scanning period according to a clock signal; And a latch circuit for simultaneously latching the binary signals distributed to a plurality of systems by a signal shifted by the shift register.

Since one field is divided into a plurality of subfields, in a configuration in which data is supplied in a dot-sequential manner in each subfield, a situation in which writing time to pixels is not sufficient is expected. Therefore, if the binary signals distributed to a plurality of systems are simultaneously latched as in the present invention, the number of stages of the shift register can be reduced and the time required for the latch circuit to latch data can be reduced. It is possible to do.

Further, the data line driving circuit sequentially shifts and outputs a latch pulse signal supplied at the beginning of a horizontal scanning period according to a clock signal, and shifts the binary signal by the shift register. A first latch circuit for sequentially latching the received signals,
A second latch circuit that latches the binary signal latched by the first latch circuit based on the latch pulse signal and simultaneously outputs the data signal to a corresponding data line as the data signal. It is also desirable to

As described above, before data is supplied to the data line, the data is temporarily latched by the first latch circuit in a dot-sequential manner, and the latched signal is supplied to the second latch circuit.
Latch circuit is simultaneously latched by a latch pulse signal supplied at the beginning of the horizontal scanning period, and supplied to the data line, it is possible to secure a relatively long time of one horizontal scanning period as a pixel writing time. It becomes possible.

Now, in such a configuration, the first
Is desirably configured to simultaneously latch the binary signals distributed to a plurality of systems by a signal shifted by the shift register.

According to this configuration, the number of stages of the shift register can be reduced, and the time required for the first latch circuit to latch data can be shortened.

Further, according to a third aspect of the present invention, there is provided a pixel comprising a memory and a pixel electrode, which is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and setting each field to an all pixel off period. And a plurality of sub-fields, and in the all-pixels off period, an all-pixels off circuit that simultaneously applies a voltage for turning off a pixel to all the pixels, and in each of the plurality of sub-fields, A data conversion circuit for generating a binary signal for instructing application of a voltage for turning on each pixel or a voltage for turning off each pixel, wherein the binary signal corresponding to each pixel is applied to each pixel for each subfield. A data conversion circuit that generates from the corresponding gradation data;
A scanning line driving circuit for sequentially supplying a scanning signal for enabling a signal from a data line to a pixel to each of the scanning lines for each of the sub-fields; A data line driving circuit for supplying a data signal for turning on or off a pixel to each data line in accordance with a binary signal from a circuit. .

In the third aspect, the first aspect is embodied as an electro-optical device, and the same effects as those of the first aspect can be obtained.

The memory according to the third aspect of the present invention writes the data supplied to a switching element that is turned on by the scanning signal and a data line corresponding to the switching element that is turned on by the scanning signal, and And a capacitor for holding written data when the element is turned off. In this configuration, simplification is easy because it is a DRAM.

Here, it is desirable that the switching element has a configuration in which a P-channel type transistor and an N-channel type transistor are complementarily combined. When the switching element is a single-channel transistor, it is necessary to set the data voltage in consideration of the threshold voltage. According to this embodiment, it is not necessary to consider the threshold voltage.

On the other hand, the memory writes data supplied to a switching element that becomes conductive by the scanning signal and data supplied to a corresponding data line when the switching element becomes conductive, and switches the switching element to a non-conductive state. It is also desirable to have a configuration composed of two inverters, each holding the written data, wherein the output of one inverter is the input of the other inverter. In this configuration, since the data is self-stored to be an SRAM, the operation margin can be expanded. Further, in the third aspect, it is preferable that the pixel, the all-pixels off circuit, the scanning line driving circuit, and the data line driving circuit are formed on a semiconductor substrate, and the pixel electrode has reflectivity.

Since the electron mobility of the semiconductor substrate is high, it is possible to reduce the size of the switching elements formed on the substrate, the constituent elements of the drive circuit, etc. as well as the high-speed response.

Further, in order to achieve the above object, the electronic apparatus according to the fourth aspect of the present invention includes the above-mentioned electro-optical device, so that a D / A conversion circuit and an operational amplifier are not required. In addition, there is no influence from the characteristics of the D / A conversion circuit and the operational amplifier and the non-uniformity of various wiring resistances. Therefore, according to this electric device, the cost can be suppressed and high-quality and high-definition gradation display can be performed.

[0032]

Embodiments of the present invention will be described below with reference to the drawings. Such an embodiment shows one aspect of the present invention, and does not limit the present invention, and can be arbitrarily changed within the scope of the present invention.

A: Principle of the driving method of the electro-optical device according to the present invention First, in order to facilitate understanding of the device according to the present embodiment,
A method for driving the electro-optical device according to the present embodiment will be described.

Generally, in a liquid crystal device using a liquid crystal as an electro-optical device, the relationship between the effective voltage value applied to the liquid crystal layer and the relative transmittance (or reflectance) is such that a black display in which no voltage is applied is used. Taking the Mary Black mode as an example, the relationship is as shown in FIG. The relative transmittance is a value obtained by normalizing the minimum value and the maximum value of the transmitted light amount as 0% and 100%, respectively.
As shown in FIG. 5A, the transmittance of the liquid crystal is 0% when the effective voltage value applied to the liquid crystal layer is smaller than VTH1.
However, when the applied voltage effective value is equal to or more than VTH1 and equal to or less than VTH2, the voltage increases nonlinearly with respect to the effective value of the voltage. When the applied effective voltage value is equal to or higher than VTH2, the transmittance of the liquid crystal decreases as the applied effective voltage value increases.

Here, it is assumed that the electro-optical device according to the present embodiment performs 8-gradation display, and that the gradation data represented by 3 bits indicates the transmittance shown in FIG. At this time, assuming that voltage effective values to be applied to the liquid crystal layer according to the respective transmittances are V0 to V7, according to the conventional technology, these voltages V0 to V7 themselves are applied to the liquid crystal layer. Had become. Therefore, in particular, the voltages V1 to V6 corresponding to the intermediate gradation are easily affected by the characteristics of analog circuits such as a D / A conversion circuit and an operational amplifier, and variations in various wiring resistances.
Since the pixels tend to be non-uniform, it is difficult to display high-quality and high-definition gradations.

Therefore, in the electro-optical device according to the present embodiment, the pixels are driven by the following method. In this specification, one field is a time required to form one raster image by performing horizontal scanning and vertical scanning in synchronization with a horizontal scanning signal and a vertical scanning signal. Therefore, one frame in the non-interlace system or the like also corresponds to one field in the present invention.

First, in this embodiment, a configuration is adopted in which the voltage instantaneously applied to the liquid crystal layer is, for example, one of the voltage VL (= 0 V) corresponding to the L level and the voltage VH corresponding to the H level. take. By controlling the ratio of the time length of applying the voltage VL to the liquid crystal layer to the time length of applying the voltage VH in one field period, the effective voltage value applied to the liquid crystal layer becomes V1, V2. ,..., V7. The details are as follows.

First, as shown in FIG. 5B, one field is divided into nine periods. Then, according to the gradation data given to each pixel, of these periods, a period during which the voltage VH is applied to the liquid crystal layer,
The period for applying L is determined. By controlling the length of time during which the voltage VL is applied to the liquid crystal layer and the length of time during which the voltage VH is applied to the liquid crystal layer in this manner, the above-described effective voltage values V1, V
2,..., V7 can be given to the liquid crystal layer;
The gradation display corresponding to the voltage can be performed.

However, in the present invention, of a plurality of periods obtained by dividing one field, in the first period,
The voltage VL is applied simultaneously to the liquid crystal layers of all the pixels regardless of the gradation data. Although details will be described later, by providing such a period at the beginning of one field, the effective voltage value applied to each pixel can be made uniform regardless of the position of each pixel. As shown in FIG. 5B, the first period of this one field is hereinafter referred to as an all-pixel off period. Further, each of the eight periods in one field excluding the all pixel off period is referred to as a subfield S for convenience.
Called f1 to Sf8.

Further, in the embodiment described below,
In the last period of one field, that is, in the subfield Sf8, the voltage VL is applied to the liquid crystal layer of each pixel regardless of the gradation data. Although details will be described later, such a period is set to one.
By providing the pixel at the end of the field, even when the pixels are turned on over all the subfields Sf1 to Sf7 except the subfield Sf8, the effective voltage applied to each pixel is changed regardless of the position of each pixel. It can be uniform. This subfield Sf8
Is set to a time length longer than the time required to scan all the scanning lines.

As described above, in the electro-optical device according to the present embodiment, each of the sub-fields S excluding the all-pixel off period and the sub-field Sf8 in one field.
For each of f1 to Sf7, a voltage VL or VH is applied to the liquid crystal layer of the pixel according to the gradation data. Here, the above-described voltage VH depends on the sub-field S
When the voltage VH is applied to the liquid crystal layer over f1 to Sf7, the effective voltage value applied to the liquid crystal layer in one field is set to be the same as V7 in FIG. As a result, the subfield Sf
If a voltage VL (= 0V) is applied to the liquid crystal layer over 1 to Sf7, the transmittance becomes 0%, and the subfields Sf1 to Sf7
If the voltage VH is applied to the liquid crystal layer over Sf7, the transmittance becomes 100%. Further, among these subfields Sf1 to Sf7, the subfield for applying the voltage VL to the liquid crystal layer and the subfield for applying the voltage VH are determined according to the gradation data, so that the subfield is applied to the liquid crystal layer. V1, V2,..., V
6, and as a result, gradation display can be realized.

For example, for a certain pixel, the gradation data (0
01), that is, when performing gradation display in which the transmittance of the pixel is 14.3%, in one field (1f), a voltage is applied to the liquid crystal layer of the pixel in the subfield Sf1. While VH is applied, the voltage VL is applied to the liquid crystal layer in the other subfields Sf2 to Sf7 and the above-described all-pixel off period and subfield Sf8. Here, since the effective voltage value is obtained by a square root obtained by averaging the square of the instantaneous voltage value over one cycle (one field), the subfield Sf
If the time length of 1 is set to (V1 / VH) ² with respect to the time length of 1 field (1f), the voltage is applied to the liquid crystal layer in one field (1f) by the above-described voltage application. The effective voltage value is V1.

Also, for example, for a certain pixel, the gradation data
Data (010), that is,
When performing gradation display with a transmittance of 28.6%, one screen
Field (1f), subfields Sf1 to Sf2
In the case of applying the voltage VH to the liquid crystal layer of the pixel,
The other subfields Sf3 to Sf7 and all pixels
In the off period and the subfield Sf8, the liquid
VL is applied to the crystal layer. Because of this,
Field Sf1 to Sf2 is set to one field (1
(V2 / VH) for the time length of f)^TwoTime length
If set, one field (1
In (f), the effective voltage value applied to the liquid crystal layer is V2.
You. Here, the subfield Sf1 is, as described above,
(V1 / VH) ^TwoBecause the time length is set to
As for the subfield Sf2, one field (1
f) (V2 / VH)^Two− (V1 / VH)^TwoBecomes
The time length may be set.

Similarly, for example, for a certain pixel,
Data (011), that is, the pixel
When performing gradation display with a transmittance of 42.9%,
Field (1f), subfields Sf1 to Sf
In 3, the voltage VH is applied to the liquid crystal layer of the pixel.
On the other hand, the other subfields Sf4 to Sf7 and all
In the elementary off period and the subfield Sf8,
A voltage VL is applied to the liquid crystal layer. For this reason,
The time length of the fields Sf1 to Sf3 is set to one field (1
f) (V3 / VH)^TwoTime length
In this case, the above voltage application causes one field (1f).
The effective voltage value applied to the liquid crystal layer is V3. here,
The subfields Sf1 to Sf2 are (V
2 / VH) ^TwoBecause the time length is set to
Regarding the field Sf3, one field (1f)
(V3 / VH)^Two− (V2 / VH)^TwoTime length
It can be seen that it should be set to.

Hereinafter, similarly, other subfields S
Each period of f4 to Sf7 is determined.

As described above, the subfields Sf1 to Sf
7, the voltage applied to the liquid crystal layer of each pixel is binary, VL or VH. The gradation display corresponding to the ratio becomes possible.

In the following, for convenience of explanation, it is assumed that the voltage VH is at the H level and the voltage VL is at the L level for the logic amplitude.

B: Configuration of the Embodiment FIG. 1 is a block diagram showing the electrical configuration of the electro-optical device according to the first embodiment of the present invention. This electro-optical device uses a twisted nematic (T) as an electro-optical material.
This is a liquid crystal device using an N) type liquid crystal, in which an element substrate and a counter substrate are adhered to each other with a certain gap therebetween, and a liquid crystal as an electro-optical material is sandwiched in this gap. Also, in this electro-optical device, a transparent substrate such as glass or quartz is used as an element substrate, and together with a thin film transistor (TFT) for driving pixels on the element substrate,
Complementary TFTs and the like that constitute the peripheral drive circuit are formed. FIG. 1 is a block diagram showing a configuration of a circuit formed on the element substrate.

As shown in FIG. 1, in the display area 101a on the element substrate, a plurality of scanning lines 112 are formed extending in the X (row) direction, and a plurality of data lines 114 are formed in the Y (column). )
It is formed to extend in the direction. Then, the pixel 110
Are provided corresponding to the intersections of the scanning lines 112 and the data lines 114, and are arranged in a matrix. In this embodiment, for convenience of explanation, the total number of the scanning lines 112 is m and the total number of the data lines 114 is n (m and n are integers of 2 or more), and a matrix type of m rows × n columns is used. Although described as a display device, the invention is not intended to be limited to this.

As a specific configuration of the pixel 110, for example, the configuration shown in FIG. In this configuration, a transistor (thin film transistor: TFT) 116
The gate of the scan line 112 and the source of the data line 114
In addition, a drain is connected to the pixel electrode 118, and a liquid crystal 105 as an electro-optical material is interposed between the pixel electrode 118 and the counter electrode 108 to form a liquid crystal layer. Here, the pixel electrode 118 and the ground potential GND (=
A storage capacitor 119 is formed between 0 V and an L level of a data signal to be described later, a counter electrode signal LCCOM or another potential. This storage capacity 11
Reference numeral 9 denotes a capacitor provided after the voltage is applied to the pixel electrode 118 via the transistor 116 to maintain the applied voltage substantially constant for a required time. The counter electrode 108 is a transparent electrode formed on one surface of the counter substrate so as to face the pixel electrode 118.

In the configuration shown in FIG. 2A, only one channel type (for example, N-channel type) is used as transistor 116. Therefore, when a voltage is applied from the data line 114 to the pixel electrode 118 via the transistor 116, when the voltage applied to the data line 114 reaches a voltage lower than the voltage on the scan line 112 by the threshold voltage of the transistor 116, The transistor 116 is turned off. Therefore, when the voltage applied to the scanning line 112 is not higher than the voltage applied to the data line 114 by the threshold voltage of the transistor 117,
The voltage applied to the pixel electrode 118 cannot be matched with the voltage on the data line 114, and an offset voltage occurs between the two voltages.

On the other hand, as shown in FIG.
With a transmission gate configuration in which a channel type transistor and an N-channel type transistor are complementarily combined, the voltage on the data line 114 is applied to the pixel electrode 118 with a very small error without generating such an offset voltage. be able to. However, in this complementary configuration, it is necessary to supply signals of inversion levels to each other as scanning signals, so that two scanning lines 112a and 112b are required for one row of pixels 110.

As another configuration of the pixel 110, as shown in FIG. 2C, a configuration using an SRAM composed of two inverters each having the output of one inverter serving as the input of the other inverter is also available. Also desirable. FIG.
In (c), Ta3 and Ta4 and Ta5 and Ta6 constitute an inverter. In this configuration, since the voltage written from the data line 114 is self-stored to be an SRAM, the operation margin can be expanded. However, in this SRAM configuration, since it is necessary to supply mutually exclusive levels as voltages to be written from the data lines, the transistors Ta1, Ta2, Ta3, Ta4, T4
a5, Ta6 and data lines 114a, 114b are required.

Referring again to FIG. 1, a timing signal generation circuit 200 generates various timing signals and clock signals in accordance with a vertical scanning signal Vs, a horizontal scanning signal Hs, and a dot clock signal DCLK supplied from a higher-level device (not shown). It is a circuit for performing. The main signals among the signals generated by the timing signal generation circuit 200 are as follows. a. Counter electrode signal LCCOM The counter electrode signal LCCOM is a signal supplied to the counter electrode 108 (see FIG. 2) formed on the counter substrate and the input terminal of the switch 121 connected to one end of each data line 114. . In the present embodiment, the counter electrode signal LCCO
M is a signal that repeats level inversion every field, such as from H level to L level, from L level to H level. b. All-pixel selection signal SL This all-pixel selection signal SL is connected to one input terminal of the OR gate 120 connected to each scanning line 112 and each data line 11
4 is a signal supplied to the gate of the switch 121 connected to the switch 4. The all-pixel selection signal SL is at the H level only during the period from the start of one field until the above-described all-pixel off period elapses.
That is, the signal is at the L level in the subfields Sf1 to Sf8. c. Start pulse DY This start pulse DY is a pulse signal output at the beginning of each subfield obtained by dividing a period excluding the all pixel off period from one field into eight. d. Clock Signal CLY This clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side). e. Latch pulse LP This latch pulse LP is a pulse signal output at the beginning of the horizontal scanning period, and is output when the level of the clock signal CLY changes (that is, rises and falls). f. Clock signal CLX This clock signal CLX is a signal that defines a so-called dot clock.

The above is the outline of the main signals generated by the timing signal generation circuit 200.

Next, the scanning line driving circuit 130 is a so-called Y shift register, which transfers a start pulse DY supplied at the beginning of each subfield in accordance with a clock signal CLY, and scans each of the scanning lines 112. , Gm are sequentially output as signals G1, G2, G3,..., Gm.

Here, one end of each scanning line 112 (the left end of each scanning line 112 in FIG. 1) is connected to the output terminal of an OR gate 120 provided corresponding to each scanning line 112. The OR gate 120 has two input terminals. One input terminal is supplied with a scanning signal Gi (i is an integer satisfying 1 ≦ i ≦ m) output from the scanning line driving circuit 130. You. This scanning signal Gi is sequentially supplied to each scanning line 112 via each OR gate 120. On the other hand, the other input terminal of each OR gate 120 is supplied with the all-pixel selection signal SL output from the timing signal generation circuit 200. When the all-pixel selection signal SL becomes H level during the all-pixel off period in one field,
This all-pixel selection signal SL is transmitted to all the OR gates 120.
Are simultaneously supplied to each scanning line 112, and the transistors 116 of all the pixels 110 are turned on. As described above, the OR gate 120 constitutes the “all-pixel selection circuit” in the claims.

One end of each data line 114 is connected to the data line drive circuit 140, while the other end is connected to each data line 1
14 is connected to the output terminal of a switch 121 provided correspondingly. The input terminal of each switch 121 is connected to the wiring to which the above-mentioned counter electrode signal LCCOM is supplied. On the other hand, the gate of each switch 121 is connected to the wiring to which the above-described all-pixel selection signal SL is supplied.
When the H-level signal is applied, the device is turned on. That is, when the H-level all-pixel selection signal SL is supplied during the all-pixels off period, each switch 121 is turned on. As a result, the common electrode signal LCCOM is supplied to all the data lines 114 at once. . Note that each of the switches 121 may have a transmission gate configuration in which an N-channel transistor and a P-channel transistor are complementarily combined.
It may be composed of only one channel type transistor.

The data line driving circuit 140 converts the binary signal Ds to the data signals d1, d2,
.., dn to each data line 114 in order. FIG. 3 is a block diagram showing a specific configuration of the data line driving circuit 140. As shown in the figure, the data line driving circuit 140 includes an X shift register 1410 and a latch circuit 1420. The X shift register 1410 outputs the latch pulse LP supplied at the beginning of the horizontal scanning period to the clock signal C.
LX, and latch signals S1, S2, S3,.
.., Sn are sequentially output. The latch circuit 1420 converts the binary signal Ds output from the data conversion circuit 300 into the latch signals S1, S2, S3,.
At the falling edge of the data signal d1, d2, d
3,... Dn are sequentially output to the corresponding data lines 114.

Note that such a scanning line driving circuit 130,
The transistors forming the data line driving circuit 140, the OR gate 120, and the switch 121 can be formed from TFTs formed on an element substrate.

Next, the data conversion circuit 300 will be described. As described above, in the present embodiment, the period excluding the all pixel off period from one field is divided into eight subfields Sf1 to Sf8, and each of these subfields corresponds to 3-bit grayscale data. The on / off driving of the pixel 110 is performed to display an image of eight gradations. The data conversion circuit 300 generates a binary signal Ds for instructing on / off driving of the pixel in each subfield based on gradation data corresponding to the pixel. FIG.
4A is a truth table showing a function of the data conversion circuit 300 when the common electrode signal LCCOM is at the H level, and FIG. 4B is a data conversion when the common electrode signal LCCOM is at the L level. 4 is a truth table showing functions of the circuit 300.

In FIG. 4A, the counter electrode signal LC
Since it is assumed that COM is at the H level, the binary signal Ds at the H level has an effect of turning off the pixel, and the binary signal Ds at the L level has an effect of turning on the pixel. On the other hand, in FIG. 4B, since it is assumed that the counter electrode signal LCCOM is at the L level, the H-level binary signal Ds has an effect of turning on the pixel, and the L-level signal DCOM has the L-level. The binary signal Ds has an effect of turning off the pixel.

Specifically, for example, the counter electrode signal LCC
In a field where OM is at the H level, a certain pixel 1
Assuming that (011) is given as the ten gradation data, the data conversion circuit 300 outputs the L-level binary signal Ds in the subfields Sf1 to Sf3 according to the truth table shown in FIG. On the other hand, in subfields Sf4 to Sf8, H-level binary signal Ds is output. In the subfields Sf1 to Sf3, the L-level voltage is applied to the pixel electrode 1 of the pixel 110.
18, the voltage applied to the liquid crystal layer is VH
, And the pixel 110 is turned on. On the other hand, in the subfields Sf4 to Sf8, as a result of the H-level voltage being applied to the pixel electrode 118 of the pixel 110,
The voltage applied to the liquid crystal layer becomes 0 V, and the pixel 110
Is turned off.

On the other hand, assuming that the gradation data (011) is given in the subfield in which the common electrode signal LCCOM is at the L level, the data conversion circuit 3
00 is an H level binary signal D in the subfields Sf1 to Sf3 according to the truth table shown in FIG.
While outputting s, an L level binary signal Ds is output in the subfields Sf4 to Sf8. Then, in the subfields Sf1 to Sf3, the H level voltage is applied to the pixel electrode 118 of the pixel 110, and as a result, the voltage applied to the liquid crystal layer becomes VH,
10 is turned on. On the other hand, subfields Sf4 to
In Sf8, as a result of the L-level voltage being applied to the pixel electrode 118 of the pixel 110, the voltage applied to the liquid crystal layer becomes 0V, and the pixel 110 is turned off.

As shown in FIGS. 4A and 4B, the subfield Sf is independent of the gradation data.
The binary signal Ds corresponding to 8 is at a voltage level that is turned off. That is, in the subfield Sf8, the pixel 110 is turned off regardless of the gradation data. This is to make the voltage applied to all the pixels 110 uniform without being affected by the writing timing of the data signal that differs depending on the position of each pixel 110 (details will be described later).

Since the binary signal Ds generated in the data conversion circuit 300 needs to be output in synchronization with the operations of the scanning line driving circuit 130 and the data line driving circuit 140, as shown in FIG. The conversion circuit 300 is supplied with a start pulse DY, a latch pulse LP defining the beginning of a horizontal scanning period, and a clock signal CLX corresponding to a dot clock signal. Furthermore, it is necessary to switch the conversion rule from the grayscale data to the binary signal Ds to one of FIGS. 4A and 4B in synchronization with the inversion of the voltage level of the common electrode signal LCCOM. The data conversion circuit 300 is also supplied with the counter electrode signal LCCOM.

In this embodiment, it is preferable that the transistors included in the scanning line driving circuit 130 and the data line driving circuit 140 are formed on the element substrate by the same process as the transistor in each pixel. When the element substrate is an insulating substrate such as glass or quartz as in this embodiment, each transistor is formed as a thin film transistor, but the element substrate may be a semiconductor substrate. It is formed as a MOS transistor built in a substrate.

C: Operation of Embodiment Next, the operation of the electro-optical device according to the above embodiment will be described. 6 and 7 are timing charts showing the operation of the electro-optical device.

As shown in FIG. 6, the all-pixel selection signal SL
Is at the H level during the all pixel off period from the start of each field.

First, in the field where the common electrode signal LCCOM is at the H level, when the all-pixel selection signal SL goes to the H level, the all-pixel selection signal SL is output to all the scanning lines 112 via the OR gate 120. . As a result, the transistors 116 of all the pixels 110 are simultaneously turned on. On the other hand, the H-level all-pixel selection signal S
When L is supplied, all the switches 121 connected to the data line 114 are turned on. As a result, the common electrode signal LCCOM is simultaneously supplied to all the data lines 114. Now, all pixels 110
Transistor 116 is in a conductive state, so that the counter electrode signal LCCOM supplied to each data line 114 is
Is applied to the pixel electrode 118 via the transistor 116. On the other hand, the counter electrode 108 has a counter electrode signal L
Since CCOM is applied, the voltage applied to the liquid crystal layers of all the pixels 110 is 0V. As a result, in the all-pixel off period in which the all-pixel selection signal SL is at the H level, all the pixels 110 are simultaneously turned off. As is clear from this, the time length of the all-pixel selection period needs to be long enough to turn off all the pixels 110.

Next, when the all pixel off period elapses, the start pulse DY is sequentially output from the timing signal generation circuit 200 at each start timing of eight subfields in one field.

Here, when a start pulse DY defining the start of the subfield Sf1 is supplied, the scanning line driving circuit 130 (see FIG. 1) transfers this start pulse DY in accordance with the clock signal CLY, and as a result, the data Within the transfer period (1 Va), the scanning signals G1, G2, G3,.
, Gm are sequentially output. The scanning signals G1, G2, G3,..., Gm each have a pulse width corresponding to a half cycle of the clock signal CLY.
The data transfer period (1 Va) is a period from the start of each subfield to the end of the supply of the scanning signal to all the scanning lines 112, and the time length is the same as the time length of each subfield. Or a shorter time length than that (ie, 1 Va ≦ Sfk (k is an integer satisfying 1 ≦ k ≦ 8) is satisfied). The scanning signal G output from the scanning line driving circuit 130
i is sequentially supplied to each scanning line 112 via the OR gate 120. Here, first, the case where the scanning signal G1 is output from the scanning line driving circuit 130 will be considered.

The scanning signal G1 is supplied to the first scanning line 112 counted from the top in FIG.
The transistors 116 of all the pixels 110 (n pixels located in the first row) connected to the transistor 12 are turned on.

On the other hand, at the falling timing of the clock signal CLY, that is, at the rising timing of the scanning signal G1, the latch pulse LP is output from the timing signal generation circuit 200. The X shift register 1410 in the data line driving circuit 140 outputs the latch pulse LP
Are transferred in accordance with the clock signal CLX. As a result, the latch signals S1, S2, S3,..., Sn are sequentially output during the horizontal scanning period (1H). Note that the latch signals S1, S
, Sn are clock signals CL, respectively.
It has a pulse width corresponding to a half cycle of X.

Then, the latch circuit 1420 in FIG.
Latches the binary signal Ds to the pixel 110 corresponding to the intersection of the first scanning line 112 counted from the top and the first data line 114 counted from the left at the falling of the latch signal S1, The first data line 114 counting from the left
As a data signal d1. Next, the latch signal S
2, the first scanning line 11 counted from the top
The binary signal Ds to the pixel 110 corresponding to the intersection of 2 with the second data line 114 counted from the left is latched and output as the data signal d2 to the second data line 114 counted from the left. Thereafter, similarly, the pixel 11 corresponding to the intersection of the first scanning line 112 counted from the top and the j-th (j is an integer satisfying 1 ≦ j ≦ n) data line 114 counted from the left.
The binary signal to 0 is sequentially latched and output to the data line 114 as a data signal dj. The same operation is performed on the data signal dn for the n-th data line 114 counted from the left.
Repeat until is supplied. The data conversion circuit 30
Needless to say, “0” converts the grayscale data of each pixel 110 into a binary signal Ds and outputs it in accordance with the latch timing of the latch circuit 1420.

Now, the first scanning line 112 counted from the top
Is turned on by the supply of the scanning signal G1. Therefore, data signals sequentially supplied to the data lines 114 from the data line driving circuit 140 are sequentially written to the pixel electrodes 118 of the respective pixels 110 via the transistors 116.

Then, the same operation is repeated until the scanning signal Gm corresponding to the m-th scanning line 112 is output. That is, 1 where a certain scanning signal Gi is output
In the horizontal scanning period (1H), the i-th scanning line 11
Data signal d1 for n pixels 110 corresponding to 2
To dn are performed dot-sequentially. Note that the data signal written to the pixel 110 is held until a new data signal is written in the next subfield Sf2.

After that, the same operation is repeated every time the start pulse DY defining the start of the subfield is supplied. When the time length of the data transfer period is equal to the time length of any of the subfields (that is, 1
When Va = Sfk), a voltage is applied to the pixel connected to the scanning line 112 located at the lowest position at the last timing of the subfield. However, writing of a new voltage to the pixel is performed at the last timing of the next subfield, so that the period during which the voltage is applied to the pixel and the other scanning lines And the period during which the voltage is applied to the pixel connected to. As a result, the voltage application period for each pixel is the same in each subfield.

Further, even when the field is switched and the counter electrode signal LCCOM is inverted to the L level, the same operation is repeated in each subfield. However, in the field where the common electrode signal LCCOM is at the L level, the data conversion circuit 300
The conversion from the grayscale data to the binary signal Ds is performed according to the truth table shown in FIG.

Next, the voltage applied to the liquid crystal layer in the pixel 110 by performing such an operation will be discussed. FIG. 7 is a timing chart showing the relationship between the gradation data and the voltage waveform applied to the pixel electrode 118 of the pixel 110 corresponding to each gradation data.

For example, when grayscale data (000) is given to a certain pixel 110 in a field where the common electrode signal LCCOM is at the H level, during the all pixel off period when the all pixel selection signal SL is at the H level Is a counter electrode signal L for the pixel electrode 118 of the pixel 110.
Since CCOM is applied, the voltage applied to the liquid crystal layer of the pixel becomes 0 V, and the pixel is turned off. Subsequently, after the lapse of the all-pixels off period, as a result of following the truth table shown in FIG. 4A, the pixel electrodes 118 of the pixel 110 have the subfields Sf1 to Sf1 as shown in FIG.
An H level data signal is written over f8.
Here, since the voltage level of the H-level data signal is the same as the voltage level of the common electrode signal LCCOM applied to the common electrode 118, the voltage applied to the liquid crystal layer of the pixel 110 is 0V. . Therefore, the effective voltage value applied to the liquid crystal layer of the pixel in one field is 0.
V. As a result, the transmittance of the pixel 110 becomes 0% corresponding to the gradation data (000).

On the other hand, when the common electrode signal LCCOM goes low in the next field, the common electrode signal LCCOM is applied to the pixel electrode 118 during the all-pixel off period, and the pixel 110 is turned off. On the other hand, after the lapse of the all-pixels off period, as a result of following the truth table shown in FIG. 4B, the pixel electrode 118 of the pixel 110 has the subfield S as shown in FIG.
An L-level data signal is written over f1 to Sf8, and the pixel 110 is turned off. As a result, the pixel 110 is turned off over one field, so that the transmittance of the pixel 110 is H when the common electrode signal LCCOM is H.
It is 0% as in the case of the level.

In the field where the common electrode signal LCCOM is at the H level, when the gradation data (001) is given to a certain pixel 110, the liquid crystal of the pixel 110 is similarly turned off during the all pixel off period. The voltage applied to the layer will be 0V. Subsequently, after the lapse of the all-pixels off period, according to the truth table shown in FIG. 4A, the counter electrode signal LC in the subfield Sf1 is obtained.
COM and an L-level data signal, which is an inverted level, are written to the pixel electrode 118, while the subfield Sf2 is
In Sf8 to Sf8, the H-level data signal is
18 is written. That is, the subfield Sf1
In this case, the voltage VH is applied to the liquid crystal layer of the pixel 110.
While the other subfields Sf2 to Sf
At f8, the voltage applied to the liquid crystal layer becomes 0V. Here, the ratio of the time length of the subfield Sf1 to the time length of one field (1f) is (V1 /
VH) ² , and the voltage VH is applied during this period, so that the effective value of the voltage applied to the liquid crystal layer of the pixel 110 in one field is V1. Therefore, the pixel 1
The transmittance of 10 is 1 corresponding to the gradation data (001).
That is 4.3%.

On the other hand, when the counter electrode signal LCCOM goes low in the next field, the voltage applied to the liquid crystal layer of the pixel 110 becomes 0 V during the all pixel off period. In the subfield Sf1, an H-level data signal is written to the pixel electrode 118, and the voltage VH is applied to the liquid crystal layer of the pixel. On the other hand, in the subfields Sf2 to Sf8, the pixel electrode 118 is written.
And the voltage applied to the liquid crystal layer of the pixel becomes 0V. As a result, as in the case where the common electrode signal LCCOM is at the H level, the effective voltage value applied to the liquid crystal layer in one field corresponds to the gradation data (001). As is clear from the above, the voltage applied to the liquid crystal layer in the subfield Sf1 in the field where the counter electrode signal LCCOM is at the L level is the subfield Sf1 in the field where the counter electrode signal LCCOM is in the H level. Has a polarity opposite to the voltage applied to the liquid crystal layer, and its absolute value is equal. By doing so, it is possible to avoid the application of the DC component to the liquid crystal layer, so that the effect of preventing the deterioration of the liquid crystal 105 is obtained. This effect can be obtained in exactly the same way when other gradation data is given.

Next, when grayscale data (010) is given to a certain pixel 110 in a field where the common electrode signal LCCOM is at the H level, as is clear from FIG. Is the pixel 110
The voltage applied to the liquid crystal layer is 0V. In the subfields Sf1 and Sf2, the pixel 11
While the voltage VH is applied to the 0 liquid crystal layer, the voltage applied to the liquid crystal layer is 0 V in the other subfields Sf3 to Sf8. Here, the ratio of the time length of the subfields Sf1 to Sf2 to the time length of one field (1f) is (V2 / VH) ² ,
Since the voltage VH is applied during this period, the effective voltage applied to the liquid crystal layer of the pixel in one field is V2
Becomes Therefore, the transmittance of the pixel 110 is 28.6% corresponding to the gradation data (010). The same applies to a field where the common electrode signal LCCOM is at the L level.

The same applies to the case where other gradation data is given. That is, in the off period of all pixels in one field, the voltage applied to the liquid crystal layer of the pixel is always 0 V regardless of the gradation data. Further, in the subfields Sf1 to Sf8 after the lapse of the all-pixels off period, the subfields in which the voltage applied to the liquid crystal layer becomes VH according to the truth table shown in FIG. , A subfield where the applied voltage is 0 V is determined. Then, the effective value of the voltage applied to the liquid crystal layer in one field is controlled, and the transmittance corresponding to the gradation data is obtained.

As described above, according to the electro-optical device according to the present embodiment, the period excluding the all pixel off period in one field is a plurality of subfields Sf1 to Sf8.
, And either 0 V or voltage VH is applied to the liquid crystal layer of each pixel for each subfield, and 1
The effective voltage value in the field is controlled. For this reason, in the present embodiment, analog signals such as a high-precision D / A conversion circuit and an operational amplifier, which are indispensable for generating a voltage corresponding to the transmittance under the conventional technology, are processed. There is no need to provide a driving circuit or the like for a circuit for performing the above. Therefore, the circuit configuration is greatly simplified, and the cost of the entire apparatus can be reduced. Furthermore, since the voltage applied to the pixel is only the H level or the L level and is binary, display unevenness due to non-uniformity such as element characteristics and wiring resistance does not occur in principle.
Therefore, according to the electro-optical device according to the present embodiment, high-quality and high-definition gradation display can be performed.

In this embodiment, since all the pixels 110 are turned off at the beginning of each field, the data signal writing timing differs depending on the position of the pixel 110. And each pixel 1
It is possible to prevent the effective voltage applied to 10 from becoming non-uniform. The details are as follows.

Here, in order to explain the effect of the driving method according to the present embodiment, a driving method without the all-pixels off period (hereinafter referred to as “another driving method”) will be examined. That is, in another driving method, one field is divided into only a plurality of subfields without providing an all pixel off period in one field. Each pixel is driven on and off so that the ratio of the time for turning on the pixel 110 to the time for turning off the pixel 110 in one field is a ratio corresponding to the gradation data. Is obtained in accordance with the transmittance.

FIG. 8A is a timing chart exemplifying voltage waveforms applied to the first pixel and the last pixel when the above-mentioned other driving method is used. Here, the first pixel is a pixel to which a data signal is written first among all pixels for one screen, that is, a first scanning line counted from the top and a first data line counted from the left. Are pixels provided corresponding to the intersection of. The last pixel is a pixel to which a data signal is written last among all pixels for one screen, that is, an m-th scanning line counted from the top and an n-th data line counted from the left. Are pixels provided corresponding to the intersection of. In FIG. 8A, for the sake of convenience, the same gradation data is given to the first pixel and the last pixel, and according to the gradation data, the subfields Sf1 to Sf1 in one field are obtained.
It is assumed that the pixel is turned on only in Sf3 and the pixel is turned off in other subfields. It is also assumed that the field immediately before the field f1 ends with a subfield for turning off the pixel.

First, for the pixel electrode of the first pixel,
At the start of the field f1 (time Ta1 in FIG. 8), the counter electrode signal LCCOM and the inverted level data signal are written. As a result, the voltage VH is applied to the liquid crystal layer of the pixel, and the pixel is turned on. Strictly speaking, the timing at which a signal is written to the pixel electrode of the first pixel and the start timing of each subfield are not the same, but here, for the sake of convenience of description, it is assumed that these timings are the same. Advance.

Similarly, in the subfields Sf2 and Sf3, the counter electrode signal LCCOM and the signal of the inverted level are written to the pixel electrode of the first pixel, and the pixel is turned on.

Next, in the subfields after the subfield Sf4, the pixels are turned off. That is, at the start timing (time Ta2) of the subfield Sf4, a signal of the same level as the counter electrode signal LCCOM is written to the pixel electrode of the first pixel, and as a result, the first pixel is turned off. Become. Similarly, in the subfields Sf5 to Sf7, a signal of the same level as the counter electrode signal LCCOM is written to the pixel electrode, and as a result, the pixel is turned off.

As is clear from the above, the field f
1, the period during which the first pixel is in the ON state is at time Ta1.
To Ta2.

Next, when the above-mentioned other driving method is used,
Consider the voltage applied to the pixel electrode of the last pixel in the field f1. First, subfield S
At f1, a time Ta at which a signal is written to the pixel electrode of the first pixel is applied to the pixel electrode of the last pixel.
Time Ta after a lapse of data transfer period (1 Va) from 1
At 1 ', the counter electrode signal LCCOM and the inverted level signal are written, and the last pixel is turned on.
In the subsequent subfields Sf2 and Sf3, the pixels are similarly turned on. And the subfield S
At f4, the data transfer period (1V) starts at time Ta2 when the data signal is written to the pixel electrode of the first pixel.
At time Ta2 'after elapse of a), a signal of the same level as the counter electrode signal LCCOM is written to the pixel electrode of the last pixel. As a result, the pixel is at time Ta2 '.
From the off state. Therefore, the last pixel is in the ON state during a period from time Ta1 ′ at which the signal of the counter electrode signal LCCOM and the inverted level signal is written to time Ta2 ′ at which the signal of the same level as the counter electrode signal LCCOM is written. It is clear.

However, during the period from time Ta1 to Ta1 ', the L-level signal written to the pixel electrode of the last pixel in the field immediately before field f1 is maintained. On the other hand, since the counter electrode signal LCCOM is inverted to the H level at the time Ta1, the voltage applied to the liquid crystal layer of the pixel becomes VH during the period from the time Ta1 to Ta1 ′, and the last pixel is turned on. . After all, the period when the last pixel is in the ON state is Ta
This is a period from 1 to Ta2 ', which is an ON state longer than the period during which the first pixel is in the ON state, that is, the period Ta1 to Ta1', that is, the data transfer period (1 Va).

As described above, in the other driving method, the period during which the first pixel is in the ON state is different from the period during which the last pixel is in the ON state. Although the same grayscale data is given, the effective voltage value applied to the first pixel is different from the effective voltage value applied to the last pixel. As a result, despite the fact that they should be displayed with the same gradation,
There is a problem that the transmittance of each pixel is different, and the display becomes non-uniform depending on the position of the pixel.

On the other hand, according to the driving method of the present embodiment, such a problem does not occur. In this regard, FIG.
This will be described with reference to FIG. FIG. 8B is a diagram illustrating waveforms of voltages applied to the first pixel and the last pixel when the driving method according to the present embodiment is used. In FIG. 8B, the same gradation data is given to the first pixel and the last pixel as in the example of FIG. 8A. It is assumed that pixels are turned on only in the subfields Sf1 to Sf3.

First, in the field f1 in which the counter electrode signal LCCOM is at the H level, the pixel electrode of the first pixel is applied from the start of the field f1 (time Tb0) to the lapse of the all-pixel off period (time Tb1). ), The common electrode signal LCCOM is applied. As a result, the first pixel is turned off in the period.

Next, after the lapse of the all-pixels off period, at time Tb1, which is the start timing of the subfield Sf1, the counter electrode signal LCCOM is supplied to the first pixel electrode.
And the data signal of the inverted level is written. As a result,
The pixel is turned on. Subfields Sf2 and Sf
Similarly, at f3, the first pixel is turned on.

Further, at the start timing of subfield Sf4 (time Tb2), a data signal of the same level as counter electrode signal LCCOM is written to the pixel electrode of the first pixel, and as a result, the pixel is turned off. Similarly, in the subsequent subfields Sf4 to Sf8,
The first pixel is turned off. After all, the period during which the first pixel is in the ON state in the field f1 is from time Tb1 to time Tb1.
This is the period of Tb2.

On the other hand, the pixel electrode of the last pixel, like the first pixel, has a counter electrode signal LCCOM during the period from the start of the field f1 (time Tb0) to the lapse of the all-pixel off period (time Tb1). And a data signal of the same level is written. As a result, the last pixel is turned off.

Next, after the lapse of the all-pixels off period, at the time Tb1 'in the subfield Sf1 at the time Tb1' after the data transfer period (1 Va) has elapsed from the timing of writing the data signal to the first pixel (time Tb1). The electrode signal LCCOM and the data signal of the inverted level are written to the pixel electrode of the last pixel. As a result, the last pixel is turned on. Note that the data signal of the same level as the counter electrode signal LCCOM written to the pixel electrode during the all pixel off period is held until time Tb1 '. On the other hand, also in the subfields Sf2 and Sf3, the last pixel is similarly turned on.

Next, in the subfield Sf4, a time Tb2 ', which has elapsed by a data transfer period (1 Va) from a time Tb2 when a data signal of the same level as the counter electrode signal LCCOM is written to the pixel electrode of the first pixel. , The counter electrode signal LC is also applied to the pixel electrode of the last pixel.
A data signal at the same level as COM is written, and the pixel is turned off. Subsequent subfields Sf5 to Sf
Similarly, at f8, the last pixel is turned off.

After all, the period during which the last pixel is in the ON state is the period from time Tb1 'to Tb2'. In this period, the data transfer period (1 V) is longer than the ON period of the first pixel.
The period is delayed in time by a), but the time length is the same as the ON period of the first pixel. That is, the effective voltage value applied to the first pixel is equal to the effective voltage value applied to the last pixel. in this way,
According to the driving method according to the present embodiment, the same effective voltage value can be applied to each pixel to which the same gradation data is given. That is, as in the other driving method described above, the effective voltage value applied to each pixel does not become uneven due to the difference in the writing timing of the data signal to the pixel. , A uniform display can be realized.

By the way, in the above embodiment, the case where the image display is performed using all the pixels arranged on the substrate has been described as an example. Therefore, in the all-pixel off period, all the elements included in the electro-optical device are provided. The pixels are simultaneously turned off. On the other hand, in recent years, electro-optics capable of partial display (that is, display using only a part of the display area) using only some of all the pixels included in the electro-optical device has recently been enabled. An apparatus is also provided. When partial display is performed by applying the present invention to such an electro-optical device, only pixels to be driven (that is, pixels belonging to a region for performing partial display) out of all pixels included in the electro-optical device In such a case, a process is performed in which the pixel is turned off in the off period of all pixels in one field, and a voltage corresponding to gradation data is applied in each subfield. That is, “all pixels” or “all pixels” in the present specification means “all pixels to be driven to perform display among the pixels included in the electro-optical device”. Therefore, even if the pixel is included in the electro-optical device, a pixel that is not a display target is not included in “all pixels” and “all pixels” in this specification. Specifically, “all pixels” or “all pixels” in this specification means exactly all of the pixels when display is performed using all the pixels included in the electro-optical device. On the other hand, in a case where display is performed using only some of all pixels included in the electro-optical device, “all pixels” or “all pixels” in this specification refers to display. Therefore, it means all the pixels driven, and does not include pixels that are not displayed.

Also, for example, the thickness of the liquid crystal layer in the region where the pixel electrode is formed and the thickness of the liquid crystal layer in the region where the pixel electrode is not formed (for example, the region other than the display region) are equal to the thickness of the pixel electrode. In order to avoid the difference, a so-called dummy pixel (dummy electrode) may be formed in a region where display is not originally performed. Here, since such a dummy pixel is not driven for display, it goes without saying that it is not included in “all pixels” or “all pixels” in this specification.

In the present embodiment, the pixels are turned off in the last subfield Sf8 of one field irrespective of the gradation data, for the following reason. is there. In the following, a subfield in which a pixel is always turned off is referred to as an off subfield.

FIG. 9A shows a case where the off-subfield (subfield Sf8) in the above embodiment is not provided and
6 is a timing chart showing a state of each signal when a field is divided into an all-pixel off period and seven subfields, and pixels are driven on and off in units of each subfield. In FIGS. 9A and 9B, it is assumed that the gradation data is (111).

As shown in FIG. 9A, when the off subfield is not provided, the period during which the last pixel is in the ON state is shorter than the period during which the first pixel is in the ON state by the data transfer period. Would. On the other hand, when the off subfield is provided at the end of one field as in the above-described embodiment, as shown in FIG. 9B, the timing when the last pixel is turned on is when the first pixel is turned on. Although it is delayed by the data transfer period from the timing of the state, the time for turning on the pixels in the off subfield can be secured by the delay. Therefore, as is clear from FIG. 9B, the period in which the first pixel is in the ON state is delayed by the data transfer period from the period in which the last pixel is in the ON state, but the time length is equal. Become. That is, by providing the off-subfield, the effective voltage applied to each pixel can be made uniform even when the pixels are turned on over all the subfields except the off-subfield. It is. As is apparent from this, the off subfield needs to have a time length longer than the data transfer period.

In the present embodiment, the relationship between the effective voltage applied to the liquid crystal and the relative transmittance (or reflectance) is shown in FIG. 5 (a). Since it is assumed that the transmittance of the liquid crystal decreases when the voltage exceeds VTH2, it is necessary to set an off subfield in order to make the effective voltage applied to each pixel uniform regardless of the position of each pixel. . However, when the applied voltage effective value is equal to or higher than VTH2, when using a liquid crystal having such a characteristic that the transmittance of the liquid crystal maintains a constant value regardless of the applied voltage effective value, the subfields Sf1 to Sf1 are used. Sf7
Is a total time length of (V7 / V
H) Even if the time length becomes longer than ² , that is, even if the effective voltage value applied to the liquid crystal layer exceeds VTH2, the transmittance is maintained at 100%, so that it is applied to each pixel. The off-subfield for making the effective voltage uniform regardless of the position of each pixel may not be provided.

D: Modifications Although one embodiment of the present invention has been described above, the above embodiment is merely an example, and various modifications may be made to the above embodiment without departing from the spirit of the present invention. be able to. For example, the following modifications can be considered.

<Modification 1> In each of the above-described embodiments, the writing of each subfield must be completed within the same or shorter data transfer period (1 Va) as the shortest subfield (that is, 1Va). 1 Va ≦
Sfk). On the other hand, in each of the above-described embodiments, eight gradations are displayed. However, in order to further increase the gradation display frequency, the subfield period needs to be further shortened. It needs to be completed.

However, the driving circuit, particularly the X shift register 1410 in the data line driving circuit 140,
Actually, since it operates at the operating frequency near the upper limit, the gradation display frequency cannot be increased without any change. Therefore, a modified example in which this point is improved will be described.

FIG. 10 is a block diagram showing a configuration of the data line drive circuit 141 in the electro-optical device according to the present modification. In this figure, X shift register 1411
Is similar to X shift register 1410 shown in FIG. 3 in that latch pulse LP is transferred according to clock signal CLX, but differs from X shift register 1410 in that the number of stages is half. .
That is, assuming an integer p that satisfies n = 2p, the X shift register 1411 outputs the latch signals S1, S2, S
,..., Sp are sequentially output.

In this modification, the binary signal Ds
Are the binary signal Ds1 to the odd-numbered data line 114 and the binary signal Ds1 to the even-numbered data line 114, counted from the left.
s2 and supplied. Further, in the latch circuit 1421, a latch circuit for latching the binary signal Ds1 corresponding to the odd-numbered data line 114 and a latch circuit for latching the binary signal Ds2 corresponding to the subsequent even-numbered data line 114 are provided. Thus, the latch is performed simultaneously at the falling edge of the same latch signal.

The data line driving circuit 141 having such a configuration is used.
According to FIG. 10, the same latch signal S1, S2, S3,...
The individual binary signals Ds1 and Ds2 are latched. That is, data signals dj and dj + 1 are simultaneously supplied to two adjacent data lines, respectively. As a result, the required horizontal scanning period can be halved while maintaining the frequency of the clock signal CLX the same as in the above embodiment. Further, the number of stages of the unit circuits constituting the X shift register 1411 is reduced from “n” corresponding to the total number of the data lines 114 to “p” which is half thereof. Therefore, the configuration of the X shift register 1411 is changed to X
It can be simplified as compared with the shift register 1410 (see FIG. 3).

On the other hand, the fact that the number of unit circuits constituting the X shift register 1411 can be reduced to half means that if the required horizontal scanning period is the same, the clock signal CL is required.
This means that the frequency of X can be reduced by half. Therefore, if the horizontal scanning period is the same, the power consumed due to the operating frequency can be suppressed.

In this modification, the number of the latch circuits 1421 that simultaneously perform the latch operation in accordance with the latch signal is “2”, but it is needless to say that the number may be “3” or more. In this case, the binary signal is supplied in a manner divided into systems corresponding to the number, and the X shift register 1411
Can be reduced to the number obtained by dividing the number of data lines by the number of data lines.

<Modification 2> In the above embodiment, 1
The dot-sequential driving in which the data signal is dot-sequentially applied to the pixels of one row selected in the horizontal scanning period is employed. Line-sequential driving for writing data signals all at once may be employed. FIG. 11 is a block diagram showing a configuration of the data line driving circuit 142 in the present modification.

The data line driving circuit 142 sequentially latches n binary signals Ds corresponding to the number of data lines 114 in a certain horizontal scanning period, and then latches the n latched 2
In the next horizontal scanning period, the value signal Ds is applied to the data lines 114 corresponding to the data signals d1, d2, d3,.
.., Dn are supplied all at once. More specifically, as shown in FIG.
Are the X shift register 1410 and the first latch circuit 14
30 and a second latch circuit 1431. The X shift register 1410 is similar to that in the above embodiment.

The first latch circuit 1430 outputs the binary signal Ds
Are sequentially latched at the falling edges of the latch signals S1, S2, S3,..., Sn. The second latch circuit 1431 simultaneously latches each of the binary signals Ds latched by the first latch circuit 1430 at the fall of the latch pulse LP, and
4, data signals d1, d2, d3,.
It is designed to be supplied as.

Here, an outline of the operation of the data line drive circuit 142 during a certain horizontal scanning period will be described. First, one horizontal scanning period (1) in which a certain scanning signal Gi is output.
In H), the second latch circuit 1431 simultaneously sends the data signals d1, d2, d3,... To each of the n data lines 114 in accordance with the latch pulse LP supplied at the rising timing of the scanning signal Gi.・, Dn
Is output. These data signals are written to the pixel electrodes via the transistors of the respective pixels which are turned on by the supply of the scanning signal Gi. On the other hand, in parallel with this write operation, the first latch circuit 1430 outputs the latch signals S1, S2, S3,..., S output from the X shift register 1410 by the transfer of the latch pulse LP.
1 corresponding to the (i + 1) -th scanning line 112 according to n
Point-sequential latching of binary signals for pixels in a row is performed.

By performing such operations in parallel for each horizontal scanning period, line-sequential driving is realized.
In this modification, as in Modification 2, the number of latch circuits 1422 that simultaneously perform a latch operation in response to a latch signal may be set to “2” or more.

E: Entire Structure of Liquid Crystal Device Next, the structure of the electro-optical device according to the above-described embodiment and application will be described with reference to FIGS.
Here, FIG. 12 is a plan view illustrating the configuration of the electro-optical device 100, and FIG. 13 is a cross-sectional view taken along line AA ′ in FIG.

As shown in these figures, the electro-optical device 100 includes an element substrate 101 on which a pixel electrode 118 and the like are formed, and a counter substrate 1 on which a counter electrode 108 and the like are formed.
02 are bonded to each other with a certain gap therebetween by a sealant 104, and a liquid crystal 105 as an electro-optical material is sandwiched in this gap. Actually, the sealing material 104 has a cutout portion, and after the liquid crystal 105 is sealed through the cutout portion, it is sealed with a sealing material, but is omitted in these drawings.

Here, in each of the above embodiments, the element substrate 101 is a transparent substrate such as glass or quartz as described above. Therefore, if the pixel electrode 118 is formed of a reflective metal such as aluminum, it can be used as a reflective display device, while the pixel electrode 118 is formed of ITO.
(Indium Tin Oxide) can be used as a transmissive display device if formed of a transparent thin film.

As described above, in each of the above embodiments,
A TFT in which the element substrate 101 is a transparent insulating substrate such as glass or quartz, and a transistor 116 connected to the pixel electrode 118, a component of a driving circuit, and the like are formed on a semiconductor thin film deposited or attached on the substrate. , But
The present invention is not limited to such an electro-optical device. For example, the element substrate 101 may be a semiconductor substrate, and a MOS transistor (MOSFET) or the like may be formed on the semiconductor substrate. However, in this case, since the element substrate is opaque, the pixel electrode 118 is formed of a reflective metal such as aluminum, and is used as a reflective display device.

In the element substrate 101, a light-shielding film 106 is provided inside the sealant 104 and outside the display area 101a. In the region where the light-shielding film 106 is formed, the scanning line driving circuit 130 is formed in the region 130a, and the data line driving circuit 140 is formed in the region 140a. That is, the light shielding film 10
Numeral 6 prevents light from entering a drive circuit formed in this region. This light-shielding film 106 has a counter electrode 10
8 together with the counter electrode signal LCCOM. For this reason, in the region where the light-shielding film 106 is formed, the voltage applied to the liquid crystal layer becomes substantially zero, and the display state is the same as the state where no voltage is applied to the pixel electrode 118.

In the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line driving circuit 140 is formed and separated from the sealing material 104 by a plurality of connection terminals. It is configured to input signals and power.

On the other hand, the counter electrode 108 of the counter substrate 102
Is electrically connected to the light-shielding film 106 and the connection terminals of the element substrate 101 by a conductive material (not shown) provided in at least one of the four corners of the substrate bonding portion. That is, the counter electrode signal L
CCOM is configured to be applied to the light-shielding film 106 via a connection terminal provided on the element substrate 101 and further to the counter electrode 108 via a conductive material.

In addition, depending on the use of the electro-optical device 100, for example, in the case of a direct-view type, first, a color filter arranged in a stripe shape, a mosaic shape, a triangle shape, or the like is provided on the counter substrate 102, for example. Second, a light-shielding film (black matrix) made of, for example, a metal material or a resin is provided. In the case of color light modulation, for example, when used as a light valve of a projector described later, no color filter is formed. In the case of a direct-view type, a front light for irradiating the electro-optical device 100 with light from the counter substrate 102 side is provided as necessary. In addition, the element substrate 101 and the counter substrate 1
On the electrode forming surface 02, an alignment film (not shown) rubbed in a predetermined direction is provided to define the alignment direction of the liquid crystal molecules when no voltage is applied. Is provided with a polarizer (not shown) according to the orientation direction. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-described alignment film and polarizer are not required, and the light use efficiency is increased. This is advantageous in terms of low power consumption and the like.

As the liquid crystal, in addition to the above-mentioned TN type, STN (Super
Twisted Nematic) and BTN (Bi-stable Twisted N)
Bistable type having memory properties such as ematic) type and ferroelectric type, polymer dispersed type, and dye (guest) having anisotropy in visible light absorption in the major axis direction and minor axis direction of molecules (guest) Is dissolved in a liquid crystal (host) having a fixed molecular arrangement, and a guest-host type liquid crystal in which dye molecules are arranged in parallel with the liquid crystal molecules can be used.

The liquid crystal molecules are aligned vertically with respect to both substrates when no voltage is applied, while the liquid crystal molecules are aligned horizontally with respect to both substrates when voltage is applied. It may be configured,
When a voltage is not applied, the liquid crystal molecules are arranged in a horizontal direction with respect to both substrates, while when a voltage is applied, the liquid crystal molecules are arranged in a direction perpendicular to both substrates. good. Further, instead of arranging the opposing electrode 108 on the opposing substrate 102, the pixel electrode and the opposing electrode may be arranged on the element substrate 101 in a comb-tooth shape at intervals. In this configuration, the liquid crystal molecules are horizontally aligned, and the orientation direction of the liquid crystal molecules changes according to the horizontal electric field between the electrodes.
As described above, as long as the liquid crystal and the alignment method are compatible with the driving method of the present invention, various types can be used.

In addition, as an electro-optical device, in addition to a liquid crystal device, electroluminescence (EL), a digital micromirror device (DMD), plasma light emission or fluorescence by electron emission are used, and the electro-optical effect is obtained. The present invention is applicable to various electro-optical devices such as a device for performing display. In this case, the electro-optical material is E
L, mirror device, gas, phosphor, etc. In addition,
When EL is used as the electro-optic material, the element substrate 101
In this case, the EL is interposed between the pixel electrode 118 and the counter electrode 108 of the transparent conductive film.
2 becomes unnecessary. As described above, the present invention is applied to all electro-optical devices having a configuration similar to the above-described configuration, and particularly to all electro-optical devices that perform grayscale display using pixels that perform on / off binary display. Applicable.

F: Electronic Apparatus Next, some examples in which the above-described liquid crystal device is used in specific electronic apparatuses will be described.

<Part 1: Projector> First, a projector using the electro-optical device according to the embodiment as a light valve will be described. FIG. 14 is a plan view showing the configuration of this projector. As shown in this figure,
Inside the projector 1100, a polarized light illumination device 1110 is provided.
Are arranged along the system optical axis PL. In the polarized light illuminating device 1110, the light emitted from the lamp 1112 becomes a substantially parallel light beam due to reflection by the reflector 1114, and enters the first integrator lens 1120. As a result, the light emitted from the lamp 1112 is split into a plurality of intermediate light beams. This split intermediate beam is
The polarization conversion element 1130 having the second integrator lens on the light incident side is converted into one kind of polarized light beam (s-polarized light beam) whose polarization direction is almost uniform, and is emitted from the polarized light illuminating device 1110.

Now, the s-polarized light beam emitted from the polarized light illuminator 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarizing beam splitter 1140. Of this reflected light beam, the light beam of blue light (B) is reflected by the blue light reflecting layer of the dichroic mirror 1151, and is modulated by the reflection-type electro-optical device 100B. Further, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of red light (R) is
The light is reflected by the red light reflection layer 52 and is modulated by the reflection type liquid electro-optical device 100R. On the other hand, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of green light (G) is
The light passes through the 52 red light reflecting layer and is modulated by the reflection-type electro-optical device 100G.

As described above, the electro-optical device 100R,
The red, green, and blue lights, each of which has been color-modulated by 100G and 100B, are output to a dichroic mirror 115.
2, 1151, and are sequentially synthesized by the polarizing beam splitter 1140, and then projected on the screen 1170 by the projection optical system 1160. In addition, the dichroic mirrors 1151 and 1152 attach the R, G, and
Since a light beam corresponding to each primary color of B enters, no color filter is required.

Although the description has been given of a projector using a reflection-type electro-optical device as an example, it is needless to say that a projector using a transmission-type electro-optical device may be used.

<Part 2: Mobile Computer> Next, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 15 is a perspective view showing the configuration of this personal computer.
In the figure, a computer 1200 includes a keyboard 12
02 and a display unit 1206
It is composed of This display unit 1206 is
It is configured by adding a front light to the front surface of the electro-optical device 100 described above.

In this configuration, the electro-optical device 100
Is used as a reflection direct-view type, so that the pixel electrode 1
At 18, the reflected light is scattered in various directions,
A configuration in which unevenness is formed is desirable.

<Part 3: Mobile Phone> An example in which the above-described electro-optical device is applied to a mobile phone will be described. FIG. 16 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302, an earpiece 1304, and a mouthpiece 1306.
In addition, an electro-optical device 100 is provided. The electro-optical device 100 is also provided with a front light on its front surface as needed. Also in this configuration, since the electro-optical device 100 is used as a reflection direct-view type, a configuration in which the pixel electrode 118 has unevenness is desirable.

Note that the electronic equipment is shown in FIGS.
In addition to those described with reference to the above, a liquid crystal television, a viewfinder type, a video tape recorder of a monitor direct-view type, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a PO
An S terminal, a device equipped with a touch panel, and the like are included. Needless to say, the electro-optical device according to the embodiment or the applied form can be applied to these various electronic devices.

[0145]

As described above, according to the present invention,
The signal applied to the data line is binarized, and a high-quality gradation display can be performed. Further, according to the present invention, since all the pixel off periods for turning off the pixels all at once are provided for each field, uniform display can be realized over all the pixels.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the invention.

FIGS. 2A, 2B, and 2C are circuit diagrams each illustrating one mode of a pixel of the electro-optical device. FIGS.

FIG. 3 is a block diagram showing a configuration of a data line driving circuit in the same electro-optical device.

FIG. 4 is a truth table showing functions of a data conversion circuit in the same electro-optical device.

FIG. 5A is a diagram illustrating voltage-transmittance characteristics in the same electro-optical device, and FIG. 5B is a diagram illustrating an all-pixel off period and each subfield in one field.

FIG. 6 is a timing chart showing the operation of the electro-optical device.

FIG. 7 is a timing chart showing a voltage applied to a counter electrode and a voltage applied to a pixel electrode in the electro-optical device.

FIG. 8 is a diagram for explaining an effect in the electro-optical device.

FIG. 9 is a diagram illustrating an off-subfield in the electro-optical device.

FIG. 10 is a block diagram illustrating a configuration of a data line driving circuit in an electro-optical device according to a modified example of the invention.

FIG. 11 is a block diagram illustrating a configuration of a data line driving circuit in an electro-optical device according to a modification example of the invention.

FIG. 12 is a plan view showing a structure of the electro-optical device.

FIG. 13 is a sectional view showing a structure of the electro-optical device.

FIG. 14 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 15 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 16 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device is applied.

[Explanation of symbols]

 Reference Signs List 100 electro-optical device 101 element substrate 101a display area 102 counter substrate 105 liquid crystal 108 counter electrode 110 pixel 112 scanning line 114 -Data line 116-Transistor 118-Pixel electrode 119-Storage capacitance 120-OR gate 121-Switch 130-Scan line drive circuit 140, 141, 142-Data line drive Circuits 1410, 1411: X shift register 1420, 1421: Latch circuit 200: Timing signal generation circuit 300: Data conversion circuit

Continued on the front page F term (reference) 2H093 NA16 NA51 NC13 NC22 NC23 NC26 NC34 NC67 ND06 NE10 NG02 5C006 AA14 AA15 AC21 AF44 BB16 BC06 BC12 BF04 FA22 5C080 AA10 BB05 DD05 EE29 FF11 FF12 JJ02 JJ03 JJ04 JJ05 JJ05 JJ05 JJ05 JJ05

Claims (15)

[Claims] 1. A method for driving an electro-optical device for driving a pixel comprising a memory and a pixel electrode disposed corresponding to each intersection of a plurality of scanning lines and a plurality of data lines in accordance with gradation data. And dividing each field into an all-pixels off period and a plurality of subfields; in the all-pixels off period, all the pixels are turned off at the same time; The electro-optical device according to claim 1, wherein each pixel is turned on or off in units of subfields such that a ratio of the pixel to an off state is a ratio according to the gradation data. Drive method. 2. A driving method for an electro-optical device, comprising: driving a pixel, which is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and includes a memory and a pixel electrode in accordance with gradation data. Dividing each field into an all-pixel off-period and a plurality of sub-fields; in the all-pixel off-period, all the pixels are simultaneously turned off; and in each of the plurality of sub-fields, the plurality of scans A method for driving an electro-optical device, comprising sequentially selecting lines and turning on or off pixels corresponding to the selected scanning line. 3. A pixel is turned off in a last subfield of a plurality of subfields included in each of the fields.
3. The method for driving an electro-optical device according to claim 1. 4. A driving circuit for an electro-optical device which drives pixels formed of a memory and a pixel electrode in accordance with each intersection of a plurality of scanning lines and a plurality of data lines in accordance with gradation data. An all-pixels off circuit that divides each field into an all-pixels off period and a plurality of subfields, and applies a voltage to turn off the pixels to all the pixels simultaneously in the all-pixels off period; A data conversion circuit for generating a binary signal for instructing application of a voltage for turning on each pixel or a voltage for turning off each pixel in each of the plurality of subfields, A data conversion circuit for generating the corresponding binary signal from gradation data corresponding to each pixel; and a scanning signal for enabling a signal supply from a data line to a pixel for each of the subfields. A scanning line driving circuit that sequentially supplies each of the scanning lines; and a data signal for turning a pixel on or off according to a binary signal from the data conversion circuit while the scanning signal is supplied. A driving circuit for an electro-optical device, comprising: a data line driving circuit for supplying a data line. 5. The all-pixels-off circuit, comprising: an all-pixels selection circuit for simultaneously supplying an all-pixels selection signal for enabling a signal supply from a data line to a pixel to all the pixels during the all-pixels off period. And a signal supply circuit for simultaneously supplying a signal for turning off a pixel to all data lines while the all-pixel selection signal is supplied. 3. A driving circuit for an electro-optical device according to claim 1. 6. The data conversion circuit generates a binary signal instructing application of a voltage for turning off a pixel in a last subfield of a plurality of subfields included in each of the fields. The driving circuit for an electro-optical device according to claim 4, wherein: 7. A shift register for sequentially shifting and outputting a latch pulse signal supplied at the beginning of a horizontal scanning period according to a clock signal, wherein the data line driving circuit shifts the binary signal by the shift register. 7. The driving circuit for an electro-optical device according to claim 4, further comprising: a latch circuit for simultaneously latching the binary signals distributed to a plurality of systems in accordance with the obtained signal. 8. A data line driving circuit, comprising: a shift register for sequentially shifting and outputting a latch pulse signal supplied at the beginning of a horizontal scanning period in accordance with a clock signal; and shifting the binary signal by the shift register. A first latch circuit for sequentially latching the binary signal latched by the first latch circuit, the binary signal latched by the first latch circuit being latched based on the latch pulse signal, and a corresponding data line as the data signal. 7. The driving circuit for an electro-optical device according to claim 4, further comprising: a second latch circuit that outputs signals simultaneously. 9. The electro-optical device according to claim 8, wherein the first latch circuit simultaneously latches the binary signals distributed to a plurality of systems by a signal shifted by the shift register. The drive circuit of the device. 10. A pixel comprising a memory and a pixel electrode provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines; And an all-pixels off circuit for simultaneously applying a voltage to turn off the pixels to all the pixels in the all-pixels off period; and turning on each pixel in each of the plurality of subfields. A binary signal for instructing the application of a voltage to be turned on or a voltage to be turned off, wherein the binary signal corresponding to each pixel is converted from gradation data corresponding to each pixel in each subfield. A data conversion circuit for generating, a scanning line driving circuit for sequentially supplying a scanning signal enabling supply of a signal from a data line to a pixel to each of the scanning lines for each of the subfields, A data line driving circuit for supplying a data signal for turning on or off a pixel to each data line according to a binary signal from the data conversion circuit while the signal is supplied. Electro-optical device. 11. The memory according to claim 1, wherein the memory writes a switching element that is turned on by the scanning signal and data supplied to a corresponding data line when the switching element is turned on, and the switching element is turned off. 11. The electro-optical device according to claim 10, further comprising a capacitor for holding the written data. 12. The switching device according to claim 11, wherein a P-channel type transistor and an N-channel type transistor are complementarily combined.
An electro-optical device according to claim 1. 13. The memory, wherein the switching element is turned on by the scanning signal, and data supplied to a corresponding data line when the switching element is turned on is written, and the switching element is turned off. 11. The electro-optical device according to claim 10, further comprising two inverters that hold the written data, wherein the output of one inverter is the input of the other inverter. 14. The pixel, the all-pixels off circuit, the scanning line driving circuit, and the data line driving circuit are formed on a semiconductor substrate, and the pixel electrode has reflectivity. 14. The electro-optical device according to any one of items 13 to 13. 15. An electronic apparatus comprising the electro-optical device according to claim 10 as a display device.