JP3997727B2 - Electro-optic panel and electronic equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical panel and an electronic apparatus.
[0002]
[Prior art]
An electro-optical device, for example, a liquid crystal display device using liquid crystal as an electro-optical material, is widely used as a display device in place of a cathode ray tube (CRT) in a display unit of various information processing devices, a liquid crystal television, and the like.
[0003]
Here, the conventional electro-optical device is configured as follows, for example. In other words, a conventional electro-optical device includes a pixel electrode arranged in a matrix, an element substrate provided with a switching element such as a TFT (Thin Film Transistor) connected to the pixel electrode, and a pixel electrode. It is composed of a counter substrate on which counter electrodes facing each other are formed, and a liquid crystal as an electro-optic material filled between the two substrates. In such a configuration, when a scanning signal is applied to the TFT through the scanning line, the TFT becomes conductive. In this conductive state, when an image signal having a voltage corresponding to the gradation is applied to the pixel electrode through the data line, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Accumulated. After the charge accumulation, even if the TFT is turned off, the charge accumulation in the liquid crystal layer is maintained by the pixel capacitance of the liquid crystal layer itself. In this way, when each TFT is driven and the amount of charge to be stored is controlled according to the gradation, the alignment state of the liquid crystal changes for each pixel, so that the density changes for each pixel. For this reason, gradation display is possible.
[0004]
At this time, since the charge may be accumulated in the liquid crystal layer of each pixel during a part of the period, first, each scanning line is sequentially selected by the scanning line driving circuit, and secondly, the scanning line selection period. In this configuration, the data lines are sequentially selected by the data line driving circuit, and thirdly, the scanning lines and the data lines are shared by a plurality of pixels by sampling an image signal having a voltage corresponding to the gradation on the selected data lines. Time-division multiplexed drive is possible.
[0005]
[Problems to be solved by the invention]
By the way, in the period in which the TFT is turned on, in order to sufficiently write the data line voltage to the pixel capacitor, it is necessary to apply a potential higher than the potential of the data line to the gate of the TFT. On the other hand, in a period in which the TFT is in an off state, it is necessary to apply a potential lower than the potential that the data line can take in order to reduce the leakage of accumulated charges.
[0006]
Since the on / off control of the TFT is performed by the scanning signal, it is necessary to prepare a voltage source different from the data line driving circuit in order to drive the scanning line driving circuit, and there is a problem that the configuration becomes complicated. It was. In addition, since the scanning line driving circuit must be driven at a high voltage, there is a problem that power consumption is increased.
[0007]
The present invention has been made in view of the above-described circumstances, and an object thereof is an electro-optical panel having a simple configuration and low power consumption, and further an electronic apparatus using the electro-optical panel. Is to provide.
[0008]
[Means for Solving the Problems]
The electro-optical panel of the present invention includes a plurality of data lines and a plurality of scanning lines, and a plurality of pixels are arranged corresponding to intersections of the plurality of scanning lines and the plurality of data lines. The pixel includes a pixel capacitor formed between the pixel electrode and the counter electrode;
A writing unit provided between one data line and the pixel electrode, and writing a data signal supplied to the data line to the pixel capacitor based on a scanning signal supplied to the one scanning line; Resetting means for resetting the voltage of the pixel electrode to a predetermined reset voltage.
[0009]
According to this invention, each pixel can set the voltage of the pixel electrode to the reset voltage at a desired timing by the reset means. Here, if the electro-optical material used for the electro-optical panel is a liquid crystal, the application of a DC voltage to the liquid crystal causes burn-in and the like, which degrades its characteristics. Therefore, it is necessary to perform so-called AC driving. is there. For this reason, it is necessary to reverse the polarity of the voltage of the pixel electrode at a predetermined cycle with the voltage of the counter electrode as the center. If the voltage of the pixel electrode is reset immediately before writing by the writing means by making the reset voltage coincide with the voltage of the counter electrode, the necessary voltage can be sufficiently written to the pixel capacitor even if the writing period is short. .
[0010]
Here, the electro-optical panel includes scanning means for supplying the scanning signal to some or all of the plurality of scanning lines based on an enable signal that indicates a row in which writing of the data signal is permitted. There may be. According to the present invention, data signal writing can be controlled in units of rows.
[0011]
The electro-optical panel includes a plurality of capacitor lines, and the pixel includes a storage capacitor in which the pixel electrode and one terminal are connected, and the capacitor line and the other terminal are connected. A first switching element provided between the one data line and the pixel electrode and controlled to be turned on / off based on a scanning signal supplied to the one scanning line, and the reset means A second switching element provided between the pixel electrode and the capacitor line may be provided. In this case, the reset voltage is supplied to the capacitor line, and the reset voltage is supplied to the pixel electrode by the second switching element.
[0012]
Here, it is preferable that on / off of the second switching element is controlled based on a scanning signal supplied to a scanning line adjacent to the one scanning line. According to the present invention, since it is not necessary to provide a special wiring for supplying the reset signal, the configuration can be simplified.
[0013]
The electro-optical panel may include a plurality of reset lines, and the second switching element may be controlled to be turned on / off based on a reset signal supplied to the reset line.
[0014]
The electro-optical panel includes a plurality of capacitance lines, and two scanning lines are used as one set to supply a scanning signal and an inverted scanning signal to the pixels in each row. And a storage capacitor to which the capacitor line and the other terminal are connected, and the writing means is provided between the one data line and the pixel electrode, and is a set of scans. A first N-channel transistor that is controlled to be turned on / off based on a signal; and a first P-channel transistor that is controlled to be turned on / off based on the set of inverted scanning signals. A second N-channel transistor and a second P-channel transistor provided in parallel between the electrode and the capacitor line may be provided. According to the present invention, the first N-channel transistor and the first P-channel transistor can be operated in a complementary manner, and the second N-channel transistor and the second P-channel transistor can be operated in a complementary manner. Can be reduced in amplitude. As a result, the power consumption of the electro-optical panel can be reduced.
[0015]
Here, the second N-channel transistor is controlled to be turned on / off based on a scanning signal supplied to a selected row immediately before selecting a row including the pixel, and the second P-channel transistor is controlled by the scanning signal. On / off may be controlled based on an inverted scanning signal corresponding to. According to the present invention, since it is not necessary to provide special wiring for controlling the second N-channel transistor and the second P-channel transistor, the configuration can be simplified.
[0016]
The electro-optical panel includes a plurality of reset line pairs that supply reset signals and inverted reset signals to the pixels in each row, and the second N-channel transistor is controlled to be turned on / off based on the reset signal. The 2P channel transistor may be turned on / off based on an inverted reset signal corresponding to the reset signal. According to this configuration, the reset signal and the inverted reset signal can be supplied independently of the scanning signal and the inverted scanning signal.
[0017]
The reset voltage preferably matches the voltage of the counter electrode.
[0018]
Next, a scanning line driving circuit of the present invention includes a plurality of data lines, a plurality of scanning lines, and a plurality of reset lines, and a plurality of scanning lines corresponding to the intersections of the plurality of scanning lines and the plurality of data lines. Used for the electro-optical panel in which the pixels are arranged, an address signal designating a row to be selected and an enable signal designating a row permitting writing of the data signal supplied to the data line are supplied from the outside. A plurality of unit circuits corresponding to each row, wherein the unit circuit decodes the address signal and outputs a decode signal, and a period in which both the enable signal and the decode signal are active. A reset signal generation circuit for generating an active reset signal, and a period after the reset signal is switched from active to inactive Only those and a scanning signal generating circuit for generating a scanning signal which becomes active.
[0019]
According to the present invention, it is not necessary to write data signals for all pixels, data signals can be written only for a certain row, and the reset signal is activated before the scanning signal is activated. It becomes possible to do. Thereby, even if the active period of the scanning signal is short, the data signal can be reliably written to the pixel.
[0020]
Here, the reset signal generation circuit latches the enable signal at a timing when the decode signal becomes active, generates a first control signal, and outputs the first control signal to the decode signal and the first control signal. A first generation circuit that generates the reset signal based on the first signal, and the scanning signal generation circuit latches the first control signal at a timing when the decode signal switches from active to inactive, and the result is obtained for a certain period of time. It is desirable to include a second flip-flop circuit that resets after elapses and a second generation circuit that generates the scanning signal based on an output signal of the second flip-flop circuit.
[0021]
The reset signal generation circuit generates an inverted reset signal obtained by inverting the reset signal in addition to the reset signal, and the scanning signal generation circuit is an inverted scanning signal obtained by inverting the scanning signal in addition to the scanning signal. May be generated.
[0022]
Next, in the electro-optical panel driving method of the present invention, the plurality of data lines, the plurality of scanning lines, and the intersections of the plurality of scanning lines and the plurality of data lines are arranged. An electro-optical device having a plurality of pixels, each pixel including a pixel electrode, a writing unit that writes a voltage to the pixel electrode, and a reset unit that resets the voltage of the pixel electrode to a predetermined reset voltage A reset step of resetting the voltage of the pixel electrode to the reset voltage using the reset unit; and controlling the writing unit by supplying a scan signal to the scan line to control the data A writing step of writing a data signal supplied via a line to the pixel electrode;
It is characterized by providing. According to the present invention, the data signal is written by the value setting stage and the writing stage.
[0023]
Here, the writing step is performed only for pixels belonging to some rows, while for pixels belonging to other rows, the voltage of the pixel electrode is constantly set to the reset voltage using the reset unit. It may be reset.
[0024]
Next, an electronic apparatus of the present invention includes the above-described electro-optical panel, and corresponds to, for example, a video projector, a notebook computer, a mobile phone, a car navigation device, and the like.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
<1. First Embodiment>
<1-1: Overall configuration>
FIG. 1 is a block diagram showing an electrical configuration of the electro-optical device according to the first embodiment of the present invention. The electro-optical device includes a liquid crystal panel 100, a timing signal generation circuit 200, a data conversion circuit 300, and a power supply circuit 400.
[0026]
First, the liquid crystal panel 100 includes a display area A on which an image is formed, a scanning line driving circuit 130A, and a data line driving circuit 140. The liquid crystal panel 100 has a configuration in which liquid crystal as an electro-optical material is sandwiched between an element substrate and a counter substrate. A counter electrode is formed on the counter substrate, and a white voltage Vwt is fed as a common voltage thereto. The liquid crystal panel 100 operates in a normally white mode, and is configured so that the transmittance is maximized in a state where no voltage is applied to the liquid crystal.
[0027]
In the display area A on the element substrate, a plurality of scanning lines 112N are formed extending in the X (row) direction in the figure, and a plurality of data lines 114 are arranged along the Y (column) direction. It is formed to extend. In addition, a plurality of capacitor lines SL are formed in the display area A so as to extend in the X (row) direction. The respective capacitor lines SL are connected to each other, and a white voltage Vwt is supplied thereto.
[0028]
The pixel 110 is arranged corresponding to each intersection of the scanning line 112N and the data line 114. In the present embodiment, the total number of scanning lines 112N is m + 1, the total number of data lines 114 is n, and the total number of capacitance lines SL is m (m and n are each an integer of 2 or more), m rows × An n-column matrix display device will be described.
[0029]
Next, the timing signal generation circuit 200 generates various timing signals, clock signals, and the like according to a vertical scanning signal Vs, a horizontal scanning signal Hs, and a dot clock signal DCLK supplied from a host device (not shown).
[0030]
Next, the power supply circuit 400 generates various voltages and supplies power to the liquid crystal panel 100 and the timing signal generation circuit 200. The scanning line driving circuit 130A of the present embodiment operates with the high potential side voltage Vgdd and the low potential side voltage Vgss, while the data line driving circuit 140 has the positive side black voltage Vbk (+), the white voltage Vwt, and the negative side. Operates with side black voltage Vbk (-) etc. Here, the positive side black voltage Vbk (+) and the negative side black voltage Vbk (−) are obtained by reversing the polarity with the white voltage Vwt as the center voltage. The power supply circuit 400 generates these voltages and supplies power to the liquid crystal panel 100.
[0031]
<1-2: Pixel configuration>
Next, a specific configuration of the pixel 110 will be described. FIG. 2 is a circuit diagram showing the detailed configuration of the pixel 110, and the configuration of each of the pixels 110-1 to 110-m corresponding to the jth column counted from the leftmost column of the display area A shown in FIG. Is shown.
[0032]
Here, the pixel 110-1 includes N-channel TFTs 116N and 117N, a pixel electrode 118, and a storage capacitor CS. The pixel electrode 118 constitutes a pixel capacitor CL together with a common electrode and liquid crystal formed on the counter substrate. The storage capacitor CS shown in the figure is described as an element independent of the pixel electrode 118 and the capacitor line SL, but the actual structure is as follows. First, a capacitor line SL having a certain width is formed on the element substrate in the X direction, and a pixel electrode 118 is formed thereon via an insulating layer. In this case, the storage capacitor CS is formed in a region where the pixel electrode 118 and the capacitor line SL overlap, and is configured by the overlapping pixel electrode 118, the capacitor line SL, and the insulating film. Of course, the storage capacitor CS may be formed by sandwiching an insulating film between some of the electrodes connected to the pixel electrode 118 and the capacitor line SL.
[0033]
Next, the source of the N-channel TFT 116N is connected to the data line 114, its drain is connected to the pixel electrode 118, and its gate is connected to the scanning line 112N-1. Therefore, the N-channel TFT 116N is controlled to be turned on / off by the scanning signal GN1. As a result, when the scanning signal GN1 becomes active, the N-channel TFT 116N is turned on, and the voltage of the data line 114 is written to the pixel capacitor CL and the storage capacitor CS. In the following description, the voltage of the pixel electrode 118 is represented by PX (i, j) in the pixel 110 in i row and j column.
[0034]
By the way, since the liquid crystal has a property that its characteristics deteriorate when a DC voltage is applied, the liquid crystal is usually driven by alternating current driving. For this reason, the polarity of the voltage applied to the pixel electrode 118 needs to be reversed with a common voltage as a reference at a certain period. On the other hand, since the period during which the voltage is written to the pixel capacitor CL and the storage capacitor CS is limited to the period during which the scanning signal GN is active (scan line selection period), the writing must be completed during the period.
[0035]
However, when the polarity inversion described above is performed, the voltage change width is large, so that it becomes difficult to write a necessary voltage to the pixel capacitor CL and the storage capacitor CS when the scanning line selection period is shortened.
[0036]
Therefore, in the present embodiment, the voltage of the pixel capacitor CL and the storage capacitor CS is reset to the white voltage Vwt immediately before the scanning line selection period. The N-channel TFT 117N is an element provided for this purpose.
[0037]
The N-channel TFT 117N has a source connected to the pixel electrode 118, a drain connected to the capacitor line SL, and a gate connected to the scanning line 112N-0. The N-channel TFT 117N is controlled to be turned on / off by the scanning signal GN0. The scanning signals GN0 to GNm become active in the order of GN0 → GN1 → GN2... → GNm. Therefore, before the scanning line 112N-1 is selected, the N-channel TFT 117N is turned on, and the pixel electrode voltage PX (1, j) is reset to the white voltage Vwt. As a result, even when the scanning line selection period is short, the voltage of the data line 114 can be sufficiently written into the pixel capacitor CL and the storage capacitor CS.
[0038]
<1-3: Data conversion circuit>
Next, the data conversion circuit 300 will be described. The data conversion circuit 300 converts the 3-bit image data D, generates a 1-bit binary signal Ds, and supplies it to the data line driving circuit 140.
[0039]
<1-3-1: Subfield>
First, before describing the data conversion circuit 300 in detail, the concept of a subfield which is a premise of the electro-optical device according to the present embodiment will be described. In general, in a liquid crystal device using liquid crystal as an electro-optic material, the effective voltage applied to the liquid crystal layer (when the voltage is constant and the on-voltage pulse width is changed) and the relative transmittance (or reflectance) This relationship is as shown in FIG. 3 in the case of a normally white mode in which white display is performed when no voltage is applied. That is, as the effective voltage value applied to the liquid crystal layer increases, the transmittance decreases nonlinearly and becomes saturated. The relative transmittance here is normalized by setting the minimum value and the maximum value of the transmitted light amount to 0% and 100%, respectively.
[0040]
Here, it is assumed that the electro-optical device according to the present embodiment performs eight gradation display, and the image data D indicated by 3 bits indicates the transmittance shown in FIG. At this time, the effective voltage values applied to the liquid crystal layer at the intermediate transmittance excluding the transmittance of 0% and the transmittance of 100% are V1, V2,..., V6, respectively.
[0041]
In the electro-optical device according to the present embodiment, first, a configuration is adopted in which the voltage instantaneously applied to the liquid crystal layer is, for example, one of a voltage VL corresponding to the L level and a voltage VH corresponding to the H level. To do. On the other hand, in this configuration, if the voltage VL is applied to the liquid crystal layer over the entire period of one frame (1f), the display is turned off during the entire period, so that the transmittance is 100%.
[0042]
Further, by controlling the ratio of the period in which the voltage VL is applied to the liquid crystal layer and the period in which the voltage VH is applied in one frame period, the effective voltage applied to the liquid crystal layer is V1, V2,. If so, gradation display corresponding to the voltage becomes possible. Even if the effective voltage applied to the liquid crystal layer exceeds V7, the transmittance is 0% because of saturation. Therefore, in the electro-optical device according to the present embodiment, secondly, one frame period is divided into a plurality of periods, and the voltage VL is applied to the liquid crystal layer for each period or the voltage VH is set based on the image data. Whether to apply the voltage is determined, and thereby the effective voltage Vd is applied to the liquid crystal layer. In the following description, a plurality of divided periods will be referred to as subfields.
[0043]
In the present embodiment, one frame is divided into a number of periods corresponding to the number of bits of the image data D. FIG. 4 shows how one frame is divided when the image data D is 3 bits. In this example, one frame is composed of subfields Sf1, Sf2, and Sf3. The subfield Sf1 corresponds to the LSB of the image data D, the subfield Sf2 corresponds to the middle bit of the image data D, and the subfield Sf3 corresponds to the MSB of the image data D.
[0044]
When the image data D of a certain pixel is (001) (that is, when gradation display is performed with the transmittance of the pixel being 85.7%), in the subfield Sf1 in one frame (1f) period, While the voltage VH is applied to the liquid crystal layer of the pixel, the voltage VL is applied in another period. In this case, the period of the subfield Sf1 is set as a period during which a voltage value such as V1 can be applied as an effective voltage.
[0045]
In addition, when the image data D is (010) (that is, when gradation display is performed with the transmittance of the pixel being 71.4%), in the subfield Sf2 during the one frame (1f) period, While the voltage VH is applied to the liquid crystal layer of the pixel, the voltage VL is applied in other periods. Here, the period of the subfield Sf2 is set as a period during which a voltage value such as V2 can be applied as an effective voltage.
[0046]
Similarly, when the image data D is (100) (that is, when gradation display is performed with the transmittance of the pixel being 42.9%), in the subfield Sf3 in one frame (1f) period, While the voltage VH is applied to the liquid crystal layer of the pixel, the voltage VL is applied in another period.
[0047]
Thus, since one frame is divided into three subfields Sf1, Sf2, and Sf3, whether to apply the voltage VH or the voltage VL to the liquid crystal layer in each subfield is determined according to the image data D. Although the voltage applied to the liquid crystal layer is binary of VL and VH, gradation display corresponding to each transmittance is possible.
[0048]
<1-3-2: Details of data conversion circuit>
In order to write the H level or the L level according to the gradation for each of the subfields Sf1 to Sf3, it is necessary to convert the image data D corresponding to the pixel in some form. The data conversion circuit 300 shown in FIG. 1 is provided for this purpose, and has a frame memory as a main part.
[0049]
The image data D is temporarily stored in the frame memory, read according to a predetermined rule, and converted into a binary signal Ds. Here, it is assumed that the image data D corresponding to the pixel 110 in the i row and the j column is represented by D (i, j), and the LSB, the middle bit, and the MSB of D (i, j) are represented by D0 (i, j). , D1 (i, j) and D2 (i, j).
[0050]
The image data D stored in the frame memory is read bit by bit in the following order. First, in the subfield Sf1, D0 (1,1), D0 (1,2),..., D0 (1, n), D0 (2,1), D0 (2,2),. , n),..., D0 (m, n), and so on, the LSB of the image data D is read out. Next, in the subfield Sf2, the middle bit D1 (i, j) of the image data D and further in the subfield Sf3, D2 (i, j) which is the MSB of the image data D are the same as in the subfield Sf1. Is read out.
[0051]
Since the binary signal Ds needs to be output in synchronization with the operations in the scanning line driving circuit 130A and the data line driving circuit 140, the data conversion circuit 300 receives the start pulses DY and DX and the horizontal scanning. A clock signal CLY to be synchronized and a clock signal CLX corresponding to a dot clock signal are supplied.
[0052]
<1-4: Data Line Drive Circuit>
Next, the data line driving circuit 140 will be described. FIG. 5 is a block diagram showing a configuration of the data line driving circuit 140. As shown in this figure, the data line driving circuit 140 includes a shift register 141, signal supply lines La and Lb, and selectors SLT1 to SLTn.
[0053]
First, the shift register 141 sequentially transfers the start pulse DX according to the clock signal CLX to generate shift signals S1 to Sn that are active at the H level.
[0054]
Next, the binary signal Ds is supplied to the signal supply line La, while the frame signal FR is supplied to the signal supply line Lb. The frame signal FR becomes H level in odd frames and becomes L level in even frames.
[0055]
Next, the selectors SLT1 to SLTn select the positive-side black voltage Vbk (+), the white voltage Vwt, and the negative-side black voltage Vbk (−) based on the binary signal Ds, the frame signal FR, and the shift signals S1 to Sn. One voltage is selected from these, and supplied to the data line 114 as data signals d1 to dn.
[0056]
When the selector SLT1 is picked up, the selection operation is performed according to the truth table shown in FIG. The other selectors SLT2 to SLTn perform the same selection operation. As shown in this truth table, when the shift signal S1 is inactive (L level), the data signal d1 becomes the white voltage Vwt, while when the shift signal S1 is active (H level), the selector SLT1 is binary. A selection operation is performed based on the signal Ds and the frame signal FR.
[0057]
Further, when the shift signal S1 is active, the selector SLT1 selects the white voltage Vwt if the binary signal Ds is L level (when the digit indicates “0”), while the binary signal Ds is H level. If the digit indicates “1”, one of the positive black voltage Vbk (+) and the negative black voltage Vbk (−) is selected based on the frame signal FR. The data signal d1 becomes the positive black voltage Vbk (+) when the binary signal Ds is at the H level, the frame signal FR is at the H level, and the shift signal S1 is at the H level. On the other hand, the data signal d1 becomes the negative side black voltage Vbk (−) when the binary signal Ds is at the H level, the frame signal FR is at the L level, and the shift signal S1 is at the H level.
[0058]
FIG. 7 is a timing chart showing the image data D and the waveform applied to the pixel electrode 118 in a certain pixel 110. For example, when the frame signal FR is at the H level and the image data D is (001), the pixel electrode 118 of the pixel has a high-potential-side black voltage in the subfield Sf1, as shown in FIG. Vbk (+) is written.
[0059]
Thus, the data signals d1 to dn supplied to the data line 114 are only the high potential side black voltage Vbk (+), the white voltage Vwt, and the low potential side black voltage Vbk (-). Therefore, a peripheral circuit such as a drive circuit does not require a circuit for processing an analog signal such as a high-precision D / A conversion circuit or an operational amplifier. Therefore, the circuit configuration is greatly simplified, and the overall cost of the apparatus can be kept low. Further, since display unevenness due to non-uniformity such as element characteristics and wiring resistance does not occur in principle, the electro-optical device according to the present embodiment enables high-quality and high-definition gradation display. .
[0060]
<1-5: Scanning line driving circuit>
FIG. 8 is a block diagram showing a configuration of the scanning line driving circuit 130A. As shown in this figure, the scanning line driving circuit 130A includes a shift register 131 and level conversion circuits LVC1 to LVCm. The shift register 131 transfers the start pulse DY supplied at the beginning of the subfield in accordance with the clock signal CLY. Further, the level conversion circuits LVC1 to LVCm are supplied with the high potential side voltage Vgdd and the low potential side voltage Vgss. The level conversion is performed on each output signal of the shift register 131 and the scanning signal is supplied to each scanning line 112N. G0, G1, G2,..., Gm are supplied. As a result, the H level of the scanning signals G0 to Gm becomes the high potential side voltage Vgdd, while the L level thereof becomes the low potential side voltage Vgss.
[0061]
<1-6: Overall operation>
Next, the operation of the electro-optical device according to the above-described embodiment will be described. FIG. 9 is a timing chart for explaining the operation of the electro-optical device.
First, the frame signal FR is a signal whose level is inverted every frame (1f). On the other hand, the start pulse DY is supplied at the start of each of the subfields Sf1 to Sf3.
[0062]
Here, when the start pulse DY is supplied in one frame (1f) in which the frame signal FR is at L level, the scanning signal G0 is transferred by the transfer according to the clock signal CLY in the scanning line driving circuit 130A (see FIG. 1). , G1, G2, G3,..., Gm are sequentially output exclusively in the period (t). The period (t) is set to a period shorter than the shortest subfield.
[0063]
The scanning signals G0, G1, G2,..., Gm each have a pulse width corresponding to a half cycle of the clock signal CLY, and the scanning signals corresponding to the first scanning line 112N-0 counted from above. G0 is configured to be output with a delay of at least a half cycle of the clock signal CLY after the clock signal CLY first rises after the start pulse DY is supplied.
[0064]
On the other hand, when the start pulse DX is supplied to the data line driving circuit 140, the data line driving circuit 140 transfers the start pulse DX according to the clock signal CLX, and horizontally scans the shift signals S1, S2, S3,. Output sequentially and exclusively during the period (1H). Note that the shift numbers S1, S2, S3,..., Sn each have a pulse width corresponding to a half cycle of the clock signal CLX.
[0065]
<1-7: Writing Operation to Pixel>
FIG. 10 is a timing chart for explaining the writing operation to the pixel 110. First, in the period T0, when the scanning signal GN0 becomes active, the N-channel TFT 117N of the pixel 110-1 shown in FIG. 2 is turned on, and the white voltage supplied to the pixel capacitor CL and the storage capacitor CS via the capacitor line SL. Vwt is written. Therefore, the pixel electrode voltage PX (1, j) increases from the low potential side black voltage Vbk (−) from time t0 and reaches the white voltage Vwt before reaching time t1. Accordingly, the pixel electrode voltage PX (1, j) can be reset to the white voltage Vwt before the data signal dj is written to the pixel 110-1.
[0066]
Then, when the scanning signal GN1 becomes active in the period T1, the N-channel TFT 116N of the pixel 110-1 is turned on, and the data signal dj is supplied to the pixel capacitor CL and the storage capacitor CS. The data signal dj in this period T1 is the high potential side black voltage Vbk (+) as shown in the figure. Therefore, the pixel electrode voltage PX (1, j) rises from the white voltage Vwt from time t1, and reaches the high potential side black voltage Vbk (+) before reaching time t2.
[0067]
As described above, in this embodiment, the pixel electrode voltage PX (i, j) is once reset to the white voltage Vwt before writing the data signal dj to a certain pixel 110. Therefore, even when the active period of the scanning signal is short. This makes it possible to reliably write the necessary voltage. Further, when the N-channel TFT 116N for writing is controlled by the scanning signal GNi, the N-channel TFT 117N for resetting is controlled by the scanning signal GNi-1, so that there is an advantage that it is not necessary to provide a special signal line for resetting. .
[0068]
Further, when the amplitude of the data signal dj changes from the low potential side black voltage Vbk (−) to the high potential side black voltage Vbk (+), the low logic level of the scanning signals GN0 to GN is the low potential side black voltage Vbk. While the low potential voltage Vgss is lower than (−), the high logic level is the higher potential voltage Vgdd higher than the high potential side black voltage Vbk (+). Therefore, the data signal dj can be reliably written.
[0069]
<2. Second Embodiment>
Next, an electro-optical device according to the second embodiment will be described. This electro-optical device has a detailed configuration of the pixel 110, a point that the scanning line 112P is used in addition to the scanning line 112N, a point that the scanning line driving circuit 130B is used instead of the scanning line driving circuit 130A, and a high potential voltage in the power supply circuit 400. The configuration is the same as that of the electro-optical device according to the first embodiment except that Vgdd and low potential voltage Vgss are not generated.
[0070]
FIG. 11 is a block diagram showing a main part of the liquid crystal panel 100 of the second embodiment. As shown in this figure, in the display area A, in addition to the scanning line 112N, a scanning line 112P is formed extending in the X direction. The scanning signals GP0 to GPm are supplied to the scanning lines 112P from the scanning line driving circuit 130B.
[0071]
FIG. 12 is a circuit diagram showing a configuration of the scanning line driving circuit 130B. The scanning line driving circuit 130B includes a shift register 131 and buffer circuits BF0 to BFm. Here, the buffer circuit BF0 is configured in the same manner as the buffer circuit 137A shown in FIG. 16, and generates a scanning signal GN0 obtained by normalizing the output signal of the shift register 131 and an inverted scanning signal GP0. Further, since the buffer circuit BF0 operates by feeding the high potential side black voltage Vbk (+) and the low potential side black voltage Vbk (−), the H level of the scanning signals GN0 and GP0 is set to the high potential side black voltage Vbk (+). On the other hand, the H level becomes the low potential side black voltage Vbk (−). The same applies to the other buffer circuits BF0 to BFm.
[0072]
FIG. 13 is a circuit diagram showing a detailed configuration of the pixel 110 according to the second embodiment. Each pixel 110-1 to 110-1 corresponding to the j-th column counted from the leftmost column of the display area A shown in FIG. The structure of 110-m is shown. FIG. 14 is a timing chart for explaining the writing operation to the pixel 110.
[0073]
Here, the pixel 110-1 includes a P-channel TFT 116P in addition to the N-channel TFT 116N as a write switching element, and a P-channel TFT 117P in addition to the N-channel TFT 117N as a reset switching element. The N channel TFT and the P channel TFT operate in a complementary manner. For this reason, in addition to the scanning signals GN0 to GNm, scanning signals GP0 to GPm obtained by inverting them are required. However, it is not necessary to make the amplitudes of the scanning signals GN0 to GNm and GP0 to GPm larger than the amplitude of the data signal dj.
[0074]
For example, if the voltage of the data signal dj is the high potential side black voltage Vbk (+), if the low potential side black voltage Vbk (−) is supplied to the gate of the P channel TFT 116P at this time, the P channel TFT 116P is passed through. The data signal dj can be written into the pixel capacitor CL and the storage capacitor CS. On the other hand, assuming that the voltage of the data signal dj is the low potential side black voltage Vbk (−), if the high potential side black voltage Vbk (+) is supplied to the gate of the N channel TFT 116N at this time, the N channel TFT 116N is passed through. The data signal dj can be written into the pixel capacitor CL and the storage capacitor CS.
[0075]
First, when the scanning signals GN0 and GP0 become active in the period T0, the N-channel TFT 117N and the P-channel TFT 117P of the pixel 110-1 shown in FIG. 13 are turned on, and the white voltage Vwt is written to the pixel capacitor CL and the storage capacitor CS. It is. In this case, the on-resistance of the N-channel TFT 117N becomes sufficiently low, so that the charges accumulated in the pixel capacitor CL and the storage capacitor CS are discharged through the N-channel TFT 117N. Accordingly, the pixel electrode voltage PX (1, j) can be reset to the white voltage Vwt before the data signal dj is written to the pixel 110-1.
[0076]
In the period T1, when the scanning signal GN1 becomes active, the N-channel TFT 116N and the P-channel TFT 116P of the pixel 110-1 are turned on, and the data signal dj is supplied to the pixel capacitor CL and the storage capacitor CS. The data signal dj in this period T1 is the high potential side black voltage Vbk (+) as shown in the figure. In this case, since the on-resistance of the P-channel TFT 116P is sufficiently low, the data signal dj is written to the pixel capacitor CL and the storage capacitor CS via the P-channel TFT 116P.
[0077]
As described above, in the present embodiment, the N-channel TFT and the P-channel TFT are used as the switching elements for resetting, and the N-channel TFT and the P-channel TFT are used as the switching elements for writing. It can be matched with the amplitude of the data signal. As a result, it is not necessary to apply the high potential voltage Vgdd and the low potential voltage Vgss to the liquid crystal panel 100, and the types of voltages generated in the power supply circuit 400 can be reduced. Further, since each pixel 110 can be driven with a low-amplitude scanning signal, power consumption can be reduced.
[0078]
In general, when a so-called complementary transmission gate configuration is adopted as a switching element for writing, the input / output impedance of the transmission gate is the highest in the vicinity of the intermediate potential of the gate voltage. It will be. However, by using the above-described configuration and driving method, the writing time of the white level Vwt is substantially doubled, and writing can be performed sufficiently. The difference between the white level and the black level (Vdp = Vbk (+) − Vwt and Vdn = Vwt−Vbk (−)) is the threshold voltage of the TFT (Vtn: threshold voltage of N channel TFT, Vtp: same P channel TFT). When close (Vdp≈Vtp, Vdn≈Vtn), the effect of the present application becomes extremely large.
[0079]
<3. Third Embodiment>
Next, an electro-optical device according to the third embodiment will be described. In the liquid crystal panel 100 of the first and second embodiments, the data signal is written to all the pixels 110 for each frame, but the electro-optical device according to the third embodiment writes the voltage. Whether to perform or hold the previous voltage can be selected in units of rows.
[0080]
This electro-optical device has a detailed configuration of the pixel 110, a point that uses the scanning line 112P and the reset line 112RN in addition to the scanning line 112N, a point that uses the scanning line driving circuit 130C instead of the scanning line driving circuit 130A, and a power supply circuit 300 The configuration is the same as that of the electro-optical device according to the first embodiment except that the low potential voltage Vgss is not generated and the control signal generated by the timing signal generation circuit 200 is different.
[0081]
<3-1: Overall configuration>
FIG. 15 is a block diagram showing a main part of the liquid crystal panel 100 of the third embodiment. As shown in the figure, in the display area A, in addition to the scanning line 112N, a scanning line 112P and a reset line 112RN are formed extending in the X direction. The scanning signals GP1 to GPm are supplied to the scanning lines 112P, and the reset signals RN1 to RNm are supplied to the reset lines 112RN from the scanning line driving circuit 130C.
[0082]
<3-2: Scanning line driving circuit>
FIG. 16 is a circuit diagram showing a configuration of the scanning line driving circuit 130C. The scanning line driving circuit 130C includes m unit circuits Uy1 to Uym, a plurality of address lines Ly, and signal lines Lc and Ld. An address signal ADRS is supplied to the address line Ly, an enable signal EN is supplied to the signal line Lc, and a reset pulse RST is supplied to the signal line Ld.
[0083]
The address signal ADRS specifies a certain row in the display area A. For example, if the display area A has 256 rows, the address signal ADRS is an 8-bit signal and the address lines Ly are eight. The enable signal EN designates whether or not writing of the data signal is permitted for each row, and becomes active at the H level. With this enable signal EN, it is possible to write data signals to the pixels 110 belonging to a certain row, while prohibiting data signals from being written to the pixels 110 belonging to other rows. Further, the reset pulse RST is a 1H cycle pulse, and is synchronized with the timing at which the address specified by the address signal ADRS changes. These control signals are generated by a timing signal generation circuit 200 (not shown).
[0084]
Next, the unit circuit Uy1 includes a decoder DCD1, D flip-flops 133 and 134, an inverter 135, a NOR circuit 136, and buffer circuits 137A and 138. Among them, the high potential side black voltage Vbk (+) and the low potential side black voltage Vbk (−) are supplied to the buffer circuit 137A, while the buffer circuit 138 is supplied with the high potential side voltage Vgdd and the low potential side black voltage Vbk ( -) Is powered. The output signal amplitude of the buffer circuit 137A swings between Vbk (+) and Vbk (−), and the output signal amplitude of the buffer circuit 138 swings between Vgdd and Vbk (−).
[0085]
The decoder DCD1 is composed of a combinational logic circuit. The decoder DCD1 decodes the address signal ADRS to generate a decode signal dcd1 that becomes active at the H level. The D flip-flop 133 latches the enable signal EN at the rising edge of the decode signal dcd1 and generates a signal ENB11. The NOR circuit 136 inverts the logical sum of the decoded signal dcd1 and the signal obtained by inverting the signal ENB11 to generate the signal RSS1.
[0086]
As described above, the enable signal EN is a signal indicating that the data signal is allowed to be written. By latching the enable signal EN based on the decode signal dcd1, it can be determined whether the data signal is allowed to be written to the pixels 110 in the first row. . That is, the signal ENB11 becomes active when writing is permitted for the first row. The signal RSS1 is active for a period in which writing is permitted for the first row and the address signal ADRS designates the first row. The buffer 138 supplies an inverted version of the signal RSS1 to the reset line 112RN-1 as the reset signal RN1. Therefore, when writing is performed for the first row, the reset signal RN1 is always active.
[0087]
Next, the D flip-flop 134 latches the signal ENB11 at the falling edge of the decode signal dcd1 to generate the signal ENB12. Therefore, the signal ENB12 becomes active (H level) at the timing when the period in which the address signal ADRS designates the first row ends, and becomes inactive (L level) when the reset pulse RST is supplied. As described above, since the reset pulse RST is a 1H cycle pulse, the signal ENB12 is active for 1H period. The buffer 137A supplies an inverted version of the signal ENB12 to the scanning line 112P-1 as the scanning signal GP1, and supplies the scanning signal GN1 in phase with the signal ENB12 to the scanning line 112N-1. Therefore, when the active period of the reset signal RN1 ends, the scanning signals GP1 and GN1 become active.
The other unit circuits Uy2 to Uym are configured in the same manner as the unit circuit Uy1 described above.
[0088]
Here, the operation of the scanning line driving circuit 130C will be specifically described. FIG. 17 is a timing chart showing an operation example of the scanning line driving circuit 130C. In this example, the address signal ADRS is specified in the order of the first row, the m-th row, and the second row. In the first frame (f1), data signals are written to the first row and the second row, In 2 frames (f2), data signals are written for the m-th row.
[0089]
First, when the enable signal EN and the decode signal dcd1 become active in the period T0, the signal ENB11 becomes H level in synchronization with the rising edge of the decode signal dcd1. Then, a signal RSS1 is generated based on the decode signal dcd1 and the signal ENB11. In this case, the signal RSS1 is active in the period T0. On the other hand, since the signal ENB12 is obtained by latching the signal ENB11 at the falling edge of the decode signal dcd1, the signal ENB12 changes to H level from time t1, and then maintains H level. When the reset pulse RST becomes active at time t2, Transition from level to L level. Therefore, in the first frame, the signal ENB11 (scanning signal GN1) becomes active.
[0090]
In addition, since the enable signal EN and the decode signal dcdm become active in the period T2, the signal ENB22 (scanning signal GN1) becomes active in the first frame, similarly to the signal ENB11 described above. On the other hand, the enable signal EN is inactive during the period T1 during which the decode signal dcdm is active. Therefore, in the first frame, the signal ENB2m (scanning signal GNm) is inactive, and the data signal is not written to the pixels 110 in the m-th row.
[0091]
<3-3: Pixel Configuration and Data Signal Writing Operation>
FIG. 18 is a circuit diagram showing the detailed configuration of the pixel 110 according to the third embodiment. Each pixel 110-1˜110 corresponding to the jth column counted from the leftmost column of the display area A shown in FIG. The structure of 110-m is shown. FIG. 19 is a timing chart for explaining the writing operation to the pixel 110 when the enable signal EN is active. FIG. 20 is a timing chart for explaining a writing operation to the pixel 110 when the enable signal EN is inactive.
[0092]
Here, the pixel 110-1 includes an N-channel TFT 116N and a P-channel TFT 116P as write switching elements, and an N-channel TFT 117N as a reset switching element.
[0093]
First, assume that the enable signal EN is active. As shown in FIG. 19, when the reset signal RN1 becomes active in the period T0, the N-channel TFT 117N of the pixel 110-1 is turned on, and the white voltage Vwt is written to the pixel capacitor CL and the storage capacitor CS. The H level of the reset signal RN1 is a high potential voltage Vgdd higher than the high potential side black voltage Vbk (+). Therefore, in this example, the initial value of the pixel electrode voltage PX (1, j) is the low potential side black voltage Vbk (−), but sufficient writing can be performed even in the case of the high potential side black voltage Vbk (+). . Accordingly, the pixel electrode voltage PX (1, j) can be reset to the white voltage Vwt before the data signal dj is written to the pixel 110-1.
[0094]
Next, when the scanning signals GN1 and GP1 become active in the period T1, the N-channel TFT 116N and the P-channel TFT 116P of the pixel 110-1 are turned on, and the data signal dj is supplied to the pixel capacitor CL and the storage capacitor CS. The data signal dj in this period T1 is the high potential side black voltage Vbk (+) as shown in the figure. In this case, since the on-resistance of the P-channel TFT 116P is sufficiently low, the data signal dj is written to the pixel capacitor CL and the storage capacitor CS via the P-channel TFT 116P.
[0095]
The amplitudes of the scanning signals GN1 and GP1 fluctuate between the high potential side black voltage Vbk (+) and the low potential side black voltage Vbk (−). On the other hand, the data signal dj can take two values of the high potential side black voltage Vbk (+) and the low potential side black voltage Vbk (−), but the N-channel TFT 116N and the P-channel TFT 116P operate in a complementary manner. Therefore, the data signal dj can be written to the pixel capacitor CL and the storage capacitor CS by the scanning signals GN1 and GP1.
[0096]
Next, when the enable signal EN is inactive, the reset signal RN1 is always at the H level (active) as shown in FIG. Therefore, the N-channel TFT 117N is always on, and the white voltage Vwt is always written to the pixel capacitor CL and the storage capacitor CS. For this reason, even if the off-leakage current of the TFT, which is the switching element used for writing, is relatively large, the white level applied voltage does not fluctuate, so there is no need to rewrite the white level signal again.
[0097]
As described above, according to the present embodiment, the row is designated by the address signal ADRS and the writing of the data signal dj is designated by the enable signal EN. Therefore, only for the row that needs to be rewritten, Writing can be performed. As a result, power consumption can be reduced.
[0098]
<4. Fourth Embodiment>
Next, an electro-optical device according to the fourth embodiment will be described. This electro-optical device has a detailed configuration of the pixel 110, a point that the reset line 112RP is used in addition to the reset line 112RN, a point that the scanning line driving circuit 130D is used instead of the scanning line driving circuit 130C, and a high potential voltage in the power supply circuit 300. The configuration is the same as that of the electro-optical device of the third embodiment except that Vgdd is not generated.
[0099]
FIG. 21 is a block diagram showing a main part of the liquid crystal panel 100 of the fourth embodiment. As shown in this figure, in the display area A, a reset line 112RP is formed extending in the X direction in addition to the reset line 112RN. Reset signals RP1 to RPm are supplied from the scanning line driving circuit 130D to the reset line 112RP.
[0100]
A detailed configuration of the scanning line driving circuit 130D is shown in FIG. The scanning line driving circuit 130D is different from the scanning line driving circuit 130C shown in FIG. 16 only in that a buffer circuit 137B is used instead of the buffer circuit 138. The detailed configuration of the buffer circuit 137B is the same as that of the buffer circuit 137A, and a high potential side black voltage Vbk (+) and a low potential side black voltage Vbk (-) are supplied thereto. Therefore, in the reset signals RN1 to RNm and RP1 to RPm of this embodiment, the H level becomes the high potential side black voltage Vbk (+), while the L level becomes the low potential side black voltage Vbk (−). Note that the operation of the scanning line driving circuit 130D is the same as the operation of the scanning line driving circuit 130C described with reference to FIG.
[0101]
FIG. 23 is a circuit diagram showing a detailed configuration of the pixel 110 according to the fourth embodiment. Each pixel 110-1˜110 corresponding to the jth column counted from the leftmost column of the display area A shown in FIG. The structure of 110-m is shown. FIG. 24 shows a timing chart when the enable signal EN is active, and FIG. 25 shows a timing chart when the enable signal EN is inactive.
First, the pixel 110 of the fourth embodiment is different from the pixel 110 of the third embodiment shown in FIG. 18 in that a P-channel TFT 117P is used in addition to the N-channel TFT 117N as a reset switching element. That is, in this embodiment, the white voltage Vwt is written to the pixel capacitor CL and the storage capacitor CS by the complementary operation of the N-channel TFT 117N and the P-channel TFT 117P.
[0102]
For this reason, the reset signal RP1 is required in addition to the reset signal RN1, and as shown in FIG. 24, the amplitude of the high potential side black, which is the maximum value that the pixel electrode voltage PX (1, j) can take, is obtained. It is sufficient to swing from the voltage Vbk (+) to the low potential side black voltage Vbk (-) which is the minimum value.
[0103]
As a result, it is not necessary to apply the high potential voltage Vgdd and the low potential voltage Vgss to the liquid crystal panel 100, and the types of voltages generated in the power supply circuit 400 can be reduced. Furthermore, since each pixel 110 can be driven with a low-amplitude reset signal, power consumption can be reduced.
[0104]
<5. Mechanical configuration of LCD panel>
Next, the structure of the liquid crystal panel used in each embodiment described above will be described with reference to FIGS. Here, FIG. 26 is a plan view showing the configuration of the liquid crystal panel 100, and FIG. 27 is a cross-sectional view taken along the line ZZ ′ in FIG.
[0105]
As shown in these drawings, in the liquid crystal panel 100, the element substrate 101 on which the pixel electrode 118 and the like are formed and the counter substrate 102 on which the counter electrode 108 and the like are formed have a certain gap by a sealant 104. The liquid crystal 105 as an electro-optic material is sandwiched between the gaps while being bonded together. Actually, the sealing material 104 has a cut-out portion, and after the liquid crystal 105 is sealed through this, the sealing material 104 is sealed with the sealing material 106.
[0106]
Here, as the element substrate 101, a semiconductor substrate can be used in addition to a glass substrate. Moreover, since each pixel 110 includes a plurality of TFTs as described above, the aperture ratio is reduced when a transmissive panel is used. Therefore, it is desirable that the pixel electrode 118 is formed of a reflective metal such as aluminum and the liquid crystal panel 100 is used as a reflective type. On the other hand, the counter substrate 102 is transparent because it is made of glass or the like.
[0107]
Here, the data line driving circuit 140 described above is formed on the opposite surface of the element substrate 101 and on the outer side of the sealing material 104. Further, a plurality of connection electrodes 107 are formed on one side, and various signals from the timing signal generation circuit 200 are supplied thereto. Two scanning line driving circuits 130 are formed on two sides adjacent to the one side. Note that if the delay of the scanning signal supplied to the scanning line 112 does not become a problem, the scanning line driving circuit 130 may be formed on only one side.
[0108]
On the other hand, the common electrode 108 of the counter substrate 102 is electrically connected to the element substrate 101 by a conductive material provided in at least one of the four corners of the bonding portion with the element substrate 101. In addition, the counter substrate 102 is provided with color filters arranged in a stripe shape, a mosaic shape, a triangle shape, or the like according to the use of the liquid crystal panel 100, and secondly, for example, chromium. A black matrix such as resin black in which carbon, titanium, or the like is dispersed in a photoresist is provided, and third, a backlight for irradiating the liquid crystal panel 100 with light is provided. Particularly in the case of color light modulation, a black matrix is provided on the counter substrate 102 without forming a color filter.
[0109]
In addition, the opposing surfaces of the element substrate 101 and the counter substrate 102 are each provided with an alignment film or the like that is rubbed in a predetermined direction, and a polarizing plate (not shown) corresponding to the alignment direction on each back side. Are provided respectively. However, if a polymer dispersion type liquid crystal dispersed as fine particles in a polymer is used as the liquid crystal 105, the above-described alignment film, polarizing plate, and the like are not required. As a result, the light utilization efficiency is increased. This is advantageous in terms of reducing power consumption.
[0110]
Instead of forming part or all of the peripheral circuits such as the drive circuit 120 on the element substrate 101, for example, a driving IC chip mounted on a film using a TAB (Tape Automated Bonding) technique is used. It is good also as a structure electrically and mechanically connected through the anisotropic conductive film provided in the predetermined position of 101, and drive IC chip itself is used for the element substrate 101 using COG (Chip On Grass) technology. It is good also as a structure electrically and mechanically connected to this predetermined position via an anisotropic conductive film.
[0111]
In the above-described embodiments, the active matrix type liquid crystal display device has been described as an example. However, the present invention is not limited to this, and the present invention can also be applied to a passive type using STN (Super Twisted Nematic) liquid crystal. Furthermore, as an electro-optical material, in addition to liquid crystal, an electroluminescence element or the like can be used for a display device that performs display by the electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to that of the liquid crystal display device described above.
[0112]
<6. Electronic equipment>
Next, some examples in which the above-described liquid crystal device is used in a specific electronic device will be described.
<6-1: Projector>
First, a projector using the electro-optical device according to the embodiment as a light valve will be described. FIG. 28 is a plan view showing the configuration of the projector. As shown in this figure, in the projector 1100, a polarization illumination device 1110 is arranged along the system optical axis PL. In this polarization illumination device 1110, the light emitted from the lamp 1112 becomes a substantially parallel light beam as reflected by the reflector 1114, and enters the first integrator lens 1120. Thereby, the emitted light from the lamp 1112 is divided into a plurality of intermediate light beams. The divided intermediate light beam is converted into a single type of polarized light beam (s-polarized light beam) whose polarization directions are substantially uniform by a polarization conversion element 1130 having a second integrator lens on the light incident side, and the polarized illumination device 1110 It will be emitted from.
[0113]
Now, the s-polarized light beam emitted from the polarization illumination device 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarization beam splitter 1140. Of this reflected light beam, the blue light (B) light beam is reflected by the blue light reflecting layer of the dichroic mirror 1151 and modulated by the reflective electro-optical device 100B. Of the light beams that have passed through the blue light reflecting layer of the dichroic mirror 1151, the red light (R) light beam is reflected by the red light reflecting layer of the dichroic mirror 1152, and is modulated by the reflective electro-optical device 100R. . On the other hand, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the green light (G) light beam is transmitted through the red light reflecting layer of the dichroic mirror 1152 and modulated by the reflective electro-optical device 100G. .
[0114]
In this way, the red, green, and blue lights that have been color-light modulated by the electro-optical devices 100R, 100G, and 100B are sequentially combined by the dichroic mirrors 1152 and 1151 and the polarization beam splitter 1140, and then are projected by the projection optical system 1160. Is projected on the screen 1170. In addition, since the light beams corresponding to the primary colors of R, G, and B are incident on the electro-optical devices 100R, 100G, and 100B by the dichroic mirrors 1151 and 1152, a color filter is not necessary.
[0115]
<6-2: Mobile computer>
Next, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 29 is a perspective view showing the configuration of this personal computer. In the figure, a computer 1200 includes a main body 1204 having a keyboard 1202 and a display unit 1206. The display unit 1206 is configured by adding a front light to the front surface of the electro-optical device 100 described above.
[0116]
In this configuration, since the electro-optical device 100 is used as a reflection direct-view type, it is desirable that the pixel electrode 118 has irregularities so that the reflected light is scattered in various directions.
[0117]
<6-3: Mobile phone>
Further, an example in which the electro-optical device is applied to a mobile phone will be described. FIG. 30 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1300 includes the electro-optical device 100 in addition to a plurality of operation buttons 1302 as well as an earpiece 1304 and a mouthpiece 1306. The electro-optical device 100 is also provided with a front light on the front surface as necessary. Also in this configuration, since the electro-optical device 100 is used as a reflection direct view type, a configuration in which the pixel electrode 118 is uneven is desirable.
[0118]
In addition to the electronic devices described with reference to FIGS. 28 to 30, the electronic devices include a liquid crystal television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor. , Workstations, videophones, POS terminals, devices with touch panels, and the like. Needless to say, the electro-optical device according to the embodiment can be applied to these various electronic devices.
[0119]
【The invention's effect】
As described above, according to the present invention, the signal applied to the data line is binarized, and high-quality gradation display is possible. In addition, various liquid crystals can be handled with a simple configuration.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to a first embodiment of the invention.
FIG. 2 is a circuit diagram illustrating a detailed configuration of a pixel 110 used in the electro-optical panel according to the first embodiment.
(A), (b), and (c) are diagrams for explaining the concept of a Von period, a Voff period, and a subfield in the electro-optical device.
FIG. 3 is a diagram showing the relationship between the effective voltage value of liquid crystal and the relative transmittance.
FIG. 4 is a diagram showing how one frame is divided when image data D is 3 bits.
FIG. 5 is a block diagram showing a configuration of a data line driving circuit 140 in the same electro-optical device.
6 is a truth table showing a selection operation in the selector SLT1 of the data line driving circuit 140. FIG.
7 is a timing chart showing image data D and a waveform applied to a pixel electrode 118 in a certain pixel 110. FIG.
FIG. 8 is a block diagram showing a configuration of a scanning line driving circuit 130A.
FIG. 9 is a timing chart for explaining the operation of the electro-optical device.
FIG. 10 is a timing chart for explaining a writing operation to the pixel 110;
FIG. 11 is a block diagram showing a main part of a liquid crystal panel 100 of a second embodiment.
FIG. 12 is a circuit diagram showing a configuration of a scanning line driving circuit 130B of the same embodiment;
FIG. 13 is a circuit diagram showing a detailed configuration of a pixel 110 according to the same embodiment.
14 is a timing chart for explaining a writing operation to the pixel 110. FIG.
FIG. 15 is a block diagram showing a main part of a liquid crystal panel 100 of a third embodiment.
FIG. 16 is a circuit diagram showing a configuration of a scanning line driving circuit 130C of the same embodiment;
FIG. 17 is a timing chart showing an operation example of the scanning line driving circuit 130C.
FIG. 18 is a circuit diagram showing a detailed configuration of a pixel 110 according to the embodiment.
FIG. 19 is a timing chart for explaining the writing operation to the pixel 110 when the enable signal is active.
FIG. 20 is a timing chart for explaining a writing operation to the pixel 110 when the enable signal is inactive.
FIG. 21 is a block diagram showing a main part of a liquid crystal panel 100 of a fourth embodiment.
FIG. 22 is a circuit diagram showing a configuration of a scanning line driving circuit 130D of the same embodiment;
FIG. 23 is a circuit diagram showing a detailed configuration of a pixel 110 according to the same embodiment.
FIG. 24 is a timing chart for explaining a writing operation to the pixel 110 when the enable signal is active.
FIG. 25 is a timing chart for explaining a writing operation to the pixel 110 when the enable signal is inactive.
26 is a plan view showing the structure of the liquid crystal panel 100. FIG.
27 is a cross-sectional view showing a structure of the liquid crystal panel 100. FIG.
FIG. 28 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.
FIG. 29 is a perspective view illustrating a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device is applied.
FIG. 30 is a perspective view showing a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device is applied.
[Explanation of symbols]
100 …… LCD panel
110 …… Pixel
112N, 112P ... Scanning line
114 …… Data line
SL: Capacity line
118 …… Pixel electrode
CS …… Storage capacity
130A to 130D: Scanning line driving circuit
140... Data line driving circuit

Claims (5)

A plurality of data lines, a plurality of scanning lines, and a reset line corresponding to each of the plurality of scanning lines, and a plurality of pixels corresponding to intersections of the plurality of scanning lines and the plurality of data lines. An electro-optic panel arranged,
A scanning unit that activates a reset signal to a reset line of a row in which writing of a data signal supplied to the data line is permitted, then inactivates, and activates a scanning signal to the scanning line of the row With
The pixel is
A pixel capacitance formed between the pixel electrode and the counter electrode;
Writing means provided between one data line and the pixel electrode, and writes a data signal supplied to the data line to the pixel capacitor when a scanning signal supplied to the one scanning line becomes active When,
Reset means for resetting the voltage of the pixel electrode to a predetermined reset voltage when a reset signal supplied to the reset line corresponding to the one scanning line becomes active, and
The reset means includes an N-channel transistor whose on / off is controlled based on the reset signal and a P-channel transistor whose on / off is controlled based on an inverted reset signal corresponding to the reset signal. Electro-optical panel featuring The electro-optical panel according to claim 1, wherein the scanning unit activates a reset signal to a reset signal line in a row where writing is not permitted. With multiple capacitance lines,
The pixel includes a storage capacitor in which the pixel electrode and one terminal are connected, and the capacitor line and the other terminal are connected,
The writing unit includes a first switching element that is provided between the one data line and the pixel electrode and that is turned on / off based on a scanning signal supplied to the one scanning line. ,
The electro-optical panel according to claim 1, wherein the N and P channel transistors in the reset unit are provided between the pixel electrode and the capacitor line. The electro-optical panel according to claim 1, wherein the reset voltage matches a voltage of the counter electrode. An electronic apparatus comprising the electro-optical panel according to claim 1.

Images