JP2015161836A - liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve smaller pixels than pixels each including two SRAMs.SOLUTION: A pixel 12 comprises, a DRAM 121 including a switch SW11 and a capacitor C11, an SRAM 122 including a switch SW12 and a memory MEM2, and a liquid crystal display element LC. After data to be outputted to a column data line d is written into a capacitor C11 in every pixel 12 composing an image display part, the switch SW12 of every pixel 12 is turned on, data of the capacitor C11 are all at once transferred to and held by the MEM2 including two inverters INV11 and INV12 in the SRAM 122, and is applied to a reflective electrode PE1. The pixel 12 composed of eight transistors and the one capacitor C11 allows a pixel to be configured with the small number of constituent elements, and the DRAM 121, the SRAM 122 and the reflective electrode PE are effectively arranged in an element height direction, thereby reducing the size of the pixel.

Description

  The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that performs gradation display by combining a plurality of subframes according to a plurality of gradation levels represented by a plurality of bits.

  Conventionally, a sub-frame driving method is known as one of halftone display methods in a liquid crystal display device. In the sub-frame driving method, which is a type of time-axis modulation method, a predetermined period (for example, one frame, which is a display unit of one image in the case of a moving image) is divided into a plurality of sub-frames to obtain gradations to be displayed. The pixel is driven by a combination of the corresponding subframes. The gradation to be displayed is determined by the ratio of the pixel driving period in a predetermined period, and this ratio is specified by a combination of subframes.

  In this sub-frame driving type liquid crystal display device, each pixel is known to be composed of a master latch and a slave latch, a liquid crystal display element, and a total of three switching transistors (first to third) ( For example, see Patent Document 1). In this pixel, the master latch applies 1-bit first data to one of the two input terminals through the first switching transistor and is complementary to the first data on the other input terminal. When the second data having the same relationship is applied through the second switching transistor and the pixel is selected by the row selection signal applied through the row scanning line, the first and second switching transistors described above are used. Is turned on to write the first data. For example, when the first data has a logical value “1” and the second data has a logical value “0”, the pixel performs display.

  After each data is written to all the pixels by the same operation as described above, the third switching transistors of all the pixels are turned on within the subframe period, and the data written to the master latch is simultaneously read and read to the slave latch. The data latched by the slave latch is applied from the slave latch to the pixel electrode of the liquid crystal display element. Thereafter, the above operation is repeated for each subframe, and a desired gradation display is performed by combining all subframes within one frame period.

  That is, in the sub-frame driving type liquid crystal display device, all the sub-frames in one frame period are assigned in advance to the same period or different predetermined periods, and at the time of maximum gradation display in each pixel. Display is performed in all subframes. In the case of the minimum gradation display, no display is performed in all subframes. In the case of other gradations, the subframe to be displayed is selected according to the display gradation. In this conventional liquid crystal display device, the input data is digital data indicating a gradation, and it is also a digital driving system having a two-stage latch configuration.

JP-T-2001-523847

  However, in the above-described conventional liquid crystal display device, since the two latches in each pixel are each composed of a static random access memory (SRAM), the number of transistors is large and it is difficult to reduce the size of the pixel. .

  The present invention has been made in view of the above points, and an object of the present invention is to provide a liquid crystal display device capable of downsizing the pixel as compared with a pixel using two SRAMs in the pixel.

In order to achieve the above object, the present invention comprises an image display unit composed of a plurality of pixels provided at intersections where a plurality of column data lines and a plurality of row scanning lines respectively intersect, and an image display unit Pixel control means for controlling a plurality of pixels
Each of the plurality of pixels
A display element in which liquid crystal is filled and sealed between the opposing pixel electrode and the common electrode, and each sub for displaying each frame of the video signal in a plurality of sub-frames having a display period shorter than one frame period of the video signal A random access memory is configured together with a first switching means for sampling frame data via a column data line and the first switching means, and the subframe data sampled by the first switching means is updated. A static random access memory is configured with the first signal holding means for storing, the second switching means for outputting the subframe data stored in the first signal holding means, and the second switching means. Sub-stored in the first signal holding means supplied through the second switching means Memory content is rewritten with frame data, characterized in that it comprises a second signal holding means for applying the output data to the pixel electrodes.

  According to the present invention, pixel miniaturization can be realized as compared with a pixel using two SRAMs in the pixel.

1 is an overall configuration diagram of an embodiment of a liquid crystal display device of the present invention. 1 is a circuit diagram of a first embodiment of a pixel which is a main part of the present invention. It is a circuit diagram of an example of an inverter. FIG. 3 is a cross-sectional structure diagram of an example of one pixel shown in FIG. 2. 3 is a timing chart for explaining the operation of a pixel in the liquid crystal display device of the present invention. It is explanatory drawing which multiplexes the saturation voltage of the liquid crystal of a liquid crystal display device, and the threshold voltage of a liquid crystal as binary weighted pulse width modulation data.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a block diagram of an embodiment of a liquid crystal display device according to the present invention. In the figure, a liquid crystal display device 10 according to the present embodiment includes an image display unit 11 in which a plurality of pixels 12 are regularly arranged, a timing generator 13, a vertical shift register 14, a data latch circuit 15, a horizontal And a driver 16. Further, the horizontal driver 16 includes a horizontal shift register 161, a latch circuit 162, and a level shifter / pixel driver 163.

  The image display unit 11 has a total of m sets (m is a natural number of 2 or more) of normal rotation scanning, one set connected to the vertical shift register 14 and extending in the row direction (X direction). Lines g1 to gm and inverted row scanning lines gb1 to gbm, and n (n is a natural number of 2 or more) column data lines d1 having one end connected to the level shifter / pixel driver 163 and extending in the column direction (Y direction) Are provided at each intersection where .about.dn intersects, and have a total of m.times.n pixels 12 arranged in a two-dimensional matrix. The i-th (i = 1 to m) normal row scanning line gi and the inverted row scanning line gbi constitute a set of row scanning lines with the i-th two. The present invention is characterized by the circuit configuration of the pixel 12, and an embodiment thereof will be described later. All the pixels 12 in the image display unit 11 are commonly connected to a forward trigger pulse trigger line trig and an inverted trigger pulse trigger line trigb, one end of which is connected to the timing generator 13.

  The normal row scanning pulses transmitted by the normal row scanning lines g1 to gm and the inverted row scanning pulses transmitted by the inverted row scanning lines gb1 to gbm are always in an inverse logical value relationship (complementary relationship). Further, the normal trigger pulse transmitted by the normal trigger pulse trigger line trig and the reverse trigger pulse transmitted by the reverse trigger pulse trigger line trigb are always in an inverse logical value relationship (complementary relationship).

  The timing generator 13 receives external signals such as a vertical synchronization signal Vst, a horizontal synchronization signal Hst, and a basic clock CLK from the host device 20 as input signals, and based on these external signals, the AC signal FR, V start pulses VST, H Various internal signals such as a start pulse HST, clock signals VCK and HCK, a latch pulse LT, and a trigger pulse trig / trigb are generated.

  Among the above internal signals, the alternating signal FR is a signal whose polarity is inverted every subframe, and a common electrode voltage Vcom described later is applied to the common electrode of the liquid crystal display element in the pixel 12 constituting the image display unit 11. Supplied as The start pulse VST is a pulse signal output at the start timing of each subframe to be described later, and switching of subframes is controlled by the start pulse VST. The start pulse HST is a pulse signal output at the start timing input to the horizontal shift register 161. The clock signal VCK is a shift clock that defines one horizontal scanning period (1H) in the vertical shift register 14, and the vertical shift register 14 performs a shift operation at the timing of VCK. The clock signal HCK is a shift clock in the horizontal shift register 161, and is a signal for shifting, for example, 32-bit data.

  The latch pulse LT is a pulse signal that is output at a timing when the horizontal shift register 161 has shifted the data for the number of pixels in one row in the horizontal direction. The timing generator 13 supplies a normal rotation trigger pulse to the all pixels 12 constituting the image display unit 11 through the trigger line trig and an inversion trigger pulse through the trigger line trigb. The normal trigger pulse and the reverse trigger pulse are output immediately after the data is sequentially written to the first signal holding means in each pixel 12 in the image display unit 11 within the subframe period, and within the subframe period. The data of the first signal holding means of all the pixels 12 in the image display unit 11 is transferred at a time to the second signal holding means in the same pixel.

  The vertical shift register 14 transfers the V start pulse VST supplied at the beginning of each subframe in accordance with the clock signal VCK, and performs normal rotation with respect to the normal row scanning lines g1 to gm and the inverted row scanning lines gb1 to gbm. A row scanning pulse and an inverted row scanning pulse are sequentially and exclusively supplied in units of 1H. The vertical shift register 14 supplies the normal row scanning pulse and the reverse row scanning pulse to all the normal row scanning lines g1 to gm and the reverse row scanning lines gb1 to gbm in one frame period. That is, the vertical shift register 14 is the most in the image display unit 11 with respect to the i-th (however, i = 1 to m) pair of normal row scanning lines gi and inverted row scanning lines gbi in one frame period. From the first set of row scanning lines g1 and gb1 to the m-th row scanning line gm and gbm at the bottom, one set is sequentially rotated in normal 1H increments and inverted. The row scanning pulse is supplied, and the normal rotation scanning pulse and the inversion row scanning pulse are supplied to all m sets in one frame period.

  The data latch circuit 15 latches 32-bit width data divided for each subframe supplied from an external circuit (not shown) based on the basic signal CLK from the host device 20, and then synchronizes with the basic signal CLK. To the horizontal shift register 161. Here, in this embodiment in which one frame of a video signal is divided into a plurality of subframes having a display period shorter than one frame period of the video signal and gradation display is performed by a combination of subframes, The circuit converts the gradation data indicating the gradation for each pixel of the video signal into 1-bit subframe data for each subframe for displaying the gradation of each pixel in the entire plurality of subframes. The external circuit further supplies the sub-frame data for 32 pixels in the same sub-frame together to the data latch circuit 15 as the 32-bit width data.

  When viewed in the processing system of 1-bit serial data, the horizontal shift register 161 starts shifting by the H start pulse HST supplied from the timing generator 13 at the beginning of 1H, and has a 32-bit width supplied from the data latch circuit 15. Data is shifted in synchronization with the clock signal HCK. The latch circuit 162 follows the latch pulse LT supplied from the timing generator 13 when the horizontal shift register 161 has shifted the 32-bit width data by the same n bits as the number of pixels n for one row of the image display unit 11. The n-bit data (that is, n subframe data for n pixels in the same row) supplied in parallel from the horizontal shift register 161 are latched and output to the level shifter of the level shifter / pixel driver 163. When the data transfer to the latch circuit 162 is completed, the H start pulse is output again from the timing generator 13, and the horizontal shift register 161 resumes shifting the 32-bit width data from the data latch circuit 15 in accordance with the clock signal HCK.

  The level shifter of the level shifter / pixel driver 163 shifts the signal level of n subframe data corresponding to n pixels in one row supplied by being latched by the latch circuit 162 to the liquid crystal drive voltage. The pixel driver of the level shifter / pixel driver 163 has a function of inverting the polarity of n subframe data corresponding to n pixels in one row after the level shift, and the polarity inversion subframe data is transferred to n data lines d1. Output in parallel to ~ dn. Since the polarity-inverted subframe data is output with the polarity reversed again by the second signal holding means MEM2 described later, the subframe data is returned to the original polarity when latched by the latch circuit 162, and the second The signal holding means MEM2 is applied to the reflective electrode PE1.

  The horizontal shift register 161, the latch circuit 162, and the level shifter / pixel driver 163 constituting the horizontal driver 16 output data for a pixel row to which data is written this time in 1H, and data for a pixel row to which data is written in the next 1H. Shift in parallel. In a certain horizontal scanning period, n subframe data corresponding to n pixels in one row latched are simultaneously output in parallel to the n data lines d1 to dn as data signals.

  Among the plurality of pixels 12 constituting the image display unit 11, n pixels 12 in one row selected by the row scanning pulse and the inverted row scanning pulse from the vertical shift register 14 are simultaneously transmitted from the level shifter / pixel driver 163. The output n subframe data for one row is sampled via n data lines d1 to dn, and written in first signal holding means (to be described later) in each pixel 12.

  Next, an embodiment of the pixel 12 in the liquid crystal display device of the present invention will be described in detail.

  FIG. 2 shows an equivalent circuit diagram of an embodiment of a pixel which is a main part of the present invention. In the figure, a pixel 12 is located at the intersection of one arbitrary column data line d and two arbitrary sets of normal row scanning lines g and inverted row scanning lines gb in FIG. Is provided. The pixel 12 is a dynamic random access memory (DRAM) 121 composed of a switch SW11 as a first switching means and a capacitor C11 as a first signal holding means MEM1, and a second switching means. It has a static random access memory (SRAM) 122 composed of a switch SW12 and two inverters INV11 and INV12 which are the second signal holding means MEM2, and a liquid crystal display element LC. The liquid crystal display element LC has a known structure in which a liquid crystal LCM is filled and enclosed in a space between a reflective electrode PE1 which is a pixel electrode having light reflection characteristics arranged in a spaced-apart relationship and a common electrode CE having light transmission characteristics. It is.

  The switch SW11 has an N-channel MOS field effect transistor (hereinafter referred to as NMOS transistor) and a P-channel MOS field effect transistor (hereinafter referred to as PMOS transistor) in which the drains are connected to each other and the sources are connected to each other. And a known transmission gate structure. The gate of the NMOS transistor is connected to the normal row scanning line g, and the gate of the PMOS transistor is connected to the inverted row scanning line gb. Further, the NMOS transistor and the PMOS transistor constituting the switch SW11 have their drains connected to the column data line d and their sources connected to the non-ground side terminal of the capacitor C11 and the switch SW12.

  As described above, the capacitor C11 serving as the first signal holding means constitutes the DRAM 121 together with the switch SW11. The capacitance value of the capacitor C11 is set larger than the capacitance value of the liquid crystal LCM. If the data to be newly written supplied via the column data line d is different from the data held in the capacitor C11, the switch SW11 is turned on, and the data held in the capacitor C11 is newly recharged or discharged. The data to be written is rewritten.

  The switch SW11 indicates that the normal row scanning pulse supplied via the normal row scanning line g is at “H” level (in this case, the inverted row scanning pulse supplied via the inverted row scanning line gb is “L”. Level), the data supplied via the column data line d is transferred to the capacitor C11. On the other hand, the switch SW11 indicates that the normal row scanning pulse supplied via the normal row scanning line g is at the “L” level (in this case, the inverted row scanning pulse supplied via the inverted row scanning line gb is “ H ”level), it is turned off, transfer of data supplied via the column data line d to the capacitor C11 is cut off, and writing to the capacitor C11 is not performed.

  Since the switch SW11 has a known transmission gate configuration, the input signal voltage in the range from GND to VDD can be turned on and off. In other words, when the input signal applied to the drains of the NMOS transistor and the PMOS transistor constituting the transmission gate is at the GND side potential ("L" level), the PMOS transistor cannot be turned on. It can conduct with low resistance. On the other hand, when the input signal applied to each drain of the NMOS transistor and the PMOS transistor is at the VDD side potential ("H" level), the NMOS transistor cannot be turned on, but the PMOS transistor is turned on with a low resistance. can do. Therefore, the transmission gate constituting the switch SW11 is turned on / off by the normal row scanning pulse supplied via the normal row scanning line g and the reverse row scanning pulse supplied via the reverse row scanning line gb. Thus, the input signal voltage range from GND to VDD can be switched with low resistance and high resistance.

  The switch SW12 constituting the second switching means has a known transmission gate configuration composed of an NMOS transistor and a PMOS transistor in which the drains are connected to each other and the sources are connected to each other. The gate of the NMOS transistor is connected to the trigger line for normal trigger pulse trig, and the gate of the PMOS transistor is connected to the trigger line for inverted trigger pulse trigb.

  The NMOS transistor and the PMOS transistor constituting the switch SW12 have their drains connected to the non-ground side terminal of the capacitor C11 and their sources connected to the input terminal of the second signal holding means MEM2. Therefore, the switch SW12 is turned on when the normal rotation trigger pulse supplied via the trigger line trig is at “H” level (in this case, the inverted trigger pulse supplied via the trigger line trigb is “L” level). The charge held in the capacitor C11 is read out and transferred to the second signal holding means MEM2. On the other hand, in the switch SW12, the normal rotation trigger pulse supplied via the normal rotation trigger line trig is “L” level (in this case, the reverse trigger pulse supplied via the reverse trigger line trigb is “H” level). Is turned off, the transfer of the charge held in the capacitor C11 to the second signal holding means MEM2 is interrupted, and writing to MEM2 is not performed.

  Since the switch SW12 has a known transmission gate configuration, the input signal voltage in the range from GND to VDD can be turned on and off. In other words, when the input signal applied to the drains of the NMOS transistor and the PMOS transistor constituting the transmission gate is at the GND side potential ("L" level), the PMOS transistor cannot be turned on. It can conduct with low resistance. On the other hand, when the input signal applied to each drain of the NMOS transistor and the PMOS transistor is at the VDD side potential ("H" level), the NMOS transistor cannot be turned on, but the PMOS transistor is turned on with a low resistance. can do. Therefore, by turning on and off the transmission gate constituting the switch SW12 by the normal trigger pulse supplied via the trigger line trig and the reverse trigger pulse supplied via the reverse trigger line trigb, the GND to VDD The voltage range up to can be switched with low resistance and high resistance.

  The second signal holding means MEM2 is a self-holding memory including two inverters INV11 and INV12 having one output terminal connected to the other input terminal. The input terminal of the inverter INV11 is connected to the output terminal of the inverter INV12 and the sources of the NMOS transistor and the PMOS transistor constituting the SW12. The input terminal of the inverter INV12 is connected to the reflective electrode PE1 and the output terminal of the inverter INV11. Each of the inverters INV11 and INV12 has a configuration of a known CMOS inverter including a PMOS transistor PTr and an NMOS transistor NTr in which gates and drains are connected to each other as shown in FIG. However, the two inverters INV11 and INV12 constituting the second signal holding means MEM2 have different driving forces.

  That is, the transistor in the inverter INV11 on the input side that constitutes MEM2 as viewed from the switch SW12 has a driving force that is higher than the transistor in the inverter INV12 on the output side that constitutes MEM2 as viewed from the switch SW12. A large transistor is used. This is because, in the pixel 12, the second signal holding means MEM2 is easy to input data from the capacitor C11 via the switch SW12 and is difficult to input data from the capacitor of the liquid crystal LCM via the reflective electrode PE1. Means having.

  When the switch SW12 is turned on, the charge held in the capacitor C11 drives the input gate of the inverter INV11 and rewrites the data held in the MEM2. Although the output of the inverter INV12 also affects the capacitor C11, the input of the inverter INV12 has only the gate capacitor constituting the INV12 and the liquid crystal capacitor of the liquid crystal LCM, compared with the gate capacitor and the capacitor C11 constituting the input of the inverter INV11. Since the capacity value is remarkably small and the driving force of the inverter INV11 is set larger than that of the inverter INV12, the driving of the inverter INV11 by the capacity C11 is prioritized over the data output of the inverter INV12, and the capacity C11 is retained. It is designed not to rewrite data.

  In addition, the data written in the capacitor C11 is an electric charge charged / discharged from the column data line d, and there is an influence such as gate feedthrough generated at the timing when the NMOS transistor and the PMOS transistor constituting the switch SW11 are turned off. As a result, the potential of the terminal voltage of the capacitor C11 is determined with potential fluctuations, and deviates from the negative power supply potential GND and the positive power supply potential VDD of the NMOS transistor and the PMOS transistor in a direction of decreasing the dynamic range. Become a voltage. However, the voltage finally applied to the reflective electrode PE1 is shaped by turning on and off the transistors constituting the inverters INV11 and INV12 constituting the second signal holding means MEM2, and is accurate GND or VDD without potential fluctuation. Therefore, the dynamic range can be increased.

  In addition, when light hits the diffusion electrode portion of each transistor that constitutes the switches SW11 and SW12 connected to the capacitor C11, a leakage current is generated and the charge held in the capacitor C11 is reduced to reduce the terminal voltage of the capacitor C11. Potential fluctuation occurs. However, the charge held in the capacitor C11 is for driving the second signal holding means MEM2, and the potential fluctuation of the terminal voltage of the capacitor C11 is regarded as “L” level or “H” level with respect to MEM2. If there is no fluctuation exceeding the threshold value, some potential fluctuation does not affect the reflective electrode PE1.

  At this time, the voltage of the reflective electrode PE1 applied to the liquid crystal LCM is supplied from the MEM2. When the applied voltage of the reflective electrode PE1 is at “H” level, the PMOS transistor (Ptr in FIG. 3) of the inverter INV11 constituting the MEM2 is turned on and the power supply voltage VDD is applied. On the other hand, when the applied voltage of the reflective electrode PE1 is at the “L” level, the NMOS transistor (Ntr in FIG. 3) of the inverter INV11 constituting the MEM2 is turned on and the ground voltage GND is applied. For this reason, according to the pixel 12 of the present embodiment, it is possible to apply a stable voltage to the liquid crystal LCM without being affected by the leakage current due to light.

  As described above, the terminal voltage of the capacitor C11 may be slightly changed if the data held in the second signal holding means MEM2 can be rewritten due to charge transfer, gate feedthrough, light leakage current, or the like. There is no problem. That is, according to the liquid crystal display device 10 of the present embodiment, the subframe data applied by the pixel 12 via the column data line d is written to the capacitor C11 in the DRAM 121, and then the subframe data written to the capacitor C11 is written. Since the SRAM 122 is configured to write data, the SRAM 122 only needs to be able to turn on and off the transistor, and thus the terminal voltage of the capacitor C11 may slightly vary. Therefore, the switches SW11 and SW12 do not have to be transmission gates as shown in FIG.

  For example, considering the case where each of the switches SW11 and SW12 is only an NMOS transistor, the “H” voltage of the input signal can only pass up to “VDD−Vth” including the substrate effect (however, Vth is the transistor voltage). Threshold voltage). That is, even if an attempt is made to write the same 3.3 V voltage as VDD to the column data line d, if the switch SW11 is a switch having only an NMOS transistor, the point a which is a connection point between the switch SW11 and the capacitor C11 is “VDD”. −Vth ”or less is 2.5V, and a voltage of 2.5V is accumulated in the capacitor C11. Next, the switch SW12 is turned on to rewrite the data held in the MEM2 to the data held in the capacitor C11. When the SW12 is also only an NMOS transistor, the point b that is a connection point between the SW12 and the MEM2 is the same as the point a. Only 2.5V is applied.

  However, if the voltage at the point b which is also the input point of the MEM2 is 1.VDD which is “VDD / 2” or more, it is written as “H” data in the inverters INV11 and INV12 constituting the MEM2 (the output reflection electrode PE1) "L" data can be written to the memory, and both "H" data and "L" data can be written. When the switches SW11 and SW12 are PMOS transistors, both “H” data and “L” data can be written in the MEM2 only by reversing the voltage range that is not input.

  Thus, the switches SW11 and SW12 may be switches using one MOS transistor instead of the transmission gate shown in FIG. In this case, since the number of transistors constituting one pixel is smaller than that of the pixel configuration of FIG. 2, there is an advantage that further pixel size reduction can be achieved.

  Note that the SRAM 122 outputs subframe data obtained by inverting the polarity of the subframe data input from the capacitor C11 and applies the subframe data to the reflective electrode PE1. However, as described above, the input subframe data supplied to the level shifter / pixel driver 163 via the data latch circuit 15, the horizontal shift register 161, and the latch circuit 162 is output with the polarity inverted by the pixel driver. The subframe data applied from the capacitor C11 to the reflective electrode PE1 through the SRAM 122 is subframe data having the same polarity (same logical value) as the input subframe data.

  As described above, according to the pixel 12 of the present embodiment shown in FIG. 2, not only the effect that the applied voltage of the liquid crystal display element LC can be set high and the dynamic range can be increased, The great effect that the pixel can be miniaturized is obtained. The downsizing of the pixel 12 is made up of a total of eight transistors and one capacitor C11 as shown in FIG. 2, and the number of constituent elements is smaller than that of a pixel using two SRAMs in a conventional pixel. This is because the DRAM 121, the SRAM 122, and the reflective electrode PE1 can be effectively arranged in the height direction of the element as described below.

  FIG. 4 shows a cross-sectional configuration diagram of an embodiment of a pixel of a main part of a liquid crystal display device according to the present invention. In the capacitor C11 shown in FIG. 2, a MIM (Metal-Insulator-Metal) capacitor that forms a capacitor between wirings, a diffusion capacitor that forms a capacitor between a substrate and polysilicon, and a capacitor between two layers of polysilicon are formed. PIP (Poly-Insulator-Poly) capacity can be used. FIG. 4 shows a cross-sectional configuration diagram of the liquid crystal display device when the capacitor C11 is configured by the MIM. FIG. 4 is a partial cross-sectional view of the pixel 12.

  In FIG. 4, the PMOS transistor PTr11 of the inverter INV12 and the PMOS transistor Tr2 of the switch SW12, in which the drains are connected, are formed on the N well 101 formed in the silicon substrate 100 by sharing the diffusion layer as the drain. Has been. Further, on the P-well 102 formed on the silicon substrate 100, an NMOS transistor NTr12 of the inverter INV12 and an NMOS transistor Tr1 of the switch SW12, in which the drains are connected by sharing a diffusion layer serving as a drain, are formed. Yes. Note that FIG. 4 does not show the NMOS transistor, the PMOS transistor, and the switch SW11 that constitute the inverter INV11.

  Further, above each of the transistors PTr11, Tr2, Tr1, and NTr12, an interlayer insulating film 105 is interposed between the metals, and the first metal 106, the second metal 108, the third metal 110, the electrode 112, and the fourth metal. 114 and the fifth metal 116 are laminated. The fifth metal 116 constitutes a reflective electrode PE1 formed for each pixel. The source of the NMOS transistor Tr1 of the switch SW12 is electrically connected to the first metal 106 via the contact 118a, and the source of the PMOS transistor Tr2 of the switch SW12 is electrically connected to the first metal 106 via the contact 118b. Yes. Further, the first metal 106 is electrically connected to the third metal 110 via the through holes 119a and 119b, and is also electrically connected to the third metal 110 via the through holes 119a and 119c. The third metal 110 forms one electrode of the capacitor C11 as will be described later.

  The diffusion layers constituting the drains of the NMOS transistor and PMOS transistor constituting the inverter INV11 (not shown) and the gate electrodes of the NMOS transistor NTr12 and PMOS transistor PTr11 constituting the inverter INV12 are connected to the first metal 106 by a contact (not shown). Are further electrically connected to the second metal 108, the third metal 110, the fourth metal 114, and the fifth metal 116 through the through holes 119a, 119c, 119e, and 119h, respectively. That is, the drains of the NMOS transistor and the PMOS transistor constituting the inverter INV11 (not shown) and the gate electrodes of the NMOS transistor NTr12 and the PMOS transistor PTr11 constituting the inverter INV12 are electrically connected to the reflective electrode PE1 made of the fifth metal 116. It is connected.

  Further, a passivation film (PSV) 117 is formed as a protective film on the reflective electrode PE1 (fifth metal 116), and is disposed so as to face the common electrode CE having a structure in which a transparent electrode (ITO film) is formed on glass. ing. A liquid crystal LCM is filled and sealed between the reflective electrode PE1 and the common electrode CE to form a liquid crystal display element LC. The common electrode CE has a transparent electrode formed on the liquid crystal LCM side.

  Here, the MIM electrode 112 is formed on the third metal 110 via the interlayer insulating film 105. The MIM electrode 112 constitutes a capacitor C 11 together with the third metal 110 and the interlayer insulating film 105 between the third metal 110. The switches SW11 and MEM2 and the switch SW12 can be formed of a transistor and a first and second layer wiring of the first metal 106 and the second metal 108. The MIM electrode 112 is electrically connected to the fourth metal 114 through the through holes 119f and 119g, and is electrically connected to the switches SW11 and SW12 at a place not shown.

  Light from a light source (not shown) passes through the common electrode CE and the liquid crystal LCM, is incident on the reflective electrode PE1 (fifth metal 116), is reflected, and travels backward through the original incident path and is emitted through the common electrode CE. . At this time, the incident light is reflected and emitted with a reflectance corresponding to the absolute value of the voltage applied to the liquid crystal LCM.

  According to the present embodiment, as shown in FIG. 4, by assigning the fifth metal 116, which is a five-layer wiring, to the reflective electrode PE1, the MEM1, the MEM2, and the reflective electrode PE1 that are the capacitors C11 are raised. It becomes possible to arrange them effectively in the direction, and pixel miniaturization can be realized. Thus, for example, pixels with a pitch of 3 μm or less can be configured with transistors having a power supply voltage of 3.3V. With this pixel of 3 μm pitch, a liquid crystal display panel having a diagonal length of 0.55 inches and a horizontal direction of 4000 pixels and a vertical direction of 2000 pixels can be realized.

  Next, the operation of the liquid crystal display device 10 of FIG. 1 using the pixel 12 of the present embodiment will be described with reference to the timing chart of FIG.

  As described above, in the liquid crystal display device 10 of FIG. 1, the first row scanning line g <b> 1 in which the normal row scanning pulse and the reverse row scanning pulse from the vertical shift register 14 are the uppermost in the image display unit 11. And gb1 toward the m-th row scanning lines gm and gbm at the bottom, one set is sequentially supplied in units of 1H, so that m rows and n columns constituting the image display unit 11 are provided. The pixels 12 are selected in units of n pixels in one row commonly connected to a set of row scanning lines, and data is written to each pixel 12 from the first row to the m-th row. Then, after all of the plurality of pixels 12 constituting the image display unit 11 have been written, all the pixels are simultaneously read based on the forward trigger pulse and the reverse trigger pulse.

  FIG. 5A schematically shows a writing period and a reading period of one pixel of 1-bit subframe data output from the horizontal driver 16 to the column data lines d (d1 to dn). A horizontal projection illustrated period with a slanting line to the right indicates a writing period. In FIG. 5A, B0a, B1a, and B2a indicate normal subframe data of bits B0, B1, and B2, and B0b, B1b, and B2b are inverted subframe data of bits BO, B1, and B2. Indicates. FIG. 5B shows a normal trigger pulse output from the timing generator 13 to the normal trigger pulse trigger line trig. This normal rotation trigger pulse is output every subframe. The inversion trigger pulse output to the inversion trigger pulse trigger line trigb is always an inverse logical value with respect to the normal rotation trigger pulse and is not shown.

  First, when the pixel 12 in the first row is selected by the normal row scanning pulse and the reverse row scanning pulse output from the timing generator 13 to the first row normal row scanning line g1 and the reverse row scanning line gb1, The switches SW11 in the n pixels 12 in the first row are respectively turned on, and the normal subframe data B0a of the bit B0 in FIG. 5A output to the column data lines d1 to dn at that time is the level shifter / pixel driver. After the polarity is inverted by the pixel driver 163, the signal is sampled by the switch SW11 and written to each capacitor C11 in the n pixels 12 in the first row. Hereinafter, similarly, the inverted subframe data B0b obtained by reversing the polarity of the normal subframe data B0a of the bit B0 is also written to the capacitor C11 of each pixel 12 from the second row to the mth row constituting the image display unit 11. Is done.

  When the subframe data B0b obtained by reversing the polarity of the normal subframe data B0a of the bit B0 is written in all the pixels 12 constituting the pixel display unit 11 in this way, it is shown in FIG. 5 immediately after the writing operation is completed. At time T1, as shown in FIG. 5B, the “H” level normal trigger pulse is simultaneously supplied to all the pixels 12 constituting the image display unit 11 via the normal trigger pulse trigger line trig. . As a result, the switches SW12 of all the pixels 12 constituting the pixel display unit 11 are turned on, so that the inverted subframe data B0b of the bit B0 held in the capacitors C11 of all the pixels 12 is transferred to the MEM2 through the switch SW12. After being transferred and held all at once, the polarity is inverted again to return to the normal rotation normal subframe data B0a and applied to the reflective electrode PE1. The subframe data holding period of bit B0 by the capacitor C11 is one subframe period from time T1 to time T2 when the next “H” normal rotation trigger pulse is input as shown in FIG. 5B. It is. FIG. 5C schematically shows subframe data applied to the reflective electrode PE1.

  Here, when the bit value of the subframe data is “1”, that is, “H” level, the power supply voltage VDD (3.3 V here) is applied to the reflective electrode PE1, and the bit value is “0”, that is, “L”. At the “level”, 0 V is applied to the reflective electrode PE1. On the other hand, a free voltage can be applied to the common electrode CE of the liquid crystal display element LC as the common electrode voltage Vcom without being limited to GND or VDD. The voltage is switched to the specified voltage at the same time as the input. Here, the common electrode voltage Vcom is set to a voltage lower than 0V by the threshold voltage Vtt of the liquid crystal during the subframe period in which the normal rotation subframe data is applied to the reflective electrode PE1, as shown in FIG. The

  The liquid crystal display element LC performs gradation display according to the applied voltage of the liquid crystal LCM, which is the absolute value of the difference voltage between the applied voltage of the reflective electrode PE1 and the common electrode voltage Vcom. Therefore, during one subframe period from time T1 to time T2 when the normal rotation subframe data B0a of the bit B0 is applied to the reflective electrode PE1, the voltage applied to the liquid crystal LCM is when the bit value of the subframe data is “1”. 3.3V + Vtt (= 3.3V − (− Vtt)). When the bit value of the subframe data is “0”, + Vtt (= 0V − (− Vtt)).

  FIG. 6 shows the relationship between the applied voltage (RMS voltage) of the liquid crystal and the gray scale value of the liquid crystal. As shown in FIG. 6, in the gray scale value curve, the black gray scale value corresponds to the RMS voltage of the liquid crystal threshold voltage Vtt, and the white gray scale value represents the RMS voltage of the liquid crystal saturation voltage Vsat (= 3.3 V + Vtt). Shifted to correspond to. It is possible to match the gray scale value to the effective part of the liquid crystal response curve. Therefore, the liquid crystal display element LC displays white when the applied voltage of the liquid crystal LCM is (3.3 V + Vtt) as described above, and displays black when it is + Vtt.

  Subsequently, within the subframe period from time T1 to time T2 when the normal subframe data of the bit B0 is displayed, the bit B0 of FIG. The inverted subframe data B0b is input and writing to the pixels 12 is started in order. At this time, the subframe data B0a obtained by reversing the polarity of the inverted subframe data B0b of the bit B0 is written in all the pixels 12 constituting the pixel display unit 11.

  At time T2 shown in FIG. 5 immediately after the end of the writing operation, as shown in FIG. 5B, the normal rotation trigger pulse of “H” level is transmitted through the normal trigger pulse trigger line trig. Are simultaneously supplied to all the pixels 12 constituting the. As a result, the switches SW12 of all the pixels 12 constituting the pixel display unit 11 are turned on, so that the normal subframe data B0a of the bit B0 held in the capacitors C11 of all the pixels 12 is transmitted to the MEM2 through the switch SW12. Then, the polarity is inverted again and returned to the inverted polarity subframe data B0b of the original polarity as shown in FIG. 5C and applied to the reflective electrode PE1. The subframe data holding period of bit B0 by the capacitor C11 is one subframe period from time T2 to time T3 when the next “H” normal rotation trigger pulse is input as shown in FIG. 5B. It is.

  As described above, when the bit value of the subframe data is “1”, that is, “H” level, the power supply voltage VDD (3.3 V in this case) is applied to the reflective electrode PE1, and the bit value is “0”, that is, “ At the L ″ level, 0 V is applied to the reflective electrode PE1. On the other hand, the common electrode voltage Vcom is set to a voltage higher than the 3.3V threshold voltage Vtt during the subframe period in which the inverted subframe data is applied to the reflective electrode PE1, as shown in FIG. The Therefore, during one subframe period from time T2 to time T3 when the inverted subframe data B0b of the bit B0 is applied to the reflective electrode PE1, the applied voltage of the liquid crystal LCM is as follows when the bit value of the subframe data B0b is “1”. −Vtt (= 3.3 V− (3.3 V + Vtt)), and −3.3 V−Vtt (= 0 V− (3.3 V + Vtt)) when the bit value of the subframe data B0b is “0”.

  Here, since the inverted subframe data B0b of bit B0 is always in the relationship of the inverse logical value with the normal subframe data B0a of bit B0 inputted one subframe before, the bit B0 inputted one subframe before is used. When the normal rotation subframe data B0a is “1”, it is “0”, and when the normal rotation subframe data B0a is “0”, it is “1”. Therefore, when the bit value of the normal subframe data B0a of the bit B0 is “1”, the bit value of the inverted subframe data B0b of the bit B0 input subsequently after one subframe period is “0”. Therefore, the applied voltage of the liquid crystal LCM is − (3.3 V + Vtt).

  That is, the applied voltage of the liquid crystal LCM is (3.3V + Vtt) when the bit value of the normal subframe data B0a of the bit B0 is “1”, whereas the bit value “0” input subsequently is “0”. "-(3.3V + Vtt)" when the inverted subframe data B0b of the bit B0 is applied, and the direction of the potential of the voltage applied to the liquid crystal LCM is opposite to that of the normal subframe data B0a of the bit B0, but the absolute value. Are the same. For this reason, the pixel 12 displays the same white color as that when the normal rotation subframe data B0a of the bit B0 is displayed.

  Similarly, when the bit value of the normal subframe data B0a of the bit B0 is “0”, the applied voltage of the liquid crystal LCM is + Vtt, and the inverted subframe of the bit B0 input subsequently after one subframe period. Since the bit value of the data B0b is “1”, the applied voltage of the liquid crystal LCM is −Vtt. Therefore, in this case as well, the direction of the potential of the voltage applied to the liquid crystal LCM is opposite between when the forward subframe data B0a is applied and when the reverse subframe data B0b is applied, but the absolute value is the same | Vtt |. The pixel 12 displays black.

  Accordingly, as indicated by B0 in FIG. 5E, the pixel 12 has the bit B0 of the normal subframe data B0a and the inverted subframe data B0b of the bit B0 during the two subframe periods from the time T1 to the time T3. Since the same gradation is displayed and AC driving is performed in which the potential direction of the applied voltage of the liquid crystal LCM is reversed for each subframe, the burn-in of the liquid crystal LCM can be prevented.

  Subsequently, within one subframe period from time T2 to time T3 during which the inverted subframe data B0b of the bit B0 is displayed, the bit B1 as schematically shown by the diagonally downward slanting line in FIG. The normal rotation subframe data B1a is input, and writing to the pixels 12 is started in order. At this time, the subframe data B1b obtained by reversing the polarity of the normal subframe data B1a of the bit B1 is written to all the pixels 12 constituting the pixel display unit 11.

  At time T3 shown in FIG. 5 immediately after the end of the writing operation, as shown in FIG. 5B, the normal rotation trigger pulse of “H” level is transferred to the image display section 11 via the normal trigger pulse trigger line trig. Are simultaneously supplied to all the pixels 12 constituting the. As a result, the switches SW12 of all the pixels 12 constituting the pixel display unit 11 are turned on, so that the inverted subframe data B1b of the bit B1 held in the capacitors C11 of all the pixels 12 is transferred to the MEM2 through the switch SW12. After being transferred and held all at once, the polarity is inverted again and returned to normal rotation subframe data B1a of the original polarity as shown in FIG. 5C and applied to the reflective electrode PE1. The subframe data holding period of bit B1 by the capacitor C11 is one subframe period from time T3 to time T4 when the next "H" level normal rotation trigger pulse is input as shown in FIG. 5B. It is.

  As described above, when the bit value of the subframe data is “1”, that is, “H” level, the power supply voltage VDD (3.3 V in this case) is applied to the reflective electrode PE1, and the bit value is “0”, that is, “ At the L ″ level, 0 V is applied to the reflective electrode PE1. On the other hand, the common electrode voltage Vcom is set to a voltage lower than 0V by the threshold voltage Vtt of the liquid crystal as shown in FIG. 5D during the subframe period in which the normal rotation subframe data is applied to the reflective electrode PE1. .

  Therefore, during one subframe period from time T3 to time T4 when the normal rotation subframe data B1a of the bit B1 is applied to the reflective electrode PE1, the voltage applied to the liquid crystal LCM is when the bit value of the subframe data B1a is “1”. The voltage applied to the liquid crystal LCM is 3.3 V + Vtt (= 3.3 V − (− Vtt)) when the bit value of the subframe data is “1”, and when the bit value of the subframe data is “0”. + Vtt (= 0 V − (− Vtt)).

  Subsequently, within the subframe period from time T3 to time T4 when the normal subframe data of bit B1 is displayed, the bit B1 of FIG. The inverted subframe data B1b is input and writing to the pixel 12 is started in order. At this time, the subframe data B1a obtained by reversing the polarity of the inverted subframe data B1b of the bit B1 is written in all the pixels 12 constituting the pixel display unit 11.

  At time T4 shown in FIG. 5 immediately after the end of the writing operation, as shown in FIG. 5 (B), the “H” level normal rotation trigger pulse is transmitted via the normal rotation trigger pulse trigger line trig. Are simultaneously supplied to all the pixels 12 constituting the. As a result, the switches SW12 of all the pixels 12 constituting the pixel display unit 11 are turned on, so that the normal subframe data B1a of the bit B1 held in the capacitors C11 of all the pixels 12 passes through the switch SW12 and MEM2 Then, the polarity is inverted again and returned to the original polarity inversion subframe data B1b as shown in FIG. 5C and applied to the reflective electrode PE1. The holding period of the subframe data of bit B1 by the capacitor C11 is one subframe period from time T4 to time T5 when the next “H” normal rotation trigger pulse is input as shown in FIG. 5B. It is.

  As described above, when the bit value of the subframe data is “1”, that is, “H” level, the power supply voltage VDD (3.3 V in this case) is applied to the reflective electrode PE1, and the bit value is “0”, that is, “ At the L ″ level, 0 V is applied to the reflective electrode PE1. On the other hand, the common electrode voltage Vcom is set to a voltage higher than the 3.3V threshold voltage Vtt during the subframe period in which the inverted subframe data is applied to the reflective electrode PE1, as shown in FIG. The Accordingly, during one subframe period from time T4 to T5 when the inverted subframe data B1b of the bit B1 is applied to the reflective electrode PE1, the voltage applied to the liquid crystal LCM is when the bit value of the subframe data B1b is “1”. −Vtt (= 3.3V− (3.3V + Vtt)), and when the bit value of the subframe data B1b is “0”, −3.3V−Vtt (= 0V− (3.3V + Vtt)).

  Here, the inverted subframe data B1b of the bit B1 is always in a reverse logical value with the normal subframe data B1a of the bit B1 input one subframe before, so the bit B1 input one subframe before When the normal rotation subframe data B1a is “1”, it is “0”, and when the normal rotation subframe data B1a is “0”, it is “1”. Therefore, when the bit value of the normal subframe data B1a of the bit B1 is “1”, the bit value of the inverted subframe data B1b of the bit B1 that is input subsequently after one subframe period is “0”. Therefore, the applied voltage of the liquid crystal LCM is − (3.3 V + Vtt).

  That is, the applied voltage of the liquid crystal LCM is (3.3 V + Vtt) when the bit value of the normal subframe data B1a of the bit B1 is “1”, whereas the bit value “0” that is subsequently input is “0”. When the inverted subframe data B1b of the bit B1 is applied, − (3.3V + Vtt) is applied, and the direction of the potential of the voltage applied to the liquid crystal LCM is opposite to that of the normal subframe data B1a of the bit B1, but the absolute value. Are the same. For this reason, the pixel 12 displays the same white as when the normal rotation subframe data B1a of the bit B1 is displayed.

  Similarly, when the bit value of the normal subframe data B1a of the bit B1 is “0”, the applied voltage of the liquid crystal LCM is + Vtt, and the inverted subframe of the bit B1 that is subsequently input after one subframe period. Since the bit value of the data B1b is “1”, the applied voltage of the liquid crystal LCM is −Vtt. Accordingly, in this case as well, the direction of the potential of the voltage applied to the liquid crystal LCM is opposite to that when the forward subframe data B1a is applied and when the reverse subframe data B1b is applied, but the absolute value is the same | Vtt |. The pixel 12 displays black.

  Therefore, as indicated by B1 in FIG. 5E, the pixel 12 has the bit B1 in the normal subframe data B1a and the inverted subframe data B1b in the bit B1 during the two subframe periods from the time T3 to the time T5. Since the same gradation is displayed and AC driving is performed in which the potential direction of the applied voltage of the liquid crystal LCM is reversed for each subframe, the burn-in of the liquid crystal LCM can be prevented.

  Thereafter, the same operation as described above is repeated, and according to the liquid crystal display device 10 having the pixel 12 of the present embodiment, gradation display can be performed by a combination of a plurality of subframes.

  The display periods of the normal subframe data B0a and the inverted subframe data B0b of the bit B0 are the same first subframe period, and the normal subframe data B1a and the inverted subframe data B1b of the bit B are the same. Each display period is the same second subframe period, but the first subframe period and the second subframe period are not necessarily the same. Here, as an example, the second subframe period is set to be twice the first subframe period. Further, as shown in FIG. 5E, the third subframe period, which is the display period of each of the normal subframe data B2a and the inverted subframe data B2b of bit B2, is twice the second subframe period. Is set to The same applies to the other subframe periods. The length of each subframe period is determined to be a predetermined length according to the system, and the number of subframes is also determined to be an arbitrary number.

  The present invention is not limited to the above embodiment. For example, the pixel electrode has been described as a reflective electrode, but may be a transmissive electrode.

DESCRIPTION OF SYMBOLS 10 Liquid crystal display device 11 Image display part 12 Pixel 13 Timing generator 14 Vertical shift register 15 Data latch circuit 16 Horizontal driver 121 Dynamic random access memory (DRAM)
122 Static random access memory (SRAM)
161 Horizontal shift register 162 Latch circuit 163 Level shifter / pixel driver MEM1 First signal holding means MEM2 Second signal holding means d, d1 to dn column data lines
g1a to gma Normal rotation scanning line
g1b to g1m Inverted row scanning line
trig Forward trigger pulse trigger line
trigb Inversion trigger pulse trigger line LC Liquid crystal display element LCM Liquid crystal PE1 Reflective electrode CE Common electrode C11 Capacitance INV11, INV12 Inverter Tr1, NTr, NTr12 N-channel MOS transistor (NMOS transistor)
Tr2, PTr, PTr11 P-channel MOS transistor (PMOS transistor)

Claims (5)

An image display unit composed of a plurality of pixels provided at intersections where a plurality of column data lines and a plurality of row scanning lines respectively intersect;
Pixel control means for controlling the plurality of pixels constituting the image display unit,
Each of the plurality of pixels is
A display element in which liquid crystal is filled and sealed between the opposing pixel electrode and the common electrode;
First switching means for sampling each subframe data for displaying each frame of the video signal in a plurality of subframes having a display period shorter than one frame period of the video signal via the column data line;
A first signal holding means for constituting a random access memory together with the first switching means, and for updating and storing the subframe data sampled by the first switching means;
Second switching means for outputting the subframe data stored in the first signal holding means;
A static random access memory is configured together with the second switching means, and the stored contents are rewritten with the subframe data stored in the first signal holding means supplied through the second switching means. And a second signal holding means for applying output data to the pixel electrode. The first signal holding means is constituted by a capacitor,
The second signal holding means is composed of a self-holding memory composed of first and second inverters whose output terminals are connected to the other input terminal, and the input terminal of the first inverter is the The second switching means is connected to the output terminal of the second inverter, and the output terminal of the first inverter is connected to the input terminal of the second inverter and the pixel electrode. The liquid crystal display device according to claim 1.   3. The liquid crystal display device according to claim 2, wherein the capacitance value is set to a value larger than the capacitance value of the liquid crystal.   The first transistor constituting the first inverter is set to have a driving force larger than that of the second transistor constituting the second inverter. Liquid crystal display device. The subframe data to be displayed in the plurality of subframes is subframe data of a plurality of bits corresponding to the plurality of subframes, and the subframe data of each bit is alternately changed for each subframe period. It consists of normal subframe data and reverse subframe data which are supplied to the first switching means via column data lines and have a relationship of opposite logical values to each other,
The pixel control means outputs a first subframe period in which the normal subframe data stored and held in the second signal holding means is output from the second signal holding means and applied to the pixel electrode. The inverted subframe data stored and held in the second signal holding means is output from the second signal holding means and applied to the pixel electrode at a predetermined first value related to the threshold voltage of the liquid crystal. The second subframe period is synchronized with the switching input of the normal subframe data and the inverted subframe data to the pixel electrode so that the second subframe period becomes a second value larger than the first value. The liquid crystal display device according to claim 1, wherein a common voltage whose value is switched is applied to the common electrode.