JP2001125528A - Driving method and driving circuit for electrooptical device and electrooptical device and eletronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform assigning intensity levels of high quality by binarizing a signal to be applied to a data line. SOLUTION: A data converting circuit 300 generates a binary signal Ds instructing the applying of a signal turning respective pixels 100 ON or a signal turning them OFF in each subfield of plural pieces of subfields in which one field is divided. A data driving circuit 140 receives this binary signal Ds and applies a voltage turning the pixels ON or a voltage turning them OFF to the respective pixels for every subfield in which one field is divided also it is provided with two kinds or more of voltage values of the voltage turning them ON and it performs weightings for every subfield by these voltage values. As a result, the priod of the minimum subfield can be maintained for a long time and binary signals to be applied to pixels can be written surely. Moreover, since on OFF voltage applying period is provided between subfields in which voltage values of the voltage turning the pixels ON are to be changed over, the changing over of the voltage values is performed after the applying of the voltage to the respective pixels is completed in a previous subfield.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving method, a driving circuit, an electro-optical device, and an electronic apparatus for an electro-optical device which performs gradation display control by pulse width modulation.

[0002]

2. Description of the Related Art An electro-optical device, for example, a liquid crystal display device using liquid crystal as an electro-optical material is a cathode ray tube (CRT).
It is widely used as a display device in place of a display unit of various information processing equipment and a liquid crystal television.

Here, the electro-optical device according to the prior art is
For example, it is configured as follows. That is, the conventional electro-optical device includes a pixel electrode arranged in a matrix and a TFT (Thin Film Transistor: TFT) connected to the pixel electrode.
A switching element such as a thin film transistor), a counter substrate on which a counter electrode facing the pixel electrode is formed, and a liquid crystal as an electro-optical material filled between the two substrates. You. In such a configuration, when a scanning signal is applied to a switching element via a scanning line, the switching element is turned on. In this conductive state, when an image signal of a voltage corresponding to the gradation level is applied to the pixel electrode via the data line, a charge corresponding to the voltage of the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode. Is accumulated. After the charge storage, even if the switching element is turned off, the charge storage in the liquid crystal layer is maintained by the capacitance of the liquid crystal layer itself, the storage capacitance, and the like. As described above, when each switching element is driven and the amount of charge to be stored is controlled in accordance with the gradation level, the alignment state of the liquid crystal changes for each pixel.
The density changes for each pixel. Therefore, the liquid crystal display device can perform gradation display.

At this time, since it is sufficient for the electric charges to be accumulated in the liquid crystal layer of each pixel during a part of the period, first, each scanning line is sequentially selected by the scanning line driving circuit, and secondly, the scanning is performed. In the line selection period, the data lines are sequentially selected by the data line driving circuit, and thirdly, the scanning lines and the data lines are constituted by sampling an image signal of a voltage corresponding to the gradation level to the selected data line. Is common to a plurality of pixels, thereby enabling time-division multiplex driving.

[0005]

However, in the liquid crystal display device according to the prior art, the image signal applied to the data line corresponding to the gradation level is an analog signal. Therefore, a peripheral circuit of the electro-optical device requires an electric circuit such as a D / A conversion circuit and an operational amplifier, which leads to an increase in the cost of the entire device. Furthermore, display non-uniformity occurs due to the characteristics of the D / A conversion circuit and the operational amplifier and the non-uniformity of various wiring resistances, so that high-quality display is extremely difficult. Yes, especially when high definition display is performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide an electro-optical device capable of high-quality and high-definition gray scale display, a driving method thereof, a driving circuit thereof, and Another object of the present invention is to provide an electronic apparatus using the electro-optical device.

[0007]

In order to achieve the above object, a first aspect of the present invention is to receive, on a field-by-field basis, gradation data of each pixel for one screen, and to determine each pixel based on the gradation data. What is claimed is: 1. A method for driving an electro-optical device that is turned on and off, wherein the method satisfies the following requirements. a. The field is divided into a plurality of subfields, and a voltage for turning on each pixel or a voltage for turning off each pixel is applied to each pixel in subfield units. b. Two or more voltage values for turning on the pixel are provided. c. The switching of the voltage value when shifting the subfield is performed after the voltage application to each pixel in the previous subfield is completed.

According to the first aspect, in one field, the application period of the signal for turning on (off) the pixel is:
As a result of pulse width modulation according to the gradation data of the pixel, gradation display is performed by controlling the effective voltage value. In this case, in each subfield, it is only necessary to instruct ON or OFF of the pixel, so that a binary signal can be used as an instruction signal to the pixel. Therefore, in the present invention, since the signal applied to the pixel is a digital signal, display unevenness due to non-uniformity such as element characteristics and wiring resistance is suppressed, and high-quality and high-definition gradation display can be performed. Become.

Further, in the present invention, since two or more types of voltage values for turning on the pixels in the subfield are provided, the number of subfields is reduced as compared with the case where the voltage value of the subfield is set to one value. It is possible to reduce the number of subfields, and it is possible to secure a relatively long period even for a subfield in the minimum period. As a result, the data signal corresponding to the gradation level can be reliably written into each pixel, and the gradation display control by the electro-optical device can be performed accurately.

Further, according to the present invention, the switching of the voltage value when shifting the subfield is performed after the voltage application to each pixel in the previous subfield is completed. During the application of the voltage to the sub-field, the switching of the voltage value is prevented, and the effective voltage of the voltage for turning on the pixel determined for each subfield is prevented from fluctuating.

In addition, even when high gradation display is performed, data writing time to pixels can be secured for each subfield, and high gradation display can be realized.

In the present invention, one field is used in the meaning of a period required for forming one raster image by performing horizontal scanning and vertical scanning in synchronization with a horizontal scanning signal and a vertical scanning signal. ing. Therefore, even one frame in the non-interlace method or the like,
Note that this corresponds to one field according to the invention.

According to a first aspect of the present invention, when the voltage for turning on the pixel is switched with the transition from the previous subfield to the next subfield, the voltage application from the previous subfield to the next subfield is terminated. It is preferable that a voltage for turning off the pixel is applied to each pixel until the start of voltage application in the subfield.

In such an embodiment, a voltage for turning off the pixel is applied to each pixel from the end of the voltage application in the previous subfield to the start of the voltage application in the next subfield, so that the voltage is turned on for each subfield. It is possible to prevent the effective voltage of the voltage for turning on the pixel based on the gradation data from fluctuating.

According to a second aspect of the present invention, gray scale data of each pixel for one screen is received for each field, and based on the gray scale data, each intersection of a plurality of data lines and a plurality of scanning lines is detected. A driving circuit of an electro-optical device that drives each of the correspondingly arranged pixels, wherein in each of a plurality of subfields obtained by dividing one field, a voltage for turning on or off a pixel is applied. A data conversion circuit for generating an instructed binary signal based on gradation data, and a scanning signal for enabling a voltage to be applied from a data line to a pixel for each of the subfields, sequentially supplied to each of the scanning lines And a voltage for turning on or off the pixel based on a binary signal generated by the data conversion circuit while the scan signal is supplied to the scan line. A data line driving circuit for supplying a data signal to the data line, a voltage switching circuit for switching a voltage for turning on the pixel, and a voltage switching circuit for switching the subfield when the voltage is switched by the voltage switching circuit. In each scanning line, a voltage for turning off the pixel is applied from the end of voltage application to each pixel on the scanning line in the previous subfield until the scanning signal in the next subfield is supplied to the scanning line. And a data signal switching circuit for forcibly applying a data signal to the plurality of data lines.

According to the second aspect of the invention, the first aspect of the invention is embodied as a driving circuit for an electro-optical device, and has the same effects as the first aspect of the invention.

Next, a third aspect of the invention is an electro-optical device having a plurality of pixels arranged corresponding to intersections of a plurality of scanning lines and a plurality of data lines, wherein one field is divided. In each of the plurality of sub-fields, a data conversion circuit for generating a binary signal instructing application of a voltage for turning on or off a pixel based on gradation data, and a data conversion circuit for each of the sub-fields. A scanning line driving circuit that sequentially supplies a scanning signal to each of the scanning lines to enable application of a voltage from a line to a pixel, and a scanning signal that is generated by the data conversion circuit while the scanning signal is supplied to the scanning line. A data line driving circuit for supplying a data signal for applying a voltage for turning on or off the pixel based on a binary signal to the data line, and a voltage for turning on the pixel; In the case where the voltage is switched by the voltage switching circuit and the voltage switching circuit at the time of shifting the subfield, when the voltage application to each pixel on the scanning line in the previous subfield is completed in each scanning line, the next switching is performed. A data signal switching circuit for forcibly applying a data signal for applying a voltage to turn off the pixel to the plurality of data lines until a scan signal in the subfield is supplied to the scan line. An electro-optical device is provided.

The third invention is an embodiment of the first invention as an electro-optical device, and has the same effects as the first invention.

In the third aspect of the invention, the pixel includes a pixel electrode, a counter electrode facing the pixel electrode,
An electro-optic material sandwiched between the pixel electrode and the counter electrode, a memory for storing a data signal supplied via the data line by receiving a scan signal via the scan line, and a memory for storing the data in the memory A selection circuit that selects one of a voltage for turning on the pixel and a voltage for turning off the pixel and applies the selected voltage to the pixel electrode,
It is provided with.

In the electro-optical device according to the present invention,
It is preferable that the level of the binary signal is inverted according to a level applied to the counter electrode.

With such a configuration, the voltage applied to the pixel can be converted into an alternating voltage, and the deterioration of image quality can be prevented.

The present invention can be embodied in a form in which the electro-optical device itself is manufactured or sold as a single unit, or in which the electro-optical device is manufactured or sold as an electronic device provided as a display device.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. First, the electro-optical device according to the present embodiment is a liquid crystal device using liquid crystal as an electro-optical material, and an element substrate and a counter substrate are adhered to each other with a constant gap therebetween, as described later, The liquid crystal as the electro-optical material is sandwiched. Further, in the electro-optical device according to the present embodiment, a semiconductor substrate is used as an element substrate, and a peripheral driving circuit and the like are formed here together with a transistor for driving a pixel.

<Method of Driving Electro-Optical Device in the Present Embodiment> First, a method of driving the electro-optical device according to the present embodiment will be described to facilitate understanding of the device according to the present embodiment.

In general, in a liquid crystal device using liquid crystal as an electro-optical material, the relationship between the voltage applied to the liquid crystal layer and the transmittance (or reflectance) is such that a normally black mode in which black display is performed in the absence of a voltage is applied. For example,
The relationship is as shown in FIG. That is, as the applied voltage to the liquid crystal layer increases, the transmittance increases nonlinearly and saturates. Here, the transmittance is a value obtained by normalizing the minimum value and the maximum value of the transmitted light amount as 0% and 100%, respectively.

Here, it is assumed that the electro-optical device according to the present embodiment performs 16-gradation display, and that gradation (shading) data represented by 4 bits indicates the transmittance shown in FIG. I do. At this time, assuming that the voltages applied to the liquid crystal layer at the respective transmittances are V0 to V15, these voltages V0 to V15 themselves are conventionally applied to the liquid crystal layer. For this reason, in particular, the voltages V1 to V14 corresponding to the intermediate gradations are not applied across the pixels due to the characteristics of analog circuits such as a D / A conversion circuit and an operational amplifier, and the effects of variations in various wiring resistances. It is easy to be uniform. Therefore, with the conventional configuration, it is difficult to display high-quality and high-definition gradations.

Therefore, in this embodiment, a voltage is applied to the liquid crystal layer as follows.

(1) One field is divided into a plurality of subfields, and a voltage is applied to the liquid crystal layer for each subfield.

The voltage applied to the liquid crystal layer in each subfield is one of two types, Von and Voff. Here, the voltage Von is a voltage that turns on the pixel, that is, a voltage that can contribute to increasing the transmittance of the liquid crystal layer. The voltage Voff is a voltage that turns off the pixel, that is, a voltage that does not contribute to increasing the transmittance of the liquid crystal layer at all.

(2) In which subfield the voltage is applied is determined by the gradation data corresponding to the pixel.

The extent to which the voltage Von contributes to the increase in the transmittance of the liquid crystal layer depends on the application time. Therefore, the subfield to which the voltage Von is applied is selected according to the grayscale data. When the grayscale data is small, the application time of the voltage Von is shortened, the effective applied voltage to the liquid crystal layer is reduced, and the grayscale data is reduced. If the data is large, the application time of the voltage Von is lengthened to increase the effective applied voltage to the liquid crystal layer.

(3) When one field is divided into a plurality of subfields, the length of each subfield may be made non-uniform.

That is, a subfield having a long time length and in which the application of the voltage Von greatly contributes to the increase in the liquid crystal transmittance, and a short time period in which the application of the voltage Von contributes to the increase in the liquid crystal transmittance. A small subfield may be provided. In this case, the length of each subfield may be made to correspond to the weight of each bit of the gradation data.

(4) The voltage Von has a lower voltage value in some subfields than in other subfields.

This is to avoid the problem of insufficient data writing time which occurs when performing multi-tone display. That is, it is as follows.

When a method of controlling the level of the gradation by the length of the application time as in the present embodiment is employed, in order to change the gradation in a fine step width, a subfield having a very short time length is required. Must be provided.

However, in an electro-optical device such as a liquid crystal panel, a voltage Von or Vof is applied to a large number of pixels arranged in rows and columns.
The image is displayed by giving f, and it takes a certain amount of time to apply the voltage to all the pixels. If the subfield is too short, it becomes impossible to apply voltages to all the pixels during the subfield. As described above, since there is a limit to shortening the subfield, it is difficult to realize high gradation display only by shortening the time length of the subfield.

Therefore, in the present embodiment, when providing a subfield having a low contribution to the information on the transmittance of the liquid crystal, the voltage Von in that subfield is set to a voltage value lower than that of the other subfields, and instead, The time length of the subfield is made longer than the original time length (that is, the time length when the same voltage Von as in the other subfields is used).

Specifically, in the present embodiment, the voltage value Vc in FIG. 5 is applied as the voltage Von in the subfield corresponding to the upper bit of the gradation data, but the voltage value Va is applied in the subfield corresponding to the lower bit. Alternatively, Vb is applied as the voltage Von. The voltage Voff uses V0 (= 0 V) in any subfield.

The voltage Von is not limited to three types,
The number of types may be four or more.

(5) An off-voltage application period fx is provided when the voltage value of the voltage Von switches.

That is, the writing of the data signal to each pixel is performed as follows.
Since the data signal is supplied to the data line while the scanning signal is sequentially supplied for each scanning line, writing to each pixel is performed for each scanning line. Therefore, by providing the off-voltage application period fx, it is possible to end the voltage application to each pixel in the previous subfield and switch the voltage value.
The value can be set to a value corresponding to the gradation data. The reason will be described later in detail.

<Electrical Configuration> Next, the electrical configuration of the electro-optical device according to the present embodiment will be described. FIG.
2 shows the configuration of a circuit formed on the element substrate.

As shown in FIG. 1, in the display area 101a on the element substrate, for example, m scanning lines 112
(N) data lines 114 formed in the (row) direction.
a, 114b are formed extending along the Y (column) direction, and m Von lines 113a and Voff lines 113 are formed.
b is formed extending in the X (row) direction. And
The pixel 110 includes a scanning line 112 and a pair of data lines 114.
a, 114b (hereinafter referred to as data line 1 for convenience of description).
14) and are arranged in a matrix.

Each data line 114a and data line 11
4b are connected to inverters 115, respectively.
One data line 114a has a data signal dj, and the other data line 114b has a data signal / dj having an inverted level.
Is entered. Further, a voltage switching circuit 160 that receives the scanning signal Gi output from the scanning line driving circuit 130 and switches the voltage value of the voltage Von to Va, Vb, and Vc is connected to each Von line 113a.

In this embodiment, for convenience of explanation, the scanning line 1
12 is m, and the total number of data lines 114 is n.
As a book (m and n are each an integer of 2 or more), m rows × n
Although described as a matrix display device with columns, the present invention is not limited to this.

A specific configuration of the pixel 110 is, for example, the one shown in FIG.

In this configuration, a memory for storing a 1-bit digital signal in the pixel itself and a circuit for selecting a voltage Von or Voff in accordance with the digital signal stored in the memory and applying the selected voltage to the pixel electrode are provided. ing.

In the pixel 110, as shown in FIG. 2, one output terminal is connected to the other input terminal by the inverters 121 and 122 to form a one-bit memory as a whole.

The transistors 116a and 116b are
A switching transistor that is turned on when writing is performed on the one-bit memory, each drain is connected to each output terminal of the inverters 121 and 122, and each gate is connected to the scanning signal Gk (k = 1). ~
m) or scan lines 112 supplying G1, G2,.
It is connected to the.

In this embodiment, two data lines 114a
And 114b are wired to each pixel, the data line 114a is connected to the source of the transistor 116a, and the data line 114b is connected to the source of the transistor 116b. The data signal 114 is supplied to the data line 114a from the data line driving circuit 140 described later.
j (j = 1 to n) is output as it is and the data line 114
The signal b whose level is inverted is output to b. The signal on each of these data lines is
Inverters 121 and 1 via 6a and 116b
22 and is written to this memory. The transmission gate 123 has an input terminal connected to the Von line 113a that supplies the voltage Von,
The output terminal is connected to the pixel electrode 118. The transmission gate 124 has an input terminal connected to the voltage Voff.
And an output terminal thereof is connected to the pixel electrode 118. These transmission gates 123 and 124 are both H
These gates are turned on when a level gate signal is applied, and output signals of the inverters 121 and 122 in the memory are supplied as gate signals to these gates. Further, the pixel electrode 118 and the counter electrode 108
And a liquid crystal layer 105, which is an electro-optical material, is sandwiched between the two electrodes to form a liquid crystal layer.
COM.

In FIG. 1, a timing signal generation circuit 2
00 denotes a vertical scanning signal Vs, a horizontal scanning signal Hs, and a dot clock signal DC supplied from a higher-level device (not shown).
This is an apparatus that generates various timing signals and clock signals based on the LK. The main signals among the signals generated by the timing signal generation circuit 200 are as follows.

A. Alternating drive logic signal FR The alternating drive logic signal FR specifies the H level and the L level of an alternating drive signal LCOM described later.

B. Alternating drive signal LCOM This alternating drive signal LCOM is applied to the opposite electrode 1 of the opposite substrate.
08 (see FIG. 2). In the present embodiment, the AC drive signal LCOM changes from VCC (H level) to V0
(L level), from L level to H level, and so on, the level inversion is repeated for each field. The AC drive signal LCOM is delayed from the AC drive logic signal FR by one clock of the latch pulse LP.

C. Start pulse DY This start pulse DY is a pulse signal output at the beginning of a subfield. In this embodiment, one field is divided into four to provide subfields Sf0 to Sf3. Therefore, the start pulse signal DY is output at the beginning of each of these subfields.

D. Stop pulse DYres This stop pulse DYres is a pulse signal that is output first when a subfield is switched to an off-voltage application period fx described later.

E. Clock Signal CLY This clock signal CLY is a signal that defines a horizontal scanning period on the scanning side (Y side).

F. Latch Pulse LP The latch pulse LP is a pulse signal output at the beginning of the horizontal scanning period, and is output when the level of the clock signal CLY changes (that is, rises and falls).

G. Clock signal CLX This clock signal CLX is a signal defined by a so-called dot clock.

H. Reset signal RES This reset signal RES is a pulse signal output in synchronization with the latch pulse LP, and is an off-voltage application period f
This signal defines the start of x. That is, the reset signal R
When ES changes from H level to L level, the scanning signal G1 in the first row is set to the off voltage, and when ES changes from L level to H level, the scanning signal Gm in the mth row is set to the off voltage.

The outline of the main signals generated by the timing signal generation circuit 200 has been described above.

In FIG. 1, the scanning line driving circuit 130
A so-called Y shift register transfers a start pulse DY and a stop pulse DYres based on a clock signal CLY, and sequentially and exclusively supplies each of the scanning lines 112 as scanning signals G1, G2, G3,..., Gm. Is what you do. The specific configuration of the scanning line driving circuit 130 is as shown in FIG.

As shown in FIG. 3, this scanning line driving circuit 1
Reference numeral 30 denotes a Y shift register 131 and an OR gate 132 which forms a signal input to the Y shift register 131.
And is constituted by.

Here, a start pulse DY and a stop pulse DYres are inputted to the input side of the OR gate 132, and when any one of these signals is at the H level (DY
+ DYres) signal to the Y shift register 131.

The Y shift register 131 transfers the supplied (DY + DYres) signal based on the clock signal CLY, and sequentially and exclusively to each of the scanning lines 112 as scanning signals G1, G2, G3,..., Gm. Supply.

The data line drive circuit 140 sequentially latches n binary signals Ds corresponding to the number of the data lines 114 in a certain horizontal scanning period, and then converts the latched n binary signals Ds into the following data. During the horizontal scanning period, data signals d1, d2, d
, Dn are supplied all at once. The specific configuration of the data line drive circuit 140 is as shown in FIG.

As shown in FIG. 4, the data line driving circuit 140 includes an X shift register 1410, a first latch circuit 1420, and a second latch circuit 1430.

Here, the X shift register 1410 transfers the latch pulse LP supplied at the beginning of the horizontal scanning period based on the clock signal CLX, and latches the latch signals S1 and S1.
2, S3,..., Sn are sequentially and exclusively supplied.

The first latch circuit 1420 outputs the binary signal D
s are sequentially latched at the falling edges of the latch signals S1, S2, S3,..., Sn.

The second latch circuit 1430 simultaneously latches each of the binary signals Ds latched by the first latch circuit 1420 at the falling edge of the latch pulse LP and outputs each signal.

Next, the data signal switching circuit 150
And a reset signal RES input from the latch circuit 1430.

When the reset signal RES is at the L level, the data signal switching circuit 150 outputs the data signals d1, d2, d3,..., Dn for applying a voltage to turn off the pixel to the pixel 110. The signal is supplied to the data line 114, and when the reset signal RES is at the H level, the signal output from the data line driving circuit 140 based on the binary signal Ds, that is, the voltage Von for turning on the pixel or turning off the pixel A data signal for applying one of the voltages Voff is supplied to each data line 114.

Next, the voltage switching circuit 160 is constituted by a circuit as shown in FIG.

That is, upon receiving the AC drive signal LCOM,
A reference voltage generation circuit 161 for generating voltage values Va, Vb, Vc according to H / L of FR, and a subfield Sf0
AND gate 162 that outputs a set signal when scanning signal Gi attains an H level, and AND gate that outputs a reset signal when scanning signal Gi attains an H level in subfields Sf1 to Sf3 163, the output of the AND gate 162 is connected to the S terminal, the AND gate 163 is connected to the R terminal, and the reference voltage value generating circuit 1 receives the output signal of the flip-flop circuit 164 and receives the output signal of the flip-flop circuit 164.
A switching element 165 for selecting the voltage values Va and Vb output from 61, an AND gate 166 for outputting a set signal when a scanning signal Gi which becomes H level in the subfields Sf0 to Sf1, and a subfield S2 To the H level in Sf3 to Sf3
an AND gate 167 that outputs a reset signal when i is input; a flip-flop circuit 168 in which the output of the AND gate 166 is connected to the S terminal and the AND gate 167 is connected to the R terminal;
68, the switching element 165
And a switching element 169 for selecting the voltage value Vc output from the reference voltage value generation circuit 161.

Thus, voltage switching circuit 160 provides voltage V having voltage value Va in subfield Sf0.
on, and in the subfield Sf1, a voltage Von having the voltage value Vb is output.
2. At the time of Sf3, a voltage Von having a voltage value Vc is output.

Now, as described above, the subfields Sf0 to Sf0
For each Sf3, the voltage Voff (V
0), Von (Va, Vb, Vc)
It is necessary to convert the gradation data corresponding to the pixel in some way. The data conversion circuit 300 in FIG. 1 performs this conversion.

Therefore, the data conversion circuit 300 supplies 4-bit grayscale data D0 to D3 supplied in synchronization with the vertical scanning signal Vs, the horizontal scanning signal Hs, and the dot clock signal DCLK, and corresponding to each pixel. The configuration is such that conversion into a binary signal Ds (0 or 1) is performed for each of the subfields Sf0 to Sf3.

The data conversion circuit 300 generates the grayscale data D0 to D0 in accordance with the level of the AC drive logic signal FR.
3 needs to be converted to a binary signal Ds. In particular,
The data conversion circuit 300 outputs the binary signal Ds corresponding to the gradation data D0 to D3 based on the contents shown in FIG. 8A when the AC drive logic signal FR is at the L level. On the other hand, when the AC drive logic signal FR is at the H level, the output is performed based on the content shown in FIG.

Since the binary signal Ds needs to be output in synchronization with the operation of the scanning line driving circuit 130 and the data line driving circuit 140, the data conversion circuit 300 supplies the start pulse DY and the horizontal signal A clock signal CLY synchronized with scanning, a latch pulse LP defining the beginning of a horizontal scanning period, and a dot clock signal DCL
A clock signal CLX corresponding to K is supplied.
Further, as described above, in the data line driving circuit 140,
In a certain horizontal scanning period, the first latch circuit 1420
Latches the binary signal Ds dot-sequentially, and then supplies the data signals d1, d2, d3,..., Dn to the data lines 114 all at once in the next horizontal scanning period. With this configuration, the data conversion circuit 300 outputs the binary signal Ds at a timing preceding by one horizontal scanning period as compared with the operation in the scanning line driving circuit 130 and the data line driving circuit 140. ing.

Next, a specific configuration of the data conversion circuit 300 for generating the above-described binary signal Ds will be described. Here, FIG. 7 is a block diagram showing a circuit configuration of the data conversion circuit 300. FIG. 8 is a truth table showing the functions of the data conversion circuit 300.

As shown in FIG. 7, the data conversion circuit 300
Are the drive pattern memory 301 and the EXOR gate 30
2 is constituted.

The drive pattern memory 301 controls the ON / OFF state of a pixel for each combination of a subfield number and gradation data.
One-bit on / off data for specifying off is stored. Then, the sub-field number and the gradation data are given to the drive pattern memory 301 as addresses.

Here, the subfield number is the number of each subfield in one field, and is "0".
To any one of “3”. There are various methods for generating the subfield number. For example, the start pulse DY is counted inside the data conversion circuit 300 and the count result is converted to the level transition (rising and rising) of the AC drive logic signal FR. It is also possible to provide a counter that resets at the time of falling and refer to the count result to recognize the current subfield and set the subfield number.

The drive pattern memory 301 outputs on / off data corresponding to the combination of the subfield number and the gradation data obtained in this way.

The EXOR gate 302 calculates the exclusive OR of the on / off data output from the drive pattern memory 301 and the AC drive logic signal FR, and outputs the result as a binary signal Ds. Here, the AC drive logic signal FR
Is 1 of the latch pulse LP from the AC drive signal LCOM.
This is a digital signal that repeats level inversion at a phase faster by a clock.

When the AC drive logic signal FR is at the L level, the on / off data read from the drive pattern memory 301 is output as it is to the data line drive circuit 140 as a binary signal Ds. On the other hand, when the AC drive logic signal FR is at the H level, the ON / OFF data read from the drive pattern memory 301 is inverted in level by the EXOR gate 302 and is sent to the data line drive circuit 140 as the binary signal Ds. Is output. In any case, when the on / off data is “1”, the binary signal Ds for turning on the pixel is supplied to the data line driving circuit 140.
And when the on / off data is “0”,
A binary signal Ds for turning off the pixel is supplied to the data line driving circuit 140.

When Von is selected by the binary signal Ds (that is, when the on / off data is “1”), the voltage switching circuit 160 determines whether the subfield is Sf0 by the voltage value Va. Weighted, and if Sf1, the voltage value Vb is weighted,
In the case of Sf2 and Sf3, a voltage weighted by the voltage value Vc is applied to the pixel.

FIGS. 8A and 8B show the relationship between the subfield number and the voltage value and the binary signal Ds for the gradation data when the AC drive logic signal FR is at the L level or the H level. ing. That is, the drive pattern memory 301 stores on / off data consisting of “1” and “0” in the truth table shown in FIG.

As is apparent from FIG. 8, the data conversion circuit 300 according to the present embodiment outputs a binary signal Ds for performing pixel on / off driving to the data line driving circuit 140 for each subfield. It has become.

Next, the voltage value of the voltage Von applied for each subfield corresponding to the grayscale data will be specifically described.

First, when the gradation data is (0001), the transmittance of the pixel should be 6.6 (= 1/15)%. For this purpose, the effective voltage value V1 shown in FIG. Must be applied to Therefore, in this embodiment,
The voltage applied between the pixel electrode 118 and the counter electrode 108 of the pixel is Vo in the subfield Sf0.
n = Va, and Vof in other subfields
A voltage is applied to the pixel electrode 118 so that f = V0 (= 0 V). Here, the effective voltage value applied to the pixel is the square of the voltage instantaneous value for one cycle (one field).
Therefore, if the length of the subfield Sf0 is the time obtained by multiplying (V1 / Va) ² for one field (1f), it corresponds to one field (1f). An effective voltage value V1 can be applied.

When the gradation data is (0010), the transmittance of the pixel should be set to 13.3 (= 2/15)%. For this purpose, the effective voltage V2 shown in FIG. It is necessary to apply to this. Therefore, in the present embodiment, the voltage applied between the pixel electrode 118 and the counter electrode 108 of the pixel becomes Von = Vb in the subfield Sf1 and Von in other subfields.
A voltage is applied to the pixel electrode 118 so that off = V0 (0 V). Here, since the effective voltage value applied to the pixel is obtained by the square root obtained by averaging the square of the voltage instantaneous value over one period (one field), the length of the sub-field Sf1 is determined with respect to one field. If the time is multiplied by (V2 / Vb) ² , the effective voltage value V2 corresponding to the gradation data (0010) can be applied to the pixel.

Similarly, when the gradation data is (0011), the transmittance of the pixel should be 20.0 (= 3/15)%, and the effective voltage value V3 is applied to the pixel. There is a need. Therefore, in the present embodiment, the voltage applied between the pixel electrode 118 and the counter electrode 108 of the pixel is Von = Va in the subfield Sf0, Von = Vb in the subfield Sf1, and Von = Vb in the other subfields. Is Voff = V0 (= 0V)
The voltage is applied to the pixel electrode 118 such that By this voltage application, an effective voltage value V3 corresponding to the gradation data (0011) can be applied to the pixel for one field.

Further, when the gradation data is (1000), the transmittance of the pixel should be set to 53.3 (= 8/15)%. For this purpose, the effective voltage value V8 shown in FIG. It is necessary to apply to this. Therefore, in the present embodiment, the voltage applied between the pixel electrode 118 and the counter electrode 108 of the pixel is set such that Von = Vc in the subfield Sf3 and Vo in the other subfields.
A voltage is applied to the pixel electrode 118 so that ff = V0 (= 0 V). Here, the effective voltage value applied to the pixel is obtained by a square root obtained by averaging the square of the voltage instantaneous value over one period (one field). If the time is multiplied by (V8 / Vc) ² , the effective voltage value V8 corresponding to the gradation data (1000) can be applied to the pixel. By applying this voltage, an effective voltage value V8 corresponding to the gradation data (1000) can be applied to the pixel for one field.

Thereafter, similarly, by setting the voltage value in the subfield for the gradation data, the same writing is performed for the other gradation data.

Thus, subfields Sf0 to Sf0
If the writing according to the gradation data is performed for Sf3, the voltage value applied to the liquid crystal layer becomes Va, Vb,
In spite of Vc and V0, display of 16 gradations corresponding to each transmittance becomes possible.

<Operation><Operation of Electro-Optical Device> Next, the operation of the electro-optical device according to the above-described embodiment will be described. FIG. 9 is a timing chart for explaining the operation of the electro-optical device.

First, the level of the AC drive signal LCOM is inverted for each field (1f) and applied to the counter electrode 108. On the other hand, the start pulse DY is supplied at the start of each subfield obtained by dividing one field (1f) as described above.

Here, in one field (1f) where the AC drive signal LCOM is at the L level, when the start pulse DY defining the start of the subfield Sf0 is supplied, the scanning line drive circuit 130 (see FIG. 1) Transfer according to the clock signal CLY in the scanning signal G
, Gm are sequentially and exclusively output during the period (1 Va). The period (1Va) is set to a period shorter than the shortest subfield.

Now, the scanning signals G1, G2, G3,.
m has a pulse width corresponding to a half cycle of the clock signal CLY, and the first scanning line 1 counted from the top.
The scanning signal G1 corresponding to 12 is configured to be output with a delay of at least a half cycle of the clock signal CLY after the clock signal CLY first rises after the start pulse DY is supplied. Therefore, after the start pulse DY is supplied at the beginning of the subfield,
By the time the scanning signal G1 is output, one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140.

Therefore, the case where one shot (G0) of the latch pulse LP is supplied will be examined. First, when one shot (G0) of the latch pulse LP is supplied to the data line driving circuit 140, it is transferred based on the clock signal CLX in the data line driving circuit 140 (see FIG. 4), and the latch signals S1, S2, S3, ..., Sn
Are sequentially and exclusively output during the horizontal scanning period (1H). Each of the latch signals S1, S2, S3,..., Sn has a pulse width corresponding to a half cycle of the clock signal CLX.

At this time, the first latch circuit 1 shown in FIG.
420 is a signal from the falling edge of the latch signal S1 to the pixel 110 corresponding to the intersection of the first scanning line 112 counted from the top and the first data line 114 counted from the left.
The value signal Ds is latched, and then, at the falling of the latch signal S2, the first scanning line 112 counted from the top,
The binary signal Ds to the pixel 110 corresponding to the intersection with the second data line 114 counted from the left is latched, and thereafter, similarly, the first scanning line 112 counted from the top and n counted from the left. Pixel 11 corresponding to the intersection with the first data line 114
Latch the binary signal Ds to 0.

As a result, first, in FIG.
2 for one row of pixels corresponding to the intersection with the actual scan line 112
The value signal Ds is point-sequentially latched by the first latch circuit 1420. The data conversion circuit 3
00 indicates that the grayscale data D0 to D3 of each pixel is set to 2 in accordance with the latch timing by the first latch circuit 1420.
It goes without saying that the signal is converted into the value signal Ds and output.
Also, here, it is assumed that the AC drive signal LCOM (AC drive logic signal FR) is at the L level.
With reference to the table shown in FIG. 8A, a binary signal Ds corresponding to the subfield Sf1 is output according to the gradation data D0 to D3.

Next, when the clock signal CLY falls and the scanning signal G1 is output, the first scanning line 112 counted from the top in FIG. All the transistors 116 of the corresponding pixel 110 are turned on. On the other hand, the falling edge of the clock signal CLY outputs the latch pulse LP. Then, at the falling timing of the latch pulse LP, the second latch circuit 1430 applies the binary signal Ds, which is point-sequentially latched by the first latch circuit 1420, to the corresponding data line 114 as a data signal. .., dn are supplied all at once. Therefore, in the pixels 110 in the first row counted from the top, writing of the data signals d1, d2, d3,..., Dn is performed simultaneously.

In parallel with this writing, the binary signal Ds for one row of pixels corresponding to the intersection with the second scanning line 112 from the top in FIG. Is done.

Then, the same operation is repeated until the scanning signal Gm corresponding to the m-th scanning line 112 is output. That is, a certain scanning signal Gi (i is 1 ≦ i ≦ m
In the one horizontal scanning period (1H) in which the pixel 110 corresponding to the i-th scanning line 112 is output,
Writing data signals d1 to dn for one row of
The point-sequential latching of the binary signal Ds for one row of the pixels 110 corresponding to the (i + 1) -th scanning line 112 is performed in parallel. The data signal written in the pixel 110 is held until it is written in the next subfield Sf2.

The same operation is repeated every time a start pulse DY defining the start of a subfield is supplied. However, the data conversion circuit 300 refers to the corresponding subfield item among the subfields Sf0 to Sf3 when converting the gradation data D0 to D3 into the binary signal Ds.

Further, even if AC drive signal LCOM is inverted to the H level after one field has elapsed, the same operation is repeated in each subfield. However, for conversion from the gradation data D0 to D3 to the binary signal Ds, the table shown in FIG. 8B is referred to.

<Voltage Applied to Pixel> Next, a voltage value of a data signal applied to the liquid crystal layer of the pixel 110 by the data driving circuit 140 will be examined. FIG. 10 is a timing chart showing the gradation data and the waveform applied to the pixel electrode 118 in the pixel 110.

For example, when the AC drive signal LCOM is at the L level and the gradation data D0 to D3 of a certain pixel is (0000), as a result of the conversion shown in FIG. The pixel electrode 118 of FIG.
As shown in FIG. 5, V0 is over one field (1f).
Is written. Here, the effective voltage value applied to the liquid crystal layer is V0. Therefore, the transmittance of the pixel is 0% corresponding to the gradation data (0000).

When the gradation data D0 to D3 of a certain pixel is (0011), as a result of following the conversion contents shown in FIG.
, The voltage value Va is written in the subfield Sf0, and the voltage value Vb is written in the subfield Sf1. Therefore, the effective voltage value applied to the pixel electrode 118 of the pixel is V3. Therefore, the transmittance of the pixel is 20.0% corresponding to the gradation data (0011).
Becomes

Further, gradation data D0 to D3 of a certain pixel
Is (1111), as a result of following the conversion content shown in FIG.
0, the voltage value Va is in the subfield Sf0, the voltage value Vb is in the subfield Sf1, and the voltage value Vb is in the subfield Sf1.
2 and Sf3, the voltage value Vc is written. Therefore, the transmittance of the pixel is determined by the gradation data (111
100% corresponding to 1). Similarly, the gradation data D0 to D3 also correspond to the transmittance for other gradation data.

On the other hand, when the AC drive signal LCOM is at the H level, the level inverted from that at the L level is applied to the pixel electrode 118. For this reason, the AC drive signal L
When COM is at the H level, the voltage applied to each liquid crystal layer is obtained by inverting the polarity of the applied voltage when the AC drive signal LCOM is at the L level, and has the same absolute value. . Therefore, as a result of avoiding a situation in which a DC component is applied to the liquid crystal layer, deterioration of the liquid crystal 105 is prevented.

<Operation of Pixel> Next, the operation of the pixel 110 will be described with reference to the gray scale data D shown in FIG.
It is assumed that signals corresponding to 0 to D3 are written to the pixel electrode 118.

An H level scanning signal Gi is output to the scanning line 112 for each subfield, and the transistor 116a
And 116b are on, H level signal dj instructing the application of a voltage and L level signal obtained by inverting the level are applied to data lines 114a and 11b.
4b. In this case, the inverter 121
Is at H level and the output signal of inverter 122 is at L level.
Only the ON state is established, and the voltage Von is applied to the pixel electrode 118 via the transmission gate 123.

At this time, when the subfield is Sf0, the voltage switching circuit 160 described above uses the Von line 11
Since the voltage value applied to 3a is Va, the voltage value Va is written to the pixel electrode 118.

On the other hand, when the subfield is Sf1, the voltage value applied to the Von line 113a is Vb, so that the voltage value Vb is written to the pixel electrode 118.

Further, the subfields are Sf2 and Sf3.
In this case, the voltage value applied to the Von line 113a is Vc, so the voltage value Vc is written to the pixel electrode 118.

The scanning signal Gi for the scanning line 112 is
Goes low, transistors 116a and 11a
6b is turned off, and inverters 121 and 122 are turned off.
Maintains the previous output signal level. During this time, since only the output signal of the inverter 121 is at the H level, the voltage V
on will be continuously applied to the pixel electrode 118.

Thereafter, the scanning signal G for the scanning line 112 is
When i attains H level again and transistors 116a and 116b are turned on, L level signal dj instructing voltage application and an H level signal whose level is inverted are output to data lines 114a and 114b. Suppose it was done. In this case, since the output signal of the inverter 121 is at the L level and the output signal of the inverter is at the H level, only the transmission gate 124 is turned on, and the voltage Voff (FR) is applied to the pixel electrode 118 via the transmission gate 124. Applied.

Then, the scanning signal G for the scanning line 112
When i becomes the L level, as described above, the inverter 1
21 and 122 maintain the previous output signal level as it is, and the voltage is continuously applied to the pixel electrode 118 via the transmission gate 124.

Further, in the voltage switching circuit 160 shown in FIG. 5, since the output Von outputs Va, Vb, and Vc which are inverted in response to the level inversion of LCOM, the level of the counter electrode 108 is inverted by FR. Even in this case, a signal having a voltage difference Va, Vb, Vc based on FR is output.

<Off-Voltage Application Period> Next, the off-voltage application period fx will be described with reference to FIGS. Note that the gradation data is (1111).

First, FIG. 11 is a timing chart of the voltage written for each row when the off-voltage application period fx is not provided. In this case, when the voltage value of Von is switched corresponding to the voltage application in the first row, as shown by the dotted line, the voltage value is changed during the application of the voltage to each pixel 110 in the second to m-th rows. Will be switched,
The effective voltage value differs from a desired value. As a result, it becomes impossible to perform a gradation display corresponding to the gradation data.

Therefore, in the present embodiment, an off-voltage application period fx as shown in FIG. 12 or 13 is provided.
The off-voltage application period fx is generated when the voltage value of the voltage Von is switched, and the generating operation is as follows.

First, the reset signal RES output from the timing signal generation circuit 200 is set to the off voltage application period f.
x, which is supplied to the scanning line driving circuit 130 and the data line driving circuit 140. The reset signal RES changes from H level to L level when the voltage value of the voltage Von changes.

Since the scanning line driving circuit 130 has a configuration as shown in FIG. 3, the (DY + DYres) signal is low.
After switching from the H level to the H level, the clock signal C
When LY switches from the H level to the H level, the scanning signals G1 to Gm serving as signals for permitting writing to the pixels 110 arranged in a row are exclusively and sequentially supplied to each scanning line 112 (see FIG. 12). ). Here, in each subfield where the voltage value is switched, although the start is sequentially different, the time from the scanning signal due to the generation of the stop pulse DYres to the scanning signal due to the generation of the start pulse DY becomes equal for each row, and this period is The off-voltage application period is fx.

In the data signal switching circuit 150, H
When the level reset signal RES is supplied, a data signal (a signal for turning on a pixel or a signal for turning off a pixel) based on grayscale data is supplied from the latch circuit 1430 to the data line 114. .

On the other hand, when the L-level reset signal RES is supplied to the data signal switching circuit 150, a data signal for turning off the pixel is supplied to the data line 114 regardless of the signal based on the gradation data. . Since the pixel 110 has a circuit configuration as shown in FIG. 2, the data signal dj of the data line 114a is set to the voltage Vof.
f, the data signal / dj of the data line 114b is the voltage Von
(The voltage value Vc), the voltage V
off is written. In addition, the voltage Voff is applied during the period from the end of voltage application in the previous subfield to the start of voltage application in the next subfield. In FIGS. 12 and 13, the voltage application on the first row in the next subfield is started almost simultaneously with the completion of the voltage application on the m-th row. However, the present embodiment is not limited to this. Needless to say, a time may be provided from the end of the voltage application in the m-th row to the start of the voltage application in the next first row.

As described above, in the present embodiment, by providing the off-voltage application period fx, when shifting from one subfield to the next subfield, the switching of the voltage value of Von is performed for each pixel in the previous subfield. This can be performed after the voltage application to the pixel is completed, and a voltage corresponding to the gradation data can be applied to each pixel for each subfield.

Further, when the voltage value is switched for each row without providing the off-voltage application period fx, the voltage switching circuit 160 for controlling each row is required. However, in the present embodiment, when the voltage value of the voltage Von is switched, the off-voltage application period fx is provided between the subfields. The switching can be performed after the data signal is written to the pixel, and there is no need for a switching circuit for switching the voltage value for each row and its control, and the switching of the voltage value of the voltage Von can be simplified by one voltage switching circuit 160 Can be done.

<Effects of Embodiment> According to the electro-optical device according to such an embodiment, one field (1f) is
It is divided into four subfields Sf0 to Sf3, and for each subfield, the voltage value of the voltage Von for turning on the pixel is weighted by three values of Va, Vb, and Vc to obtain 1
Sets the effective voltage value in the field. Thereby, the data signals d1 to d supplied to the data line 114
Since n is a digital signal, circuits for processing analog signals, such as high-precision D / A conversion circuits and operational amplifiers, are not required in peripheral circuits such as drive circuits. Therefore, the circuit configuration is greatly simplified, and the cost of the entire device can be reduced.

Further, since the data signals d1 to dn supplied to the data lines 114 are digital signals, display unevenness due to non-uniformity such as element characteristics and wiring resistance does not occur in principle. Therefore, according to the electro-optical device according to the present embodiment, high-quality and high-definition gradation display can be performed.

Further, the binary signal Ds divides one field into four subfields Sf0 to Sf3, and outputs the subfields Sf0 to Sf3 based on 4-bit gradation data D0 to D3.
The voltage values f0 to Sf3 are weighted by V0, Va, Vb, and Vc. Therefore, a sufficient writing time can be ensured even in a subfield of a relatively short time among the sub-feeds Sf0 to Sf3, and a data signal can be reliably written to each pixel 110. The gradation display by the device can be performed with high accuracy.

In the present embodiment, when the voltage value of the voltage Von is switched, an off-voltage application period fx is provided between subfields, and the voltage application to each pixel in the previous subfield is terminated to switch the voltage value. Is performed, the voltage is accurately applied to each pixel corresponding to the gradation data in each subfield, and gradation display corresponding to the gradation data can be performed.

In addition, the switching of the voltage value of Von is performed after the application of the voltage at the final stage is completed, so that the switching of the voltage value can be easily performed by one voltage switching circuit 160.

Further, according to the present embodiment, since the memory built-in type pixels are employed, the voltage applied to the pixel electrodes does not volatilize due to the leakage, and the driving of each pixel in the unit of sub-field does not occur. It can be performed with high accuracy.

In the above-described embodiment, the level of the AC drive signal LCOM is inverted at a cycle of one field. However, the present invention is not limited to this. The level may be inverted. However, in the above-described embodiment, the data conversion circuit 300 recognizes the current subfield by counting the start pulse DY and resetting the count result by the transition of the AC drive signal LCOM. , AC drive signal LCOM
When the level is inverted at a cycle of two fields, it is necessary to provide some signal in order to define the field.

<Application> In the above embodiment, 16
Although gradation display is used, for example, it is possible to correspond to gradation display of 8 gradations, 32 gradations, or 64, 128, 256, 512,....

<Overall Structure of Liquid Crystal Device> Next, with respect to the structure of the electro-optical device according to the above-described embodiment and application,
This will be described with reference to FIGS. Here, FIG.
4 is a plan view showing the configuration of the electro-optical device 100,
FIG. 15 is a sectional view taken along line AA ′ in FIG.

As shown in these figures, the electro-optical device 100 includes an element substrate 101 on which a pixel electrode 118 and the like are formed, and a counter substrate 1 on which a counter electrode 108 and the like are formed.
02 are bonded to each other with a fixed gap therebetween by a sealant 104, and a liquid crystal 105 as an electro-optical material is sandwiched in the gap.
Actually, the sealing material 104 has a cutout portion, and after the liquid crystal 105 is sealed through the cutout portion, it is sealed with a sealing material, but is omitted in each drawing.

Here, the element substrate 101 is opaque because it is a semiconductor substrate as described above. Therefore, the pixel electrode 118 is formed of a reflective metal such as aluminum, and the electro-optical device 100 is used as a reflective type. On the other hand, the counter substrate 102 is transparent because it is made of glass or the like.

In the element substrate 101, a light-shielding film 106 is provided inside the sealant 104 and outside the display area 101a. In the region where the light-shielding film 106 is formed, the scanning line driving circuit 130 is formed in the region 130a, and the data line driving circuit 140 is formed in the region 140a. That is, the light shielding film 106
Prevents light from entering the drive circuit formed in this region. The light shielding film 106 has a counter electrode 108
At the same time, the AC drive signal LCOM is applied. For this reason, in the region where the light-shielding film 106 is formed, the voltage applied to the liquid crystal layer becomes substantially zero, and the display state is the same as the state where no voltage is applied to the pixel electrode 118.

In the element substrate 101, a plurality of connection terminals are formed outside the region 140a where the data line driving circuit 140 is formed and separated from the sealing material 104 by external control. It is configured to input signals and power.

On the other hand, the opposite electrode 108 of the opposite substrate 102
Is electrically connected to the light-shielding film 106 and the connection terminals of the element substrate 101 by a conductive material (not shown) provided in at least one of the four corners of the substrate bonding portion. That is, the AC drive signal LC
The OM is configured to be applied to the light-shielding film 106 via a connection terminal provided on the element substrate 101 and further to the counter electrode 108 via a conductive material.

In addition, depending on the use of the electro-optical device 100, for example, in the case of a direct-view type, first, color filters arranged in a stripe shape, a mosaic shape, a triangle shape, etc. Second, a light-shielding film (black matrix) made of, for example, a metal material or a resin is provided. In the case of color light modulation, for example, when used as a light valve of a projector described later, no color filter is formed. In the case of a direct-view type, a front light for irradiating the electro-optical device 100 with light from the counter substrate 102 side is provided as necessary. In addition, the element substrate 101 and the counter substrate 1
An alignment film (not shown) rubbed in a predetermined direction is provided on the electrode forming surface of No. 02 to define the alignment direction of the liquid crystal molecules in the state where no voltage is applied. And a polarizer (not shown) corresponding to the orientation direction. However, when a polymer-dispersed liquid crystal in which fine particles are dispersed in a polymer is used as the liquid crystal 105, the above-described alignment film and polarizer are not required, and the light use efficiency is increased. This is advantageous in terms of low power consumption and the like.

<Others> In the embodiment, the element substrate 101 constituting the electro-optical device is used as a semiconductor substrate, and the transistor 116 connected to the pixel electrode 118 and the components of the driving circuit are replaced with MOS transistors. Type FET
However, the present invention is not limited to this. For example,
The element substrate 101 may be an amorphous substrate such as glass or quartz, and a semiconductor thin film may be deposited thereon to form a TFT. When a TFT is used in this manner, a transparent substrate can be used as the element substrate 101.

Further, as an electro-optical material, in addition to a liquid crystal, an electroluminescent element or the like can be used to apply to an apparatus for displaying by the electro-optical effect. That is, the present invention is applicable to all electro-optical devices having a configuration similar to the above-described configuration, and particularly to all electro-optical devices that perform gradation display using pixels that perform on- or off-state binary display. It is.

<Electronic Equipment> Next, some examples in which the above-described liquid crystal device is used in specific electronic equipment will be described.

<Part 1: Projector> First, a projector using the electro-optical device according to the embodiment as a light valve will be described. FIG. 16 is a plan view showing the configuration of this projector. As shown in this figure,
Inside the projector 1100, a polarized light illumination device 1110 is provided.
Are arranged along the system optical axis PL. In the polarized light illuminating device 1110, the light emitted from the lamp 1112 becomes a substantially parallel light beam due to reflection by the reflector 1114, and enters the first integrator lens 1120. As a result, the light emitted from the lamp 1112 is split into a plurality of intermediate light beams. This split intermediate beam is
The polarization conversion element 1130 having the second integrator lens on the light incident side converts the light into one type of polarized light beam (s-polarized light beam) having a substantially uniform polarization direction, and emits it from the polarized light illuminating device 1110.

The s-polarized light beam emitted from the polarized light illuminating device 1110 is reflected by the s-polarized light beam reflecting surface 1141 of the polarizing beam splitter 1140. Of this reflected light beam, the light beam of blue light (B) is reflected by the blue light reflecting layer of the dichroic mirror 1151, and is modulated by the reflection-type electro-optical device 100B. Further, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of red light (R) is
The light is reflected by the red light reflection layer 52 and is modulated by the reflection type liquid electro-optical device 100R. On the other hand, among the light beams transmitted through the blue light reflecting layer of the dichroic mirror 1151, the light beam of green light (G) is
The light passes through the 52 red light reflecting layer and is modulated by the reflection-type electro-optical device 100G.

Thus, the electro-optical device 100R,
The red, green, and blue lights, each of which has been color-modulated by 100G and 100B, are output to a dichroic mirror 115.
2, 1151, and are sequentially synthesized by the polarizing beam splitter 1140, and then projected on the screen 1170 by the projection optical system 1160. Note that the electro-optical devices 100R, 100B, and 100G are provided with dichroic mirrors 1151 and 1152 for R, G,
Since a light beam corresponding to each primary color of B enters, no color filter is required.

<Part 2: Mobile Computer> Next, an example in which the electro-optical device is applied to a mobile personal computer will be described. FIG. 17 is a perspective view showing the configuration of this personal computer.
In the figure, a computer 1200 includes a keyboard 12
02, a display unit 1206,
It is composed of This display unit 1206 is
It is configured by adding a front light to the front surface of the electro-optical device 100 described above.

In this configuration, the electro-optical device 100
Is used as a reflection direct-view type, so that the pixel electrode 1
At 18, the reflected light is scattered in various directions,
A configuration in which unevenness is formed is desirable.

<Part 3: Mobile Phone> An example in which the above-described electro-optical device is applied to a mobile phone will be described. FIG. 18 is a perspective view showing the configuration of the mobile phone. In the figure, a mobile phone 1300 has a plurality of operation buttons 130.
The electro-optical device 100 is provided together with the earpiece 1304 and the mouthpiece 1306 in addition to the earpiece 2. The electro-optical device 100 is also provided with a front light on its front surface as needed. Also in this configuration, the electro-optical device 10
Since 0 is used as a reflection direct-view type, it is desirable that the pixel electrode 118 be formed with irregularities.

Note that the electronic devices are shown in FIGS.
In addition to those described with reference to the above, a liquid crystal television, a viewfinder type, a video tape recorder of a monitor direct-view type, a car navigation device, a pager, an electronic organizer, a calculator, a word processor, a workstation, a videophone, a PO
An S terminal, a device equipped with a touch panel, and the like are included. Needless to say, the electro-optical device according to the embodiment or the applied form can be applied to these various electronic devices.

[0157]

As described above, according to the present invention, the data signal applied to the data line is digitized,
High-quality gradation display is possible.

The voltage value for turning on the pixel is 2
Since more than one type is provided, and the voltage value is weighted for each subfield according to the grayscale level of the pixel, for example, even when the grayscale display is set to 64 grayscales, the period of the subfield is made relatively long. Therefore, writing to the pixel by the data signal can be reliably performed.

Further, when the voltage value of the voltage for turning on the pixel is switched, the voltage corresponding to the gradation data in each subfield is changed by applying the voltage to each pixel in the previous subfield. It can be applied to the pixel, and a display corresponding to the gradation data can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an electrical configuration of an electro-optical device according to an embodiment of the invention.

FIG. 2 is a block diagram showing one mode of a pixel of the electro-optical device.

FIG. 3 is a block diagram showing a configuration of a scanning line driving circuit in the same electro-optical device.

FIG. 4 is a block diagram showing a configuration of a data line driving circuit in the same electro-optical device.

FIG. 5 is a block diagram showing a configuration of a voltage switching circuit in the same electro-optical device.

FIG. 6 is an explanatory diagram showing voltage-transmittance characteristics in the same electro-optical device.

FIG. 7 is a block diagram showing a configuration of a data conversion circuit in the same electro-optical device.

FIGS. 8A and 8B are tables showing conversion contents of gradation data of a data conversion circuit in the same electro-optical device.

FIG. 9 is a timing chart showing an operation of the electro-optical device.

FIG. 10 is a timing chart showing a voltage applied to a counter substrate and a voltage applied to a pixel electrode in the same electro-optical device in field units.

FIG. 11 is a timing chart showing a voltage applied to each pixel electrode in each row when an off-voltage application period is not provided.

FIG. 12 illustrates a case where an off-voltage application period is provided.
6 is a timing chart showing the operation of the scanning line driving circuit and the voltage applied to each pixel electrode for each row in sub-field units.

FIG. 13 illustrates a case where an off-voltage application period is provided.
6 is a timing chart showing an operation of a data line driving paddle and a voltage applied to each pixel electrode for each row in sub-field units.

FIG. 14 is a plan view showing the structure of the electro-optical device.

FIG. 15 is a sectional view showing a structure of the electro-optical device.

FIG. 16 is a cross-sectional view illustrating a configuration of a projector as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 17 is a perspective view showing a configuration of a personal computer as an example of an electronic apparatus to which the electro-optical device is applied.

FIG. 18 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the electro-optical device is applied.

[Explanation of symbols]

 100 electro-optical device 101 element substrate 101a display area 102 counter substrate 105 liquid crystal (electro-optical material) 108 counter electrode 112 scanning line 114 data line 116 transistor 118 ... Pixel electrode 119 Storage capacitance 130 Scan line drive circuit 131 Y shift register 132 OR gate 140 Data line drive circuit 150 Data signal switching circuit 1410 X shift register 1420 1 latch circuit 1430 second latch circuit 160 voltage switching circuit 200 timing signal generation circuit 300 data conversion circuit 400 clock signal supply control circuit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G02F 1/133 575 G02F 1/133 575 G09G 3/36 G09G 3/36 F-term (Reference) 2H093 NA43 NA55 NA55 NB02 NB08 NB12 NB30 NC03 NC16 NC22 NC26 NC34 NC35 ND06 ND49 ND54 NG02 NH15 5C006 AA01 AA14 AA16 AC28 AF44 BB11 BC12 BF03 BF04 BF06 BF26 EC11 FA56 5C080 AA10 BB05 DD05 DD22 EE29 FF09 JJ02JJ04

Claims (7)

[Claims] 1. A driving method for an electro-optical device that receives gradation data of each pixel for one screen for each field and drives each pixel on and off based on the gradation data, and satisfies the following requirements. A method of driving an electro-optical device. a. The field is divided into a plurality of subfields, and a voltage for turning on each pixel or a voltage for turning off each pixel is applied to each pixel in subfield units. b. Two or more voltage values for turning on the pixel are provided. c. The switching of the voltage value when shifting the subfield is performed after the voltage application to each pixel in the previous subfield is completed. 2. When the voltage for turning on the pixel is switched with the transition from the previous subfield to the next subfield, from the end of the voltage application in the previous subfield to the start of the voltage application in the next subfield. During
The method according to claim 1, wherein a voltage for turning off the pixel is applied to each pixel. 3. Receiving the gradation data of each pixel for one screen for each field, and arranging the data corresponding to each intersection of a plurality of data lines and a plurality of scanning lines based on the gradation data. A driving circuit of an electro-optical device for driving each pixel, wherein in each of a plurality of subfields obtained by dividing one field, a binary signal for instructing application of a voltage for turning on or off a pixel is provided. A data conversion circuit that is generated based on gradation data; and a scanning line driving circuit that sequentially supplies a scanning signal enabling voltage application from a data line to a pixel to each of the scanning lines for each of the subfields. A data signal for applying a voltage for turning on or off the pixel based on a binary signal generated by the data conversion circuit while the scan signal is supplied to the scan line; A data line driving circuit for supplying the data line to the data line; a voltage switching circuit for switching a voltage for turning on the pixel; and a voltage switching circuit for switching the subfield when the voltage is switched by the voltage switching circuit. Data for applying a voltage to turn off the pixels from the end of voltage application to each pixel on the scanning line in the previous subfield until the scanning signal in the next subfield is supplied to the scanning line. A data signal switching circuit for forcibly applying a signal to the plurality of data lines; and a driving circuit for the electro-optical device. 4. An electro-optical device having a plurality of pixels arranged corresponding to respective intersections of a plurality of scanning lines and a plurality of data lines, wherein each of a plurality of sub-fields obtained by dividing one field is provided. A data conversion circuit that generates a binary signal instructing application of a voltage for turning on or off a pixel based on grayscale data; and applying a voltage from a data line to a pixel for each subfield. A scan line driving circuit for sequentially supplying a scan signal to each of the scan lines, and a binary signal generated by the data conversion circuit while the scan signal is supplied to the scan line. A data line driving circuit for supplying a data signal for applying a voltage for turning on or off the pixel to the data line; a voltage switching circuit for switching a voltage for turning on the pixel When the voltage is switched by the voltage switching circuit when shifting the subfield, the scanning signal in the next subfield after the voltage application to each pixel on the scanning line in the previous subfield in each scanning line is completed. And a data signal switching circuit for forcibly applying a data signal for applying a voltage to turn off the pixel to the plurality of data lines until is supplied to the scanning line. Electro-optical device. 5. The pixel is provided with a pixel electrode, a counter electrode facing the pixel electrode, an electro-optical material sandwiched between the pixel electrode and the counter electrode, and a scan signal supplied to the pixel via the scan line. A memory for storing a data signal supplied via the data line, and selecting one of a voltage for turning on the pixel and a voltage for turning off the pixel in accordance with the data signal stored in the memory. The electro-optical device according to claim 4, further comprising: 6. The electro-optical device according to claim 4, wherein the level of the binary signal is inverted according to a level applied to the counter electrode. 7. An electronic apparatus comprising the electro-optical device according to claim 4 as a display device.