KR100879769B1 - Active matrix array devices - Google Patents

Abstract

The active matrix device includes a plurality of display elements 10 including data storage nodes 18 and 72 that store data in the form of capacitors 72 and / or capacitive elements 18. For example, a refresh circuit 51 is provided to refresh the data storage node including the temporary storage circuit 55 and the drive circuit 56.

Description

ACTIVE MATRIX ARRAY DEVICES

FIELD OF THE INVENTION The present invention relates to an active matrix array device comprising an array of matrix elements, in particular one of which active matrix devices comprising display pixels, in particular active matrix liquid crystal display devices and active matrix electroluminescent display devices. It is about.

Active matrix display devices, especially active matrix liquid crystal display devices (AMLCDs), are now increasingly used in a variety of product areas, with laptop and notebook computer screens, desktop computer monitors, PDAs, electronic notebooks and mobile phones most likely. Will be friendly.

Examples of an active matrix device other than a display device include a sensing device such as an image sensing device and a fingerprint sensing device in which the matrix element includes, for example, an optical sensing element or a capacitive sensing element, and the matrix element is for example a piezoelectric element or Included are converters that include movable electromechanical elements, such as electrostatically controlled actuator elements.

The structure and general operation of a conventional active matrix display device, in this case AMLCD, is described in US-A-5130829, the entire contents of which are incorporated herein by reference. In short, the display device comprises an array of pixels arranged in rows and columns, each pixel typically comprising an electro-optic display element and associated switching device in the form of a thin film transistor (TFT). The pixel is connected with a set of row and column address electrodes, each pixel being located around an intersection between each electrode of each set, the pixel being sequential to each row electrode by the row and column address electrodes A selection (scanning) signal applied to select the row and supplied to the pixels of the selected row by the column address electrode at the same time as the row selection, and data for determining the display output of each pixel of the associated row (video information ) Is addressed using the. The data signal is derived by appropriately sampling the input video signal in the column address circuit connected with the column address electrode. The pixels in each row are addressed in turn to make the display from the entire array in one field (frame) period, with the pixel array repeatedly addressed in this manner in successive fields. Due to the losses incurred in pixels, it is necessary to refresh the pixels regularly using video information. In the case of an AMLCD, the polarity of the data signal voltage applied to the display element needs to be inverted periodically to prevent deterioration of the LC material. For example, each field may be inverted (so-called field inversion), or each row may also be inverted (so-called line inversion) after being addressed.

Much of the power consumption of an active matrix display device is related to transferring video information from the video signal source to the pixels of the display device. This power component can be reduced if the pixels of the display device can store the video signal for an indeterminate time period. In such a case, the addressing of the pixel using the new video information can be stopped when no change in the display output (luminance) state of the pixel is required.

Conventionally, a display has been proposed in which video information is stored in pixels of a display device. For example, US-A-4430648 shows that an active matrix LC display can operate in a manner similar to a dynamic memory, using a voltage on a pixel that is periodically refreshed to maintain an image on the display. The entire contents of are incorporated herein by reference. This is accomplished by integrating the sense and refresh circuitry within the column addressing circuitry of the display. During the refresh operation, charge is transferred from the pixels in one row of the display device to the corresponding column electrodes. A sensing circuit is then used to detect this charge and to determine the state of the pixel. This information is then written again to the same pixel by the refresh circuit. One disadvantage of this approach is that the signal that must be detected by the sensing circuit is relatively small because the column capacitor has a relatively large value compared to the pixel capacitor. This makes the design of the sensing circuit difficult, and the performance of the sensing circuit has a significant influence on the operation of the display device. In particular, the display device can be sensitive to sources of electrical noise. Also, as the pixels in the display device are refreshed, the columns of the display device are driven in accordance with the video information stored by the refresh circuit. The charging and discharging of the thermal capacitor will consume the power of the display device.

The present invention provides an active matrix array device, and in particular an active matrix display device improved in this respect.

According to the present invention, there is provided an active matrix device in which data or information is dynamically stored in the form of charge retained in a capacitor in a matrix element, which device can incorporate one or more new features or combinations of such features as described herein. Have

According to a first aspect of the invention, an active matrix device comprises an array of matrix elements, each matrix element having at least one storage node having a capacitor for dynamically storing data in the form of charge stored on the capacitor. The matrix element may further include a refresh circuit for refreshing data stored in the storage node.

Thus, there is provided an active matrix device comprising means for refreshing video information in which matrix elements (pixels) are stored. Through the refresh means, the display output (luminance) of the pixel in the display device can be maintained even if it is not addressed using the new video information. Compared to the device of the kind described in US-A-4430648 described above, the advantage of such a device is that power consumption can be reduced because the pixel need not be addressed if its output state does not need to be changed. In particular, losses occurring in any circuit driving the column electrode as a result of the capacitance of the column electrode can be avoided.

In an embodiment, the refresh circuit may include a temporary storage circuit for storing data in the storage node and a storage node driving circuit for driving the storage node according to the data stored in the temporary storage circuit. The storage node driving circuit may include an inverter for driving the storage node with an inverted value of data stored in the temporary storage circuit. In this manner, the inversion of the data stored in the storage node can be obtained when the storage node is refreshed. The inversion value is particularly important in the liquid crystal display device in order to reduce the long term deterioration of the liquid crystal.

The refresh circuit can be driven by a refresh line to activate the refresh circuit to refresh the storage node. Then, in the display device embodiment, the first mode of dynamically driving the display device without internal refresh by controlling the refresh externally, and the internal refresh circuit periodically by the display device in response to a periodic refresh signal on the refresh line. The display apparatus may operate in a second mode in which the still image stored in the internal storage node refreshed by the second image is displayed.

The storage node may comprise a separate capacitor. Alternatively or additionally, data may be stored in the pixel circuit device. For example, in the case of liquid crystal displays, data may be stored on the capacitors of the pixel electrodes used to drive the pixels.

In an embodiment, each matrix element is driven by an address line and connected between a column line and a data storage node, an address switch, a storage switch connecting a storage node with a temporary storage circuit, and a storage node with a storage node driving circuit. A refresh switch, wherein the storage switch and the refresh switch are connected with a common refresh line for switching between a first setting in which the storage switch is opened and the refresh switch is closed, and a second setting in which the storage switch is closed and the refresh switch is opened. Has a control terminal. In the first configuration, the storage node may be refreshed, and in the second configuration, data on the storage node may be stored in the temporary storage circuit.

The matrix element (pixel) may comprise a plurality of data storage capacitors for storing a plurality of data bits. In this manner, still images stored on data storage capacitors can have multiple gray levels or colors, or both, per matrix element. The capacitor may be, for example, part of a liquid crystal pixel element or a separate capacitor.

Each row of the device is addressed by a plurality of row address lines that control a plurality of address thin film transistors connected to respective data storage capacitors, thereby selecting one or more data storage capacitors. In an alternative arrangement, a plurality of column address lines may be provided in each column to address the plurality of address thin film transistors.

The plurality of address thin film transistors may be connected to a common driving line connected to the column line through the select transistor, where the select transistor is controlled by the select line. By connecting one select transistor with the column line, rather than connecting the column line in parallel with all the address thin film transistors, the address thin film transistor is not connected as a load of the capacitance of the column line. Thus, the thermal lines can be easier and / or faster to drive. The selection transistor may be one of the address thin film transistors or a separate transistor.

A refresh line may be provided to control the refresh circuit such that the refresh circuit for refreshing the selected data storage capacitor is connected to a common drive line.

The refresh circuit can include a pair of cross-connected inverters.

In an embodiment, each matrix element comprises a plurality of register units connected in series, each register unit comprises a data storage node, and a register unit connected with a subsequent register unit is driving means for driving the next register unit. It includes. At least one clock line may be provided to control data transfer along a series of register units. In this way, data is provided to the data input at the start of a series of register units, and data is passed through the series of register units until data is written to each register unit, thereby addressing the plurality of data storage nodes. It is possible to reduce the number of address or column lines required. After data is written, the data can be refreshed periodically by the refresh circuit as needed.

The drive means may also function as a refresh circuit by reconnecting the output end of the drive means to the storage node. The driving means may be an inverter. This reduces the number of independent elements needed for each pixel.

The invention also relates to a method of operating an active matrix device having a matrix element comprising a storage node, comprising: storing image data as charge in the storage node; And displaying the stored image data, and periodically applying a refresh signal to the refresh circuit in the matrix element to cause the refresh circuit to refresh the image data stored in the storage node. It includes the step of working.

The method may further comprise operating the active matrix device in a normal mode by regularly addressing matrix elements with new video information and displaying the video information.

Further features and advantages of the present invention will become apparent by reading the following description of the preferred embodiments, given by way of example only, with reference to the accompanying drawings.

1 is a simplified schematic diagram of a typical known AMLCD.

2 and 3 schematically show a typical pixel circuit in each of the two embodiments of the active matrix device according to the invention.

4 schematically illustrates the functional part of the pixels of FIGS. 2 and 3;

FIG. 5 shows an additional possible pixel circuit device having a refresh function and suitable for use in an alternative type of display device such as an AMLED display device.                 

6 illustrates another pixel circuit capable of storing video information in a plurality of binary digits.

7 illustrates an additional pixel circuit having a plurality of data storage nodes.

8 illustrates another pixel circuit having a plurality of data storage nodes.

9 illustrates an additional pixel circuit having a plurality of data storage nodes.

10 illustrates another pixel circuit having a plurality of data storage nodes.

11 and 12 show in more detail an exemplary pixel circuit according to the invention.

13 illustrates exemplary voltage waveforms present in the operation of the pixel circuits of FIGS. 11 and 12.

14 illustrates an alternative pixel circuit in accordance with the present invention.

15-17 illustrate refresh circuits suitable for use in the present invention.

18 to 21 show refresh apparatuses in an embodiment having a plurality of data storage nodes.

22 and 23 show an apparatus according to the invention with a plurality of register units arranged in series.

24 shows signals used in the device of FIGS. 22 and 23.

In the drawings, the same reference numerals are used to denote the same, similar, or corresponding parts.

Referring to FIG. 1, a simplified schematic circuit diagram of a conventional conventional AMLCD including a row and column matrix array NxM of display pixels 10 is shown. Each display pixel has a liquid crystal display element 18 and an associated TFT 12 serving as a switching device, and is addressed via a set of (M) row and (N) column address electrodes 14, 16. For simplicity, only a few display pixels are shown here, and there may actually be rows and columns of hundreds of pixels. The drain of each TFT 12 is connected with each display element electrode disposed adjacent to the intersection of each column and row address electrode, while the gates of all the TFTs associated with each row of display pixels 10 are the same. The source of all the TFTs associated with each column of display pixels is connected with the row address electrode 14 and the same column address electrode 16. The electrodes 14, 16, TFT 12, and display element electrodes are all housed on the same insulating substrate, for example glass, and are associated with the deposition and photolithographic patterning of various conductive, insulating, and semiconductor layers. It is made using known thin film techniques. Second glass substrates (not shown) containing continuous transparent electrodes common to all display elements in the array are spaced apart from the substrate 25 and the two substrates define a confined space in which the liquid crystal material will be contained. In order to be sealed together around the edge of the pixel array. Each display element electrode defines a light modulated LC display element with an overlap of the common electrode and the liquid crystal material therebetween.

In operation, a select (gating) signal is applied to each row address electrode 14 in sequence by a row drive circuit 30, e.g., from row 1 to row M, including, for example, a digital shift register. The data signal is applied to the column electrode 16 by the column drive circuit 35 in synchronization with the selection signal. When each row electrode 14 is addressed using a selection signal, the pixel TFT 12 connected with the row electrode is turned on, so that each display element is a data signal present at the associated column electrode. It is charged according to its level. After a row of pixels is addressed, for example, with each row address period T _L corresponding to the line period of the applied video signal, the associated TFT is left in the rest of the field (frame) period to electrically insulate the display element. During the part, it is off at the end of the select signal to ensure that the applied charge is stored to maintain its display output until it is addressed again in a subsequent field period. Each row of pixels in the array from row 1 to row M is addressed in each successive row address period T _L in this manner, producing a display image from the array in one field period Tf. Where Tf is equal to or slightly larger than M × T _L, and then the operation is repeated for successive fields.

The timing of operation of the row and column drive circuits 30, 35 is controlled by the timing and control unit 40, for example, in accordance with timing signals derived from input video signals obtained from a computer or other source. The video information in this input signal is supplied to the column drive circuit 35 in series form via the bus 31 by the video signal processing circuit in the unit 40. Such circuitry includes one or more shift registers / sampling and retention circuits that sample the video information signal in synchronism with the row scan to provide serial-to-parallel conversion suitable for simultaneous row addressing of the pixel array. Successive fields of video information according to successive fields of the input video signal are written to the array by repeatedly addressing the rows of pixels of the array in successive field periods.

In the transmissive mode of operation, the display element electrodes are formed of a light transmissive conductive material such as ITO, and each display element functions to modulate light directed to one side from the backlight, for example, to address all rows of pixels in the array. The display image thus created can be viewed from the other side. In the reflective mode of operation, the display element electrode is formed of a light reflecting conducting material, and light entering the front of the device through the substrate supporting the common electrode is modulated by the LC material of each display element in accordance with its display state. It is reflected back through the substrate, producing a display image that the viewer can see from the front.

Following known practice, the polarity of the drive voltage applied to the display element is periodically inverted, for example after every field, so that deterioration of the LC material is avoided. Polarity inversion can also be performed after every row (row inversion) to reduce the flicker effect.

In this device, a significant amount of power is consumed when transferring video information from a video signal source to a display pixel. When the display device is used in portable battery-charged equipment such as a notebook computer or a mobile phone, it is naturally desirable to minimize the power consumed by the display device during operation. If the pixel simply displays the same information continuously and no change to its display output is needed, then the pixel's addressing with the new video information is stopped, so that if the pixel can store video information for an indeterminate period, Consumption can be reduced.

As mentioned above, in US-A-4430648, video information is dynamically stored in pixels, but the methods associated with the use of sensing and refresh circuits in column drive circuits, described for realizing this, in particular the design and performance of such circuits. And a method of operation in which the thermal capacitor is periodically charged and discharged, inevitably consumes power.

This disadvantage can be overcome at least to some extent by providing a refresh circuit within the pixels of the display device.

An embodiment of an active matrix device according to the invention, using this method and including an active matrix device, especially as applied to AMLCDs, is now shown in FIGS. 2 and 3 schematically illustrating a general pixel circuit arrangement in the device. This will be explained with reference.

In each case, the pixel 10 is selected by two circuit elements, namely an address control signal, and a switch device 50 which allows the video information supplied by the column drive circuit 35 of the display device to be transferred to the pixel, And a refresh circuit 51 capable of correcting any deterioration in the stored video information activated by the refresh control signal. The switch device 50 may similarly include the TFT 12. The LC display element 18 is again represented by a capacitor. In each arrangement, the refresh circuit 51 is addressed via an auxiliary row electrode 52 extending next to the associated row address electrode 14.

Once the pixel 10 is addressed, the charge representing the video information to be displayed is placed in the display element capacitor (combination of the liquid crystal capacitor and any pixel storage capacitor (not shown)). Over one time period, the display element capacitors will discharge, and the stored video information deteriorates. This can be avoided by periodically operating the refresh circuit to recover the video information. The functional elements of the refresh circuit are shown in FIG. The first part of the circuit is a temporary data storage circuit 55 which holds video information while the storage node (display element capacitor) is refreshed. The output of the temporary storage circuit is supplied to the storage node driver circuit 56. This circuit restores the video information on the storage node to its original state.

Although the function of the refresh circuit 51 is to recover the video information on the storage node, this does not necessarily mean to restore the voltage of the storage node or the charge on the pixel capacitor to its initial value. It may be appropriate to modify the way the video information is displayed. This can be done each time the information is refreshed, or at some other time interval. One example where this may be necessary is the case of a liquid crystal display having the pixel structure shown in FIG. 2 or 3. The stored video information also represents the drive voltage on the liquid crystal. The driving voltage applied to the liquid crystal is usually periodically inverted to prevent deterioration of the liquid crystal material, so that the storage node driving circuit 56 inverts the voltage representing the video information every time the pixel is refreshed to accommodate this demand. It is convenient to arrange to

Another possible arrangement for the pixel circuit including the refresh function is shown in FIG. In this example, a separate display element drive circuit 58 is inserted between the display element 18 and the data storage node, which is a node 59 in which video information is stored. As shown, data storage capacitor 72 is associated with this node. This type of pixel structure can be applied to any liquid crystal display, but is most appropriate in situations where a display element cannot be used to store the charge representing the video information. One example of such a display is a display device using a light emitting diode such as, for example, an active matrix polymer LED or an organic LED (OLED) display device. In an alternative arrangement for this pixel, the input to the temporary storage circuit of the refresh circuit can be taken from the output of the display element driver circuit 58. This has the advantage of buffering the signal taken from the data storage node 59.

In the example described so far, it has been assumed that video information is stored in the form of the amount of charge retained in the capacitor in the pixel. In the simplest case, the video information represents one bit of digital data, which determines whether the pixel output is bright or dark. In principle, the number of values that video information can take can be increased by implementing a refresh circuit that can detect and restore the number of increased voltage levels. This causes each pixel 10 to be set to one of the plurality of gray levels in accordance with the stored video information.                 

An alternative method for realizing grayscale reproduction is to use a pixel design in which video information is stored in pixels in the form of a plurality of binary numbers as shown in FIG. This can be for example a liquid crystal display in which the display element electrode is divided into a plurality of binary weighted regions, denoted here by pixel capacitors D0, D1, and D2. By setting different display element regions to a dark state or a bright state, the average luminance of the pixels can be controlled to generate grayscale. Although the subdisplay elements of the display device can use the pixel structure shown in the previous figure, it is preferable to use one refresh circuit to refresh all the subpixel display elements so that the pixel circuits are not complicated. This can be realized using the multiplexer 60 connected between the refresh circuit 51 and the subdisplay element or data storage node. One example of how this can be done is shown in FIG. 6. In this case, it is not always necessary, but a multiplexer is also used while addressing the subdisplay elements. At least one auxiliary row electrode 61 is used to supply a video information bit control signal to the multiplexer 60; The number of auxiliary row electrodes required depends on the number of subdisplay elements.

Sharing of the refresh circuit 51 by insertion of the multiplexer 60 can also be extended to a pixel array each containing a single storage node. For example, each refresh circuit 51 may be shared between three adjacent groups of pixels, to reduce the overall complexity of the pixel circuits. The pixels also share a single connection with the column electrode so that when referring to FIG. 6 three display elements 18 represent as close as possible red, green and blue image information rather than three sub-elements. To be

7 illustrates one embodiment illustrating a method of transferring data to multiple capacitors 72 in each pixel. The plurality of column electrodes 16 are connected with respective capacitors 72 through respective TFTs 12, which are capacitors present in the circuit, such as separate capacitors or plate capacitors of liquid crystal elements. Can be. Each pixel includes a refresh circuit, a driver circuit, and a display circuit 74 including pixel elements. One example of display circuit 74 implementation will be described below. In use, the plurality of digital data bits are delivered to the pixel at the same time that the address line 14 is selected.

8 shows an alternative drive structure in which a plurality of address lines 14 are provided in each row to independently control the plurality of thin film transistors 12. In use, the address line 14 is each selected to deliver each successive bit sequentially to the pixel.

The first address line 80, the second address line 81, the third address line 82, and the fourth address line 83 each include the first capacitor 90, the second capacitor 91, and the first address line 83. Each TFT 12 driving the third capacitor 92 and the fourth capacitor 93 in turn is driven.

9 shows an alternative arrangement in which the arrangement of FIG. 8 is modified. Only one of the address TFTs 12, the select transistor 78 is connected with the column line, and the other TFT is connected in series with the select transistor 78. This structure significantly reduces the thermal capacitance as compared to the example of FIG. 8. Initially, the first, second, third, and fourth address lines 80, 81, 82, 83 are all selected to carry data, and the data is supplied along column line 16 to provide a fourth capacitor ( 93). The fourth address line 83 is then deselected, and additional data bits are applied to the column line 16 and written to the third capacitor 92. After deselecting the third address line 82, the second capacitor 91 may be written. Finally, the second address line 81 may be deselected so that only the first address line 80 remains selected and data is written to the first capacitor 90.

The disadvantage of the arrangement of FIG. 9 is that the final data storage capacitor 93 is driven in series through all the TFTs 12. This difficulty is addressed in the embodiment shown in FIG. 10 by providing a selection TFT 78 and an additional selection line 76. This arrangement again ensures that only one TFT, here the selection TFT 78, is connected to the column 16, while only two TFTs are placed in the path between the capacitor and the column line.

Two examples of pixel circuits for an active matrix liquid crystal display device incorporating a refresh circuit will now be described with reference to FIGS. 11 and 12, and this kind of pixel circuit and its operation manner will be described in more detail. Features of the circuit include a normal mode that is regularly addressed with new video information and has full grayscale performance, and a refresh mode that does not need to be addressed with new video information but can limit the number of gray levels. It can work.

The pixel circuits shown in FIGS. 11 and 12 represent an implementation of the two pixel structures shown previously in FIGS. 2 and 3, respectively. The addressing switch 50 is composed of an n-type TFT (T1) 12, and the pixel is addressed using video information from the column drive circuit 35 by taking the row address electrode 14 at a high voltage level. . The temporary storage circuit 55 of the refresh circuit 51 is composed of a p-type TFT (T2) 62 and a capacitor C _inv 66. Such capacitors represent capacitors at the nodes of the circuit and need not necessarily be implemented as separate physical capacitors. The capacitor may simply be configured as a capacitor of a node generated in the arrangement of pixels and an input capacitor of a storage node driving circuit. The gate of T2 62 is connected to the refresh electrode 52 that controls the refresh operation. The storage node driving circuit 56 is a CMOS inverter formed of TFT (T3) 63 and TFT (T4) 64, and also an output switching transistor (T5) 65 connected to the refresh control signal line 52. It is composed. C _LC represents the capacitor of the LC display element 18, and C _S represents the storage capacitor of the capacitor 72 connected with the display element electrode.

In short, the refresh operation is performed as follows. The refresh control signal is usually at a low level. In order to start the refresh operation, the refresh signal is taken at the high voltage level. The refresh signal turns off transistor T2 62 that insulates pixel capacitors 18, 72, C _LC , C _S from node capacitor C _inv 66. The data voltage present on the pixel capacitor at the beginning of the refresh process is now held at C _inv 66 for the refresh cycle duration. The inverter circuit generates a voltage at its output, which voltage represents an inverted logic state at the input of the inverter circuit. When the refresh signal goes high, the output transistor T5 65 is turned on, so that the pixel capacitor is charged to one voltage, which represents the inversion of the signal present at the start of the refresh operation. The ability of the inverter to recover the voltage level representing the video data means that any degradation of the stored voltage level present at the start of the refresh period is eliminated.

The operation of the pixel is further illustrated by the voltage waveform shown in FIG. FIG. 13 shows pixel voltage waveforms and driving waveforms associated with two vertically adjacent pixels, pixel n and pixel n + 1 in one column and row (n, n + 1) of the display device. Assume that the display device is initially addressed using a field inversion drive structure in which all pixels in the display are addressed using the same drive voltage polarity for one field period. In addition, it is assumed that a part of the driving voltage required for the liquid crystal is applied to the common electrode of the display device (common electrode driving structure). Vd is a video information (data) voltage signal waveform applied to the column electrode 16. Vs (n) and Vs (n + 1) are row drive voltage waveforms applied to the nth and (n + 1) th row electrodes 14, respectively. Vr is a refresh signal waveform applied to the refresh electrode 52.

FIG. 13 shows the video already present in the pixel, transitioning to the state where the pixel 10 is refreshed internally, with the display device addressed using an external video drive signal generated by the column drive circuit 35. Indicates to keep the information. During the period in which the pixel is driven externally, the column electrode 16 voltage is switched in accordance with the changing video information. Once the display device enters the internal refresh mode, the column electrodes 16 no longer need to be switched and can be connected to a near potential, for example grounded. Immediately after the end of the field where the pixel 10 is externally addressed, it is necessary to refresh the pixel first, which is realized by taking the voltage Vr on the refresh control electrode 52 at a high voltage level. In this example, it is possible to connect all of the refresh electrodes 52 of the display device with the same signal, but in other cases it may be necessary to provide one or more signals. The driving voltage applied to the common electrode V _COM of the display device must be switched while the LC pixel capacitor 18 is being charged in order for the common electrode driving structure to operate correctly. Therefore, this switching must be performed during the refresh period. It is important that the common electrode potential is not switched before refresh occurs, because the potential will change the voltage present at the input of the refresh circuit and it is no longer possible for the refresh circuit to detect the state of the video information. .

In the pixel circuits shown in FIGS. 11 and 12, it is possible to operate the pixel 10 in full grayscale mode by applying the appropriate analog voltage generated by the column drive circuit 35. These voltages are present at the input to the inverter circuit formed of T4 64 and T3 63. If an intermediate voltage level is applied at the input of the CMOS inverter, significant current can come from the power supply of the circuit. However, it is desirable to avoid this because it significantly increases the power consumption of the display device. One way to avoid this is to equalize the voltages applied to VDD and VSS when the display device is operating in normal grayscale mode. Alternatively, one or more TFTs can be connected in series with the power line of the inverter, and these TFTs are turned off when the intermediate voltage is supplied to the pixels by the column drive circuit 35.

Figure 14 shows a circuit for avoiding the problem of increased power consumption of the inverter circuit due to the intermediate input voltage level when operating the circuit in non-refresh grayscale mode. The two n-type TFTs 180 and 182 are directly controlled by the refresh line 52 and are connected in series with the p-type TFTs 63 and 64. The two n-type TFTs 180 and 182 thus replace the TFT T5 of FIG. The n-type TFTs 180 and 182 are only turned on when the refresh signal is high, and are not turned on when the pixel is operating in grayscale mode.

An additional feature of the pixel circuits shown in Figs. 11, 12 and 14 is that it is possible to read video data on the column electrode 16 during the refresh operation. This is realized by turning on the transistors T1 12 when the refresh control signal is at a high level.

11, 12, and 14 are inverted form. That is, when the digital data is refreshed, the logic state of the data is reversed. It is not always desirable to perform this inversion. Various non-inverted refresh structures will now be discussed with reference to FIGS. 15-17. In general, these circuits do not change the logic level indicated by the voltage on the data storage capacitor, but simply compensate for any deterioration in the voltage level that may occur because the data is finally refreshed. different. This typically means that no temporary storage circuitry is needed, but it can be seen that temporary storage circuitry can still be used if available.

15 shows a simple non-inverting refresh circuit. The circuit is simply composed of a pair of cross-connected CMOS inverters 110 and 112 connected to the corresponding data storage node 72 via the TFT 12. The first CMOS inverter 110 has an input terminal connected to the switch 12 and an output terminal connected to the input terminal of the second CMOS inverter 112. The output terminal of the second CMOS inverter 112 is connected to the switch 12. Thus, when one switch formed by one of the TFTs 12 is closed, the data on the corresponding storage node 72 drives the first inverter 110 and the second inverter 112, thereby storing the storage node 72. To recharge to the nominal level.

16 shows an alternative implementation of the first inverter 110 and the second inverter 112. The TFT 184 is controlled by a signal (/ refresh) taken at a low level while refreshing to turn on the TFT 184 and power the cross-connect inverters 110 and 112. The transistor 184 minimizes the current flow between the power lines VDD and VSS when the refresh operation is not performed.

Transistor sizing and design of the circuits of FIGS. 15 and 16 ensure that the cross-connected inverters 110 and 112 adopt the logic state of the data storage node rather than impose its initial state on the data storage node 72. Is selected.

17 shows an alternative non-inverting refresh circuit that mitigates this design constraint. The second inverter 112 is connected to the switch 12 and thus to the storage node 72 via an additional refresh TFT 114 controlled by the additional refresh line 116. In use, the additional refresh line 116 may be driven with some delay after closing one of the switches 12 allowing the inverters 110 and 112 to switch, connecting the output stage to drive the storage node 72. Before this, the correct voltage at the output terminal of the second inverter 112 can be ensured.

The refresh apparatus for pixel circuits having a plurality of bits stored separately will now be described. One way is to provide separate refresh circuits for each bit.

One alternative is to multiplex the refresh circuit. 6 shows one example of such an alternative. FIG. 18 is an extension of the circuit of FIG. 10 with a refresh circuit 51 driven by a refresh line 52 connected to each TFT 12 along the same drive line 102 driven by a selection TFT 78. Indicates. The display circuit 100 does not include a refresh circuit, unlike the display circuit 74 of FIGS. 6 to 10.

The data storage capacitor 72 maintains the select line 76 in a non-selected state and selects one of the address lines 14 to select one of the capacitors 72 through the corresponding TFT 12. , Can be refreshed individually. The refresh line 52 may then be selected to cause the refresh circuit 51 to refresh the selected one of the capacitors. The other capacitors may be selected sequentially.

Digital data can be used to provide a drive signal to a pixel element either directly or by a pixel drive circuit. The pixel driving circuit may include some form of D / A converter circuit. Data may be simultaneously transferred to the pixel element or the driving circuit. There are a plurality of ways in which a plurality of storage bits can set the gray level of a pixel, including, for example, a method of implementing a digital-to-analog (D / A) converter in each pixel.

In some cases, however, it may be desirable to transfer data in series to the pixel driver circuit, for example using the circuitry shown in FIG. 19. The display and refresh circuit 74 is sequentially connected with each data storage capacitor 72 under the control of the address line 14. A refresh operation may occur simultaneously with transferring data to the pixel element or the pixel driving circuit.

A specific example of multi-bit refresh within a pixel is shown in FIG. 20, which uses a 4-bit serial charge redistributed digital-to-analog conversion. The driving line 102 is connected to the liquid crystal capacitor 18 through the first auxiliary TFT 124 and the inverter 120 and also the second auxiliary TFT 122. The first auxiliary TFT 124 and the second auxiliary TFT 122 have opposite conductivity types, and are each connected with the refresh line 52.

In use, one of the data storage capacitors 72 is selected, and upon selection of the refresh line 52, the first auxiliary TFT 124 connects the drive line 102 with the liquid crystal element 18 through the inverter 120. . When the refresh line 52 is deselected, the second auxiliary TFT 122 connects the output terminal of the inverter 120 again to refresh the selected capacitor 72. The circuit serves as an inverting refresh circuit. Further details of the plurality of liquid crystal elements 18 are provided in US5448258 and US5923311 which are incorporated herein by reference.

21 shows a further example of a multi-bit refresh design, in this case a parallel design that is different from the serial design of FIG. 20. The switching transistor 138 controlled by the voltage on each capacitor 72 includes a first weight capacitor 130, a second weight capacitor 132, a third weight capacitor 134, and a fourth weight capacitor 136. To the ground line 140. The first weight capacitor 130, the second weight capacitor 132, the third weight capacitor 134, and the fourth weight capacitor 136 each have capacitance in a ratio of substantially 1: 2: 4: 8. , Unit capacitance may be designated by the sign (C _C ). The other ends of the first to fourth weighting capacitors 130, 132, 134, and 136 are connected in parallel with the liquid crystal element 18. The reset transistor 142 controlled by the reset line 144 connects the fixed voltage line 140 with the liquid crystal element 18.

In use, the line 140 is connected to the reference voltage VREF, which is convenient if the voltage is conveniently the same as the voltage connected to the storage capacitor 72, but need not necessarily be the same. A rectangular wave is applied to the common electrode VCOM of the display. Just before the voltage on the common electrode is switched, the voltage on the display element is reset to the same level as the voltage level on the line 140 by simply turning on the TFT 142. When the common electrode voltage VCOM is switched, the voltage appearing on the liquid crystal element 18 is determined by the parallel coupling of the potential divider formed by the liquid crystal capacitor 18 and the selected weighting capacitors 130, 132, 134 and 136. Thus, part of the common electrode voltage change appearing on the display element 18 depends on the conduction state of the TFT 138 and the value of the digital data stored in the capacitor 72. Just before the common electrode voltage VCOM is switched back to its initial value, the voltage will be maintained on the display element until the display element voltage is reset again using the TFT 142. Thus, the total capacitance of the selected weighting capacitor can be changed between 15C C _C and _C by selecting one or all of the weighting capacitors.

22 and 23 illustrate one embodiment using an alternative method using a shift register like structure. FIG. 22 shows a single register unit, and FIG. 23 shows an embodiment in which these four circuits are connected to each other.

As shown in FIG. 22, the register unit 170 has a data input terminal 156 for the capacitor 72 connected to the first TFT 152 controlled by the first clock 162, and the data input terminal Is sequentially connected to the output terminal 160 through the second TFT 154 and the inverter 150. The output terminal 160 is in turn connected to the capacitor 72 through the refresh data line 158 and the refresh transistor 50 controlled by the refresh line 52.

23 shows four units 170 connected together in series with a common first clock 162, a second clock 164, and a refresh line 52.                 

In use, the data input 156 may be connected to the column electrode. The first clock 162 is selected to apply data on the data input terminal 156 to the capacitor 72 via the first TFT 152. The second clock 164 may be selected to deliver the signal through the second TFT 154 and the inverter 150 to the next unit.

If the data is not delivered quickly enough through the chain of units 170, the second clock 164 may be periodically pulsed to refresh the data to deliver a signal on the capacitor 72 to the input of the inverter 150. There is a need. Thereafter, the refresh signal goes high to pass the output signal from the inverter 150 to the refresh line 158 and the refresh TFT 50 to invert the signal on the capacitor 72.

The transmission waveform in this arrangement is shown in FIG. In input step 172, data is sequentially transferred onto capacitor 72. In storage step 174, data remains on the capacitor and is refreshed periodically.

In the stop mode, it is also possible for some pixels in the array to operate using data stored in pixels, while other pixels operate simultaneously using data supplied by an external signal source. This can be realized without the need to modify the pixel circuits by simply driving the display with the appropriate signal. This method can minimize power consumption.

For example, while a portion of the display represents a moving picture, the remaining portion of the display may represent a still background. The external video source needs to provide data to the display only for the image area representing the moving image, thereby saving power.

By modifying the pixel circuits and connecting them to the refresh control inputs of the pixels, different display regions can be arranged to operate in different modes. For example, the center region can display moving images, and the edge region can display still images stored in pixels.

Other pixel circuits can also be used to implement refreshing of data within a pixel or group of pixels. For example, the CMOS inverter may be replaced with a clocked CMOS inverter, a ratioized NMOS or PMOS inverter, or a ratioless NMOS or PMOS inverter. Other methods of performing the refresh operation are also conceivable, for example, a structure in which the data storage node is precharged and then discharged if appropriate. It is also possible to detect and refresh multiple pixel voltage levels.

The proposed refresh circuit-mounted pixel can be applied to other active matrix array devices that need to store information in the matrix. The application in the display device is more advantageous because the method can stop addressing the display element with new video information when low power consumption is required.

As noted above, the principle is, for example, an active matrix LED display device such as the device described in EP-A-1116205 (PHB 34351), the contents of which are incorporated herein by reference, and electrochromic. It can also be used in other kinds of active matrix devices such as electrophoretic, and electroluminescent display devices.                 

The same kind of theory as described above in connection with display pixels can be advantageously used in other matrix array devices in which data is stored in matrix elements.

For example, an array of electromechanical actuators may similarly benefit from the long term data storage performance provided by the refresh circuit integrated within the array element in the manner described above.

Similarly, active matrix transducer devices may also benefit.

The method can also be applied to a sensor comprising an array of sensing elements, for example, which can preferably be stored locally in the device before the output of each sensor element is read slightly later. By inserting a local refresh circuit into the sensing element, the time between the sensing operation from the array element and the data read is no longer limited. Examples of such devices include, for example, optical image sensing array devices as described in US-A-5349174, and capacitive fingerprint detection devices as described in US-A-5325442. It is incorporated herein by reference.

Numerous other modifications and variations will be apparent to those skilled in the art from this specification. Such modifications and variations may include other features that may be used in place of, or in addition to, features already known in the art and already disclosed herein.

As mentioned above, the present invention is applicable to an active matrix array device comprising an array of matrix elements.

Claims (17)

An active matrix device comprising an array of matrix elements, the matrix elements each having at least one storage node having a capacitor for dynamically storing data in the form of charges stored in the capacitor, wherein the matrix element comprises data stored in the storage node. Further comprising a refresh circuit for refreshing, And wherein said refresh circuit comprises a pair of cross-connected inverters. 2. The active matrix of claim 1, wherein the refresh circuit comprises a temporary storage circuit for storing data in at least one storage node and a storage node driving circuit for driving the storage node according to data stored in the temporary storage circuit. Device. The active matrix device of claim 2, wherein the storage node driving circuit comprises an inverter for driving at least one storage node by using an inverted value of data stored in the temporary storage circuit. 4. The active matrix device according to any one of claims 1 to 3, further comprising a refresh line activating the refresh circuit to refresh the storage node. The active matrix device of claim 1, wherein each storage node comprises a capacitor. 4. A storage device as claimed in claim 2 or 3, wherein each matrix element comprises an address switch controlled by an address line and connected between a column line and at least one data storage node, the storage switch connecting the storage node with the temporary storage circuit. And a refresh switch connecting the storage node with the storage node driving circuit, wherein the storage switch and the refresh switch include a first setting in which the storage switch is opened and the refresh switch is closed, and the storage switch is closed and the refresh switch is closed. An active matrix device having a control terminal connected with a common refresh line to switch between the second settings in which the switch is opened. The method of claim 6, Wherein said matrix element comprises a plurality of data storage capacitors each storing a plurality of data bits per matrix element. 8. The active matrix device of claim 7, comprising a plurality of row address lines controlling a plurality of address thin film transistors associated with each data storage capacitor to select one or more of the data storage capacitors. The method of claim 8, And the plurality of address thin film transistors are connected to a common driving line connected to the column line through a select transistor, wherein the select transistor is controlled by a select line. 10. The active matrix device of claim 9, further comprising a refresh line that controls the refresh circuit to couple the refresh circuit with the common drive line to refresh a selected data storage capacitor. delete The method of claim 7, wherein Each matrix element comprises a plurality of register units connected in series, each register unit comprises a data storage node, and a subsequent register unit connected with the register unit comprises drive means for driving the next register unit, At least one clock line is provided to control data transfer along the plurality of register units connected in series. 13. The active matrix of claim 12, wherein in each register unit, the output of the drive means is coupled back to the storage node to refresh data stored in the storage node, such that the drive means constitutes the refresh circuit. Device. The method according to any one of claims 1 to 3, And said matrix element is a display pixel for displaying an image pixel according to data stored in said storage node. The method according to any one of claims 1 to 3, And said matrix element is a pixel electrode for controlling liquid crystal. A method of operating an active matrix device having a matrix element comprising a capacitor type storage node, the method comprising: Storing image data as charge in the storage node; And Displaying the stored image data and periodically applying a refresh signal to the refresh circuit in the matrix element to cause a refresh circuit to refresh the image data stored in the storage node. Operating the matrix device, And wherein said refresh circuit comprises a pair of cross-connected inverters. 17. The method of claim 16, further comprising operating the active matrix device in a normal mode, comprising regularly addressing matrix elements using fresh video information and displaying the video information. Operating method of the active matrix device.

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