KR20020052569A - 반도체패키지용 회로기판의 도전성볼 융착 방법 - Google Patents
반도체패키지용 회로기판의 도전성볼 융착 방법 Download PDFInfo
- Publication number
- KR20020052569A KR20020052569A KR1020000081963A KR20000081963A KR20020052569A KR 20020052569 A KR20020052569 A KR 20020052569A KR 1020000081963 A KR1020000081963 A KR 1020000081963A KR 20000081963 A KR20000081963 A KR 20000081963A KR 20020052569 A KR20020052569 A KR 20020052569A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive ball
- circuit board
- ball
- laser beam
- conductive
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
Claims (7)
- 반도체패키지용 회로기판의 랜드에 일정량의 플럭스를 돗팅하고, 상기 플럭스에 납이 함유되지 않은 도전성볼을 임시로 부착한 후, 상기 도전성볼을 융용시켜 상기 도전성볼을 랜드에 융착하는 반도체패키지용 회로기판의 도전성볼 융착 방법에 있어서,상기 도전성볼에는 레이저빔을 입사하여 융용시킴으로써, 상기 도전성볼을 랜드에 융착함을 특징으로 하는 반도체패키지용 회로기판의 도전성볼 융착 방법.
- 제1항에 있어서, 상기 회로기판 상면에는 상기 도전성볼이 상부로 노출되도록 다수의 홀이 형성된 마스크가 더 위치된 것을 특징으로 하는 반도체패키지용 회로기판의 도전성볼 융착 방법.
- 제1항에 있어서, 상기 레이저빔은 상기 도전성볼에 대략 200~280℃ 이상의 온도가 제공되는 세기(Intensity)인 것을 특징으로 하는 반도체패키지용 회로기판의 도전성볼 융착 방법.
- 제1항에 있어서, 상기 레이저빔은 도전성볼에만 간헐적으로 입사됨을 특징으로 하는 반도체패키지용 회로기판의 도전성볼 융착 방법.
- 제1항에 있어서, 상기 레이저빔을 입사하는 공정중에는 불활성기체를 제공하여 도전성볼의 산화가 방지되도록 함을 특징으로 하는 반도체패키지용 회로기판의 도전성볼 융착 방법.
- 제1항에 있어서, 상기 레이저빔은 다수의 도전성볼에 순차적으로 입사되도록, 상기 레이저빔을 반사시키는 미러가 더 이용됨을 특징으로 하는 반도체패키지용 회로기판의 도전성볼 융착 방법.
- 제5항에 있어서, 상기 미러는 갈바닉(Galvanic) 미러 또는 폴리곤(Polygon) 미러가 이용됨을 특징으로 하는 반도체패키지용 회로기판의 도전성볼 융착 방법.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0081963A KR100384337B1 (ko) | 2000-12-26 | 2000-12-26 | 반도체패키지용 회로기판의 도전성볼 융착 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2000-0081963A KR100384337B1 (ko) | 2000-12-26 | 2000-12-26 | 반도체패키지용 회로기판의 도전성볼 융착 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20020052569A true KR20020052569A (ko) | 2002-07-04 |
KR100384337B1 KR100384337B1 (ko) | 2003-05-16 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR10-2000-0081963A KR100384337B1 (ko) | 2000-12-26 | 2000-12-26 | 반도체패키지용 회로기판의 도전성볼 융착 방법 |
Country Status (1)
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KR (1) | KR100384337B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100919931B1 (ko) * | 2007-11-06 | 2009-10-07 | 엘에스산전 주식회사 | 레이저 솔더링 장치 및 방법과 이를 이용한 전력용 반도체모듈의 제조방법 |
KR101154013B1 (ko) * | 2009-07-10 | 2012-06-15 | 주식회사 엘티에스 | 라인 빔을 이용한 반도체 패키지의 솔더링 시스템 및 방법 |
-
2000
- 2000-12-26 KR KR10-2000-0081963A patent/KR100384337B1/ko active IP Right Grant
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100919931B1 (ko) * | 2007-11-06 | 2009-10-07 | 엘에스산전 주식회사 | 레이저 솔더링 장치 및 방법과 이를 이용한 전력용 반도체모듈의 제조방법 |
KR101154013B1 (ko) * | 2009-07-10 | 2012-06-15 | 주식회사 엘티에스 | 라인 빔을 이용한 반도체 패키지의 솔더링 시스템 및 방법 |
Also Published As
Publication number | Publication date |
---|---|
KR100384337B1 (ko) | 2003-05-16 |
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