KR102541861B1 - 리소-에칭가능 층에 브리지를 포함하는 통합 디바이스 패키지 - Google Patents

리소-에칭가능 층에 브리지를 포함하는 통합 디바이스 패키지 Download PDF

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KR102541861B1
KR102541861B1 KR1020187004859A KR20187004859A KR102541861B1 KR 102541861 B1 KR102541861 B1 KR 102541861B1 KR 1020187004859 A KR1020187004859 A KR 1020187004859A KR 20187004859 A KR20187004859 A KR 20187004859A KR 102541861 B1 KR102541861 B1 KR 102541861B1
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die
layer
bridge
integrated device
encapsulation
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KR20180044905A (ko
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시쿤 구
홍복 위
재식 이
동욱 김
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퀄컴 인코포레이티드
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    • H01L23/5385—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H01L23/3128—
    • H01L23/481—
    • H01L23/5383—
    • H01L23/5384—
    • H01L24/13—
    • H01L24/16—
    • H01L24/32—
    • H01L24/92—
    • H01L25/0655—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/616—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips
    • H10W70/618—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together package substrates, interposers or redistribution layers combined with bridge chips the bridge chips being embedded in the package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
KR1020187004859A 2015-08-21 2016-06-03 리소-에칭가능 층에 브리지를 포함하는 통합 디바이스 패키지 Active KR102541861B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/832,363 US9368450B1 (en) 2015-08-21 2015-08-21 Integrated device package comprising bridge in litho-etchable layer
US14/832,363 2015-08-21
PCT/US2016/035895 WO2017034641A1 (en) 2015-08-21 2016-06-03 Integrated device package comprising bridge in litho-etchable layer

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KR20180044905A KR20180044905A (ko) 2018-05-03
KR102541861B1 true KR102541861B1 (ko) 2023-06-08

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US (1) US9368450B1 (enExample)
EP (1) EP3338303B1 (enExample)
JP (1) JP6748186B2 (enExample)
KR (1) KR102541861B1 (enExample)
CN (1) CN107924905B (enExample)
BR (1) BR112018003233B1 (enExample)
CA (1) CA2991933C (enExample)
WO (1) WO2017034641A1 (enExample)

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9583426B2 (en) 2014-11-05 2017-02-28 Invensas Corporation Multi-layer substrates suitable for interconnection between circuit modules
US10283492B2 (en) 2015-06-23 2019-05-07 Invensas Corporation Laminated interposers and packages with embedded trace interconnects
US10438881B2 (en) * 2015-10-29 2019-10-08 Marvell World Trade Ltd. Packaging arrangements including high density interconnect bridge
US10163856B2 (en) * 2015-10-30 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked integrated circuit structure and method of forming
US9852994B2 (en) * 2015-12-14 2017-12-26 Invensas Corporation Embedded vialess bridges
US11089689B2 (en) * 2016-04-02 2021-08-10 Intel Corporation Fine feature formation techniques for printed circuit boards
US20170287838A1 (en) 2016-04-02 2017-10-05 Intel Corporation Electrical interconnect bridge
US11508662B2 (en) * 2016-09-30 2022-11-22 Intel Corporation Device and method of very high density routing used with embedded multi-die interconnect bridge
US11277922B2 (en) * 2016-10-06 2022-03-15 Advanced Micro Devices, Inc. Circuit board with bridge chiplets
KR102666151B1 (ko) * 2016-12-16 2024-05-17 삼성전자주식회사 반도체 패키지
US11004824B2 (en) 2016-12-22 2021-05-11 Intel Corporation Scalable embedded silicon bridge via pillars in lithographically defined vias, and methods of making same
US20180240778A1 (en) * 2017-02-22 2018-08-23 Intel Corporation Embedded multi-die interconnect bridge with improved power delivery
US10468374B2 (en) 2017-03-31 2019-11-05 Intel Corporation Die interconnect substrates, a semiconductor device and a method for forming a die interconnect substrate
US11476185B2 (en) 2017-04-01 2022-10-18 Intel Corporation Innovative way to design silicon to overcome reticle limit
US10593563B2 (en) * 2017-04-13 2020-03-17 Invensas Corporation Fan-out wafer level package with resist vias
US10403599B2 (en) 2017-04-27 2019-09-03 Invensas Corporation Embedded organic interposers for high bandwidth
US11233025B2 (en) * 2017-05-31 2022-01-25 Futurewei Technologies, Inc. Merged power pad for improving integrated circuit power delivery
US10943869B2 (en) 2017-06-09 2021-03-09 Apple Inc. High density interconnection using fanout interposer chiplet
US10727198B2 (en) 2017-06-30 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and method manufacturing the same
US10373893B2 (en) * 2017-06-30 2019-08-06 Intel Corporation Embedded bridge with through-silicon vias
US10622311B2 (en) * 2017-08-10 2020-04-14 International Business Machines Corporation High-density interconnecting adhesive tape
KR102069659B1 (ko) 2017-08-31 2020-01-23 해성디에스 주식회사 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판
US10658281B2 (en) * 2017-09-29 2020-05-19 Intel Corporation Integrated circuit substrate and method of making
US10867954B2 (en) * 2017-11-15 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect chips
US10784202B2 (en) * 2017-12-01 2020-09-22 International Business Machines Corporation High-density chip-to-chip interconnection with silicon bridge
US10651126B2 (en) * 2017-12-08 2020-05-12 Applied Materials, Inc. Methods and apparatus for wafer-level die bridge
DE112017008336T5 (de) * 2017-12-29 2020-09-17 Intel Corporation Mikroelektronische Anordnungen
US11508663B2 (en) * 2018-02-02 2022-11-22 Marvell Israel (M.I.S.L) Ltd. PCB module on package
KR102101712B1 (ko) * 2018-03-21 2020-04-21 (주)심텍 브릿지 기판을 포함하는 인쇄회로기판
US10742217B2 (en) 2018-04-12 2020-08-11 Apple Inc. Systems and methods for implementing a scalable system
US11088123B1 (en) * 2018-05-15 2021-08-10 Marvell Israel (M.I.S.L) Ltd. Package system having laterally offset and ovelapping chip packages
US20200020634A1 (en) * 2018-07-16 2020-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Package and method of manufacturing the same
KR102560697B1 (ko) * 2018-07-31 2023-07-27 삼성전자주식회사 인터포저를 가지는 반도체 패키지
CN110896066B (zh) * 2018-09-13 2022-08-30 欣兴电子股份有限公司 具有内埋基板的线路载板及其制作方法与芯片封装结构
US10937762B2 (en) * 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US10916494B2 (en) * 2019-01-02 2021-02-09 Qualcomm Incorporated Device comprising first solder interconnects aligned in a first direction and second solder interconnects aligned in a second direction
US12205877B2 (en) 2019-02-21 2025-01-21 AT&S(Chongqing) Company Limited Ultra-thin component carrier having high stiffness and method of manufacturing the same
CN111599687B (zh) * 2019-02-21 2022-11-15 奥特斯科技(重庆)有限公司 具有高刚度的超薄部件承载件及其制造方法
US11164818B2 (en) 2019-03-25 2021-11-02 Intel Corporation Inorganic-based embedded-die layers for modular semiconductive devices
TWI707408B (zh) * 2019-04-10 2020-10-11 力成科技股份有限公司 天線整合式封裝結構及其製造方法
US10998262B2 (en) * 2019-04-15 2021-05-04 Intel Corporation Stripped redistrubution-layer fabrication for package-top embedded multi-die interconnect bridge
CN114144875B (zh) 2019-06-10 2026-02-10 马维尔以色列(M.I.S.L.)有限公司 具有顶侧存储器模块的ic封装
US12341129B2 (en) * 2019-06-13 2025-06-24 Intel Corporation Substrateless double-sided embedded multi-die interconnect bridge
TW202111907A (zh) 2019-09-05 2021-03-16 力成科技股份有限公司 以矽中介層作為互連橋的封裝晶片結構
US11393759B2 (en) * 2019-10-04 2022-07-19 International Business Machines Corporation Alignment carrier for interconnect bridge assembly
DE102020119181A1 (de) 2019-10-29 2021-04-29 Taiwan Semiconductor Manufacturing Co., Ltd. Halbleiterpackages und verfahren zu deren herstellung
US11164817B2 (en) * 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
CN110911384A (zh) * 2019-12-19 2020-03-24 中国电子科技集团公司第五十八研究所 一种嵌入式无源桥接芯片及其应用
US12261124B2 (en) 2019-12-23 2025-03-25 Intel Corporation Embedded die architecture and method of making
US11309246B2 (en) * 2020-02-05 2022-04-19 Apple Inc. High density 3D interconnect configuration
US11605594B2 (en) * 2020-03-23 2023-03-14 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect integrated device coupled to the substrate
US11302643B2 (en) * 2020-03-25 2022-04-12 Intel Corporation Microelectronic component having molded regions with through-mold vias
KR102854175B1 (ko) 2020-07-31 2025-09-03 삼성전기주식회사 인쇄회로기판 및 그 제조방법
CN112435981B (zh) * 2020-09-30 2024-12-10 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
US12355000B2 (en) 2020-11-10 2025-07-08 Qualcomm Incorporated Package comprising a substrate and a high-density interconnect integrated device
US12327797B2 (en) 2020-12-16 2025-06-10 Intel Corporation Microelectronic structures including glass cores
CN112736031A (zh) * 2020-12-23 2021-04-30 海光信息技术股份有限公司 转接板及其制作方法，半导体器件及其制作方法
US12469811B2 (en) 2021-03-26 2025-11-11 Qualcomm Incorporated Package comprising wire bonds coupled to integrated devices
US12205939B2 (en) 2021-03-26 2025-01-21 Samsung Electronics Co., Ltd. Semiconductor package
US11791270B2 (en) * 2021-05-10 2023-10-17 International Business Machines Corporation Direct bonded heterogeneous integration silicon bridge
KR20230001574A (ko) 2021-06-28 2023-01-05 삼성전자주식회사 반도체 패키지
US20230035627A1 (en) * 2021-07-27 2023-02-02 Qualcomm Incorporated Split die integrated circuit (ic) packages employing die-to-die (d2d) connections in die-substrate standoff cavity, and related fabrication methods
CN114050145A (zh) * 2021-10-25 2022-02-15 日月光半导体制造股份有限公司 半导体封装结构及其制造方法
US20230130354A1 (en) * 2021-10-27 2023-04-27 Advanced Micro Devices, Inc. Three-dimensional semiconductor package having a stacked passive device
CN118202460A (zh) * 2021-11-05 2024-06-14 美商艾德亚半导体接合科技有限公司 多沟道器件堆叠
US11848273B2 (en) 2021-11-17 2023-12-19 International Business Machines Corporation Bridge chip with through via
CN114284242A (zh) * 2021-11-30 2022-04-05 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
KR20230089156A (ko) * 2021-12-13 2023-06-20 삼성전기주식회사 브리지를 포함하는 기판 및 전자 장치
US12424560B2 (en) * 2021-12-14 2025-09-23 Advanced Micro Devices, Inc. Semiconductor chip device
CN114203691B (zh) * 2021-12-14 2025-09-02 华进半导体封装先导技术研发中心有限公司 一种多芯片高密度互连封装结构及其制作方法
US20230317618A1 (en) * 2022-03-29 2023-10-05 Intel Corporation Glass bridge for connecting dies
US12463178B2 (en) * 2022-07-03 2025-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor die assembly having a polygonal linking die
KR102898555B1 (ko) * 2022-07-05 2025-12-09 한병준 브릿지를 이용한 팬아웃 패키징 소자 및 브릿지를 이용한 팬아웃 패키징 소자의 제조방법
CN115312497A (zh) * 2022-07-20 2022-11-08 南通越亚半导体有限公司 多芯片互连封装结构及其制作方法
US20240063094A1 (en) * 2022-08-19 2024-02-22 Micron Technology, Inc. Semiconductor device assemblies with a cavity exposing through-silicon vias for controller attachment
US20240103065A1 (en) * 2022-09-27 2024-03-28 International Business Machines Corporation Active bridge for chiplet and module inter-communication
CN115547843A (zh) * 2022-09-28 2022-12-30 上海为旌科技有限公司 高密度互连转接板、封装结构及其制作方法
CN117995806A (zh) * 2022-10-31 2024-05-07 奥特斯奥地利科技与系统技术有限公司 封装件和制造封装件的方法
US20240282729A1 (en) * 2023-02-20 2024-08-22 Qualcomm Incorporated Package dies including vertical interconnects for signal and power distribution in a three-dimensional (3d) integrated circuit (ic) package
CN116504651A (zh) * 2023-03-28 2023-07-28 华天科技（昆山）电子有限公司 硅桥嵌入三维互联封装结构的制造方法及其结构
CN120883372A (zh) * 2023-04-04 2025-10-31 哈纳米克罗恩公司 半导体封装及其制造方法
CN119447096A (zh) * 2023-08-04 2025-02-14 星科金朋私人有限公司 半导体器件及其形成方法
KR102898567B1 (ko) * 2023-09-25 2025-12-09 실리콘박스 피티이 엘티디 반도체 패키지용 인터커넥션 모듈 기판과 이를 포함하는 반도체 패키지 소자 및 이들의 제조 방법
JP2025088548A (ja) * 2023-11-30 2025-06-11 Ｒａｐｉｄｕｓ株式会社 電子装置
JP2025088549A (ja) * 2023-11-30 2025-06-11 Ｒａｐｉｄｕｓ株式会社 電子装置
WO2025262765A1 (ja) * 2024-06-17 2025-12-26 Ａｓｔｅｍｏ株式会社 半導体装置の製造方法、半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140021583A1 (en) 2012-07-18 2014-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US20140264791A1 (en) 2013-03-14 2014-09-18 Mathew J. Manusharow Direct external interconnect for embedded interconnect bridge package
US20140360759A1 (en) * 2013-06-05 2014-12-11 Ibiden Co., Ltd. Wiring board and method for manufacturing the same

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4581768B2 (ja) 2005-03-16 2010-11-17 ソニー株式会社 半導体装置の製造方法
US8064224B2 (en) * 2008-03-31 2011-11-22 Intel Corporation Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same
US7969009B2 (en) 2008-06-30 2011-06-28 Qualcomm Incorporated Through silicon via bridge interconnect
KR101479506B1 (ko) 2008-06-30 2015-01-07 삼성전자주식회사 임베디드 배선 기판, 이를 포함하는 반도체 패키지 및 그제조 방법
US8227904B2 (en) * 2009-06-24 2012-07-24 Intel Corporation Multi-chip package and method of providing die-to-die interconnects in same
CN102742367B (zh) * 2010-07-23 2015-04-22 欣兴电子股份有限公司 线路板及其制造方法
US8097490B1 (en) 2010-08-27 2012-01-17 Stats Chippac, Ltd. Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
US8288209B1 (en) * 2011-06-03 2012-10-16 Stats Chippac, Ltd. Semiconductor device and method of using leadframe bodies to form openings through encapsulant for vertical interconnect of semiconductor die
TWI476888B (zh) * 2011-10-31 2015-03-11 欣興電子股份有限公司 嵌埋穿孔中介層之封裝基板及其製法
TWI528876B (zh) * 2012-03-22 2016-04-01 矽品精密工業股份有限公司 中介板及其電性測試方法
US8872349B2 (en) * 2012-09-11 2014-10-28 Intel Corporation Bridge interconnect with air gap in package assembly
US8866287B2 (en) * 2012-09-29 2014-10-21 Intel Corporation Embedded structures for package-on-package architecture
US9190380B2 (en) * 2012-12-06 2015-11-17 Intel Corporation High density substrate routing in BBUL package
US9119313B2 (en) 2013-04-25 2015-08-25 Intel Corporation Package substrate with high density interconnect design to capture conductive features on embedded die
US9147638B2 (en) * 2013-07-25 2015-09-29 Intel Corporation Interconnect structures for embedded bridge
EP3058586B1 (en) * 2013-10-16 2020-11-11 Intel Corporation Integrated circuit package substrate
US9642259B2 (en) * 2013-10-30 2017-05-02 Qualcomm Incorporated Embedded bridge structure in a substrate
KR101815489B1 (ko) * 2014-02-26 2018-01-05 인텔 코포레이션 스루 브리지 도전성 비아 신호 접속에 의한 임베딩된 멀티디바이스 브리지

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140021583A1 (en) 2012-07-18 2014-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Package structures including a capacitor and methods of forming the same
US20140264791A1 (en) 2013-03-14 2014-09-18 Mathew J. Manusharow Direct external interconnect for embedded interconnect bridge package
US20140360759A1 (en) * 2013-06-05 2014-12-11 Ibiden Co., Ltd. Wiring board and method for manufacturing the same

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