KR102540941B1 - 가상 반도체 디바이스 제조 환경에서 키 파라미터 식별, 프로세스 모델 캘리브레이션 및 가변성 분석을 위한 시스템 및 방법 - Google Patents

가상 반도체 디바이스 제조 환경에서 키 파라미터 식별, 프로세스 모델 캘리브레이션 및 가변성 분석을 위한 시스템 및 방법 Download PDF

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KR102540941B1
KR102540941B1 KR1020180069418A KR20180069418A KR102540941B1 KR 102540941 B1 KR102540941 B1 KR 102540941B1 KR 1020180069418 A KR1020180069418 A KR 1020180069418A KR 20180069418 A KR20180069418 A KR 20180069418A KR 102540941 B1 KR102540941 B1 KR 102540941B1
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윌리엄 제이 이건
케네스 비. 그라이너
데이비드 엠. 프라이드
안슈만 쿤와르
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코벤터, 인크.
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/20—Design optimisation, verification or simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
    • G06F3/0481—Interaction techniques based on graphical user interfaces [GUI] based on specific properties of the displayed interaction object or a metaphor-based environment, e.g. interaction with desktop elements like windows or icons, or assisted by a cursor's changing behaviour or appearance
    • G06F3/04815—Interaction with a metaphor-based environment or interaction object displayed as three-dimensional [3D], e.g. changing the user viewpoint with respect to the environment or object
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/048—Interaction techniques based on graphical user interfaces [GUI]
    • G06F3/0484—Interaction techniques based on graphical user interfaces [GUI] for the control of specific functions or operations, e.g. selecting or manipulating an object, an image or a displayed text element, setting a parameter value or selecting a range
    • G06F3/04847—Interaction techniques to control parameter settings, e.g. interaction with sliders or dials
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/31—Design entry, e.g. editors specifically adapted for circuit design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T19/00—Manipulating three-dimensional [3D] models or images for computer graphics
    • G06T19/20—Editing of three-dimensional [3D] images, e.g. changing shapes or colours, aligning objects or positioning parts
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/10—Numerical modelling
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/18—Details relating to CAD techniques using virtual or augmented reality
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00—Indexing scheme for image data processing or generation, in general
    • G06T2200/16—Indexing scheme for image data processing or generation, in general involving adaptation to the client's capabilities
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2219/00—Indexing scheme for manipulating 3D models or images for computer graphics
    • G06T2219/20—Indexing scheme for editing of 3D models
    • G06T2219/2004—Aligning objects, relative positioning of parts

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  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
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  • Computer Hardware Design (AREA)
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  • Software Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
KR1020180069418A 2017-06-18 2018-06-18 가상 반도체 디바이스 제조 환경에서 키 파라미터 식별, 프로세스 모델 캘리브레이션 및 가변성 분석을 위한 시스템 및 방법 Active KR102540941B1 (ko)

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KR1020230070992A KR102659980B1 (ko) 2017-06-18 2023-06-01 가상 반도체 디바이스 제조 환경에서 키 파라미터 식별, 프로세스 모델 캘리브레이션 및 변동성 분석을 위한 시스템 및 방법

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US201762521506P 2017-06-18 2017-06-18
US62/521,506 2017-06-18
US201862631022P 2018-02-15 2018-02-15
US62/631,022 2018-02-15

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KR1020230070992A Active KR102659980B1 (ko) 2017-06-18 2023-06-01 가상 반도체 디바이스 제조 환경에서 키 파라미터 식별, 프로세스 모델 캘리브레이션 및 변동성 분석을 위한 시스템 및 방법
KR1020240052031A Active KR102848559B1 (ko) 2017-06-18 2024-04-18 가상 반도체 디바이스 제조 환경에서 키 파라미터 식별, 프로세스 모델 캘리브레이션 및 변동성 분석을 위한 시스템 및 방법

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KR1020240052031A Active KR102848559B1 (ko) 2017-06-18 2024-04-18 가상 반도체 디바이스 제조 환경에서 키 파라미터 식별, 프로세스 모델 캘리브레이션 및 변동성 분석을 위한 시스템 및 방법

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US (3) US11144701B2 (https=)
JP (3) JP7097757B2 (https=)
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Families Citing this family (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11144701B2 (en) 2017-06-18 2021-10-12 Coventor, Inc. System and method for key parameter identification, process model calibration and variability analysis in a virtual semiconductor device fabrication environment
KR102580012B1 (ko) * 2018-02-16 2023-09-18 코벤터, 인크. 충진 분율 복셀 데이터 (fill-fraction voxel data) 로부터 복수 재료 메시 생성을 위한 시스템 및 방법
US10794839B2 (en) * 2019-02-22 2020-10-06 Kla Corporation Visualization of three-dimensional semiconductor structures
US10580615B2 (en) * 2018-03-06 2020-03-03 Globalfoundries Inc. System and method for performing failure analysis using virtual three-dimensional imaging
SG11202105438XA (en) * 2018-11-26 2021-06-29 Agency Science Tech & Res Method and system for predicting performance in electronic design based on machine learning
US11182688B2 (en) * 2019-01-30 2021-11-23 International Business Machines Corporation Producing a formulation based on prior distributions of a number of ingredients used in the formulation
WO2020169355A1 (en) 2019-02-20 2020-08-27 Asml Netherlands B.V. A method for characterizing a manufacturing process of semiconductor devices
CN111832123A (zh) * 2019-03-29 2020-10-27 晶乔科技股份有限公司 半导体元件的工艺开发方法以及系统
GB2582932B (en) 2019-04-08 2022-07-27 Arrival Ltd System and method for flexible manufacturing
US11010532B2 (en) 2019-04-29 2021-05-18 Samsung Electronics Co., Ltd. Simulation method and system
US12423486B2 (en) 2019-05-10 2025-09-23 Coventor, Inc. System and method for process window optimization in a virtual semiconductor device fabrication environment
CN110135492B (zh) * 2019-05-13 2020-12-22 山东大学 基于多高斯模型的设备故障诊断与异常检测方法及系统
CN110135090B (zh) * 2019-05-21 2020-10-09 北京航空航天大学 一种基于响应面法的电路系统容差建模与分析方法
JP7469337B2 (ja) * 2019-06-18 2024-04-16 テトラ ラバル ホールディングス アンド ファイナンス エス エイ 液体食品のための包装容器における逸脱の検出
US11156991B2 (en) 2019-06-24 2021-10-26 Nanotronics Imaging, Inc. Predictive process control for a manufacturing process
US20210049242A1 (en) * 2019-08-13 2021-02-18 International Business Machines Corporation Process Optimization by Clamped Monte Carlo Distribution
US11017147B2 (en) * 2019-08-30 2021-05-25 Siemens Industry Software Inc. Edge-based camera for characterizing semiconductor layout designs
KR102822697B1 (ko) 2019-10-08 2025-06-23 삼성전자주식회사 반도체 메모리 장치, 전자 장치, 및 그것의 설정 방법
US12153401B2 (en) * 2019-11-06 2024-11-26 Nanotronics Imaging, Inc. Systems, methods, and media for manufacturing processes
CN112784522A (zh) * 2019-11-07 2021-05-11 科文托尔公司 用于在虚拟制造环境中执行回流焊建模的系统和方法
TWI740313B (zh) * 2019-12-18 2021-09-21 新加坡商鴻運科股份有限公司 虛擬量測方法、裝置及電腦可讀存儲介質
US11126159B2 (en) * 2020-01-09 2021-09-21 Siemens Industry Software Inc. Multi-objective calibrations of lithography models
JP7325356B2 (ja) * 2020-02-20 2023-08-14 東京エレクトロン株式会社 情報処理システム及びシミュレーション方法
CN115803642A (zh) * 2020-07-09 2023-03-14 特克特朗尼克公司 自动协助电路验证
KR20230042056A (ko) * 2020-07-17 2023-03-27 코벤터, 인크. 반도체 디바이스 가상 제조 환경에서 사양 한계들을 결정하는 시스템들 및 방법들
CN111814406B (zh) * 2020-07-27 2022-08-09 太原理工大学 一种多晶硅原料重要度分析方法及系统
US12443840B2 (en) * 2020-10-09 2025-10-14 Kla Corporation Dynamic control of machine learning based measurement recipe optimization
WO2022081840A1 (en) * 2020-10-14 2022-04-21 Coventor, Inc. System and method for performing deformation and stress analysis modeling in a virtual fabrication environment
TWI758979B (zh) 2020-11-30 2022-03-21 財團法人工業技術研究院 適應性搜尋空間調整的參數最佳化系統與方法及應用其之使用者介面
DE102020215718A1 (de) * 2020-12-11 2022-06-15 Robert Bosch Gesellschaft mit beschränkter Haftung Vorrichtung und Verfahren zur kontinuierlichen Prozessoptimierung bei einer Herstellung von Halbleiterbauelementen
US20220207602A1 (en) * 2020-12-24 2022-06-30 Fidelity Information Services, Llc Systems and methods for analyzing financial product utilization
US11687694B1 (en) * 2021-03-31 2023-06-27 Cadence Design Systems, Inc. Method, product, and system for automated, guided, and region-based layer density balancing
US12001197B2 (en) * 2021-04-14 2024-06-04 Applied Materials, Inc. Eco-efficiency (sustainability) dashboard for semiconductor manufacturing
CN113191017B (zh) * 2021-05-21 2022-12-27 成都数之联科技股份有限公司 虚拟量测模型构建方法、虚拟量测方法、系统、电子设备及计算机可读存储介质
CN113447251B (zh) * 2021-06-16 2022-07-26 南京航空航天大学 一种涡轮发动机支撑结构稳健性度量方法
US20220414305A1 (en) * 2021-06-29 2022-12-29 Synopsys, Inc. Modeling effects of process variations on superconductor and semiconductor devices using measurements of physical devices
CN113326849B (zh) * 2021-07-20 2022-01-11 广东魅视科技股份有限公司 一种可视化数据采集方法及系统
US12182487B2 (en) 2021-08-30 2024-12-31 Siemens Industry Software Inc. Controllable pattern clustering for characterized semiconductor layout designs
JP7742763B2 (ja) * 2021-12-02 2025-09-22 株式会社日立製作所 設計条件計算システム、及び半導体装置の製造方法
US12228905B2 (en) 2021-12-10 2025-02-18 Applied Materials, Inc. Eco-efficiency monitoring and exploration platform for semiconductor manufacturing
CN116414890A (zh) * 2021-12-29 2023-07-11 中芯国际集成电路制造(北京)有限公司 一种晶圆分组实验结果的分析系统及分析方法
TWI806412B (zh) * 2022-02-08 2023-06-21 中華精測科技股份有限公司 標記產品全域高點的方法
US20230402283A1 (en) * 2022-06-09 2023-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating mask
CN115034098A (zh) * 2022-08-11 2022-09-09 深圳市信润富联数字科技有限公司 风电算法模型验证方法、装置、设备及存储介质
CN115758859A (zh) * 2022-09-29 2023-03-07 中国辐射防护研究院 一种关键参数不确定性分析校准方法、存储介质及系统
EP4645201A1 (en) * 2022-12-27 2025-11-05 The University of Osaka Critical process parameter analysis method, critical process parameter analysis device, and critical process parameter analysis program
CN116306452B (zh) * 2023-05-17 2023-08-08 华芯程(杭州)科技有限公司 一种光刻胶参数获取方法及装置、电子设备
CN116796701B (zh) * 2023-08-28 2023-12-19 宁波联方电子科技有限公司 一种器件测试单元结构自动化实现装置和方法
US12518069B2 (en) * 2023-09-08 2026-01-06 Applied Materials, Inc. Comprehensive modeling platform for manufacturing equipment
CN117237434B (zh) * 2023-11-15 2024-02-09 太原理工大学 一种h型钢尺寸测量方法及装置
WO2025131245A1 (en) * 2023-12-19 2025-06-26 Carl Zeiss Digital Innovation Gmbh Method and manufacturing installation for producing a workpiece
CN118133054B (zh) * 2024-01-18 2024-10-18 韶关朗正数据半导体有限公司 一种半导体加工工艺控制方法
WO2025183905A1 (en) * 2024-02-26 2025-09-04 Lam Research Corporation Performing fabrication process simulations
US20250370353A1 (en) * 2024-05-31 2025-12-04 Applied Materials, Inc. Enhanced run-to-run process control modeling platform
WO2025250914A1 (en) * 2024-05-31 2025-12-04 Lam Research Corporation Process navigator for doe results checking in virtual fabrication platform

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006178907A (ja) 2004-12-24 2006-07-06 Matsushita Electric Ind Co Ltd 回路シミュレーション方法および装置
US20090249263A1 (en) 2008-03-28 2009-10-01 Fujitsu Microelectronics Limited Semiconductor circuit design method and semiconductor circuit manufacturing method
US20120239178A1 (en) 2011-03-15 2012-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Device performance parmeter tuning method and system
US20170039308A1 (en) 2015-08-03 2017-02-09 Synopsys, Inc. Pre-Silicon Design Rule Evaluation

Family Cites Families (71)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0536832A (ja) 1991-02-26 1993-02-12 Toshiba Corp 論理セルの並列配置処理方法
JP3426647B2 (ja) 1992-06-24 2003-07-14 日本電信電話株式会社 ３次元トポグラフィシミュレーションのための一般化されたソリッドモデリング
US5473710A (en) 1993-10-08 1995-12-05 Industrial Technology Research Institute Controlled tapered angle etching process for fabricating optical integrated circuits
JPH07115071A (ja) * 1993-10-15 1995-05-02 Hitachi Ltd 半導体装置の設計方法
JPH08107050A (ja) 1994-09-30 1996-04-23 Sony Corp 半導体プロセス工程における断面形状のシミュレーション方法
US6116766A (en) 1997-04-15 2000-09-12 Maseeh; Fariborz Fabrication based computer aided design system using virtual fabrication techniques
JP2002110489A (ja) 2000-09-26 2002-04-12 Toshiba Corp 半導体装置の回路特性のシミュレータ、及び、シミュレート方法
JP4798866B2 (ja) * 2001-04-05 2011-10-19 Ｏｋｉセミコンダクタ株式会社 回路シミュレーション用パラメータ抽出方法
US7136796B2 (en) 2002-02-28 2006-11-14 Timbre Technologies, Inc. Generation and use of integrated circuit profile-based simulation information
JP2003345854A (ja) 2002-05-23 2003-12-05 Mitsubishi Electric Corp デザインルール作成システム
US7492364B2 (en) 2002-07-23 2009-02-17 Imagecom, Inc. System and method for creating and updating a three-dimensional model and creating a related neutral file format
JP3926296B2 (ja) * 2003-06-24 2007-06-06 株式会社ルネサステクノロジ 半導体集積回路の性能分散系算出装置及びその算出方法
US8296687B2 (en) 2003-09-30 2012-10-23 Tokyo Electron Limited System and method for using first-principles simulation to analyze a process performed by a semiconductor processing tool
US7155689B2 (en) 2003-10-07 2006-12-26 Magma Design Automation, Inc. Design-manufacturing interface via a unified model
US7194709B2 (en) 2004-03-05 2007-03-20 Keith John Brankner Automatic alignment of integrated circuit and design layout of integrated circuit to more accurately assess the impact of anomalies
WO2005103819A2 (en) 2004-04-20 2005-11-03 Litel Instruments Method of emulation of lithographic projection tools
JP4428175B2 (ja) 2004-09-14 2010-03-10 株式会社Ｓｕｍｃｏ 気相エピタキシャル成長装置および半導体ウェーハの製造方法
JP4627674B2 (ja) * 2005-03-24 2011-02-09 株式会社山武 データ処理方法及びプログラム
US7526739B2 (en) 2005-07-26 2009-04-28 R3 Logic, Inc. Methods and systems for computer aided design of 3D integrated circuits
JP5147167B2 (ja) * 2005-07-29 2013-02-20 キヤノン株式会社 決定方法及びプログラム
WO2007019269A2 (en) 2005-08-08 2007-02-15 Brion Technologies, Inc. System and method for creating a focus-exposure model of a lithography process
US7359759B2 (en) 2005-10-31 2008-04-15 Taiwan Semiconductor Manufacturing Company Method and system for virtual metrology in semiconductor manufacturing
JP4627268B2 (ja) 2006-02-21 2011-02-09 富士通株式会社 ３次元デバイスシミュレーションプログラムおよび３次元デバイスシミュレーションシステム
JP2008034714A (ja) 2006-07-31 2008-02-14 Fujitsu Ltd デバイス製造支援装置、そのシミュレーション方法、デバイス製造装置
US7373215B2 (en) 2006-08-31 2008-05-13 Advanced Micro Devices, Inc. Transistor gate shape metrology using multiple data sources
JP2008112383A (ja) 2006-10-31 2008-05-15 Fujitsu Ltd 半導体集積回路設計方法、および設計プログラム
JP4333799B2 (ja) 2007-03-20 2009-09-16 ソニー株式会社 半導体集積回路の設計方法、半導体集積回路の設計装置、記録媒体、およびマスク製造方法
GB2482076B (en) 2007-05-16 2012-08-22 Seereal Technologies Sa Communications system including a holographic display
JP4996366B2 (ja) 2007-06-28 2012-08-08 株式会社東芝 ３次元構造データ作成装置
US20090024377A1 (en) 2007-07-16 2009-01-22 Sung-Ki Min System and Method for Modeling Semiconductor Devices Using Pre-Processing
EP2223245B1 (en) 2007-11-30 2011-07-20 Coventor, Inc. System and method for three-dimensional schematic capture and result visualization of multi-physics system models
DE102008016424B4 (de) 2008-03-31 2011-06-01 Amd Fab 36 Limited Liability Company & Co. Kg Verfahren mit einem Bilden einer Kontaktloshöffnung und eines Grabens in einer dielektrischen Schicht mit kleinem ε
JP5288894B2 (ja) 2008-06-09 2013-09-11 株式会社東芝 半導体装置の製造管理方法
US20100269084A1 (en) 2008-11-24 2010-10-21 Yuri Granik Visibility and Transport Kernels for Variable Etch Bias Modeling of Optical Lithography
JP2010165827A (ja) 2009-01-15 2010-07-29 Renesas Electronics Corp 半導体装置の設計方法、及び、設計プログラム
US8606774B1 (en) * 2009-05-18 2013-12-10 Google Inc. Methods and systems for 3D shape retrieval
US20110185323A1 (en) 2009-08-21 2011-07-28 William Matthew Hogan Stacked Integracted Circuit Verification
JP2011113291A (ja) * 2009-11-26 2011-06-09 Fujitsu Semiconductor Ltd 半導体装置の動作シミュレーション方法、測定データ取得方法、及び回路設計方法
US8219355B2 (en) 2009-12-23 2012-07-10 Cadence Design Systems, Inc. Methods and systems for high sigma yield estimation
US20110289472A1 (en) 2010-05-19 2011-11-24 International Business Machines Corporation Layout quality evaluation
US8557613B2 (en) 2010-06-14 2013-10-15 California Institute Of Technology Methods for designing, fabricating, and predicting shape formations in a material
US8273610B2 (en) 2010-11-18 2012-09-25 Monolithic 3D Inc. Method of constructing a semiconductor device and structure
US8674315B2 (en) * 2010-11-12 2014-03-18 Siemens Medical Solutions Usa, Inc. Method and apparatus for using image cumulative distribution function for tomographic reconstruction quality control
TWI430125B (zh) 2011-01-31 2014-03-11 國立交通大學 半導體元件之參數萃取方法
TW201243765A (en) 2011-04-18 2012-11-01 Hon Hai Prec Ind Co Ltd Three-dimensional effect simulation system and method
US8490244B1 (en) 2012-04-16 2013-07-23 International Business Machines Corporation Methodologies for automatic 3-D device structure synthesis from circuit layouts for device simulation
US8924909B2 (en) 2012-06-13 2014-12-30 Purdue Research Foundation Microelectromechanical system design and layout
KR102004852B1 (ko) * 2012-11-15 2019-07-29 삼성전자 주식회사 컴퓨팅 시스템을 이용한 반도체 패키지 디자인 시스템 및 방법, 상기 시스템을 포함하는 반도체 패키지 제조 장치, 상기 방법으로 디자인된 반도체 패키지
US9965577B2 (en) 2013-03-14 2018-05-08 Coventor, Inc. System and method for performing directed self-assembly in a 3-D virtual fabrication environment
US10242142B2 (en) 2013-03-14 2019-03-26 Coventor, Inc. Predictive 3-D virtual fabrication system and method
US8959464B2 (en) 2013-03-14 2015-02-17 Coventor, Inc. Multi-etch process using material-specific behavioral parameters in 3-D virtual fabrication environment
US9317632B2 (en) 2013-03-14 2016-04-19 Coventor, Inc. System and method for modeling epitaxial growth in a 3-D virtual fabrication environment
US8832620B1 (en) 2013-03-14 2014-09-09 Coventor, Inc. Rule checks in 3-D virtual fabrication environment
JP6509225B2 (ja) 2013-12-11 2019-05-08 ケーエルエー−テンカー コーポレイション 要件に対するターゲット及びプロセス感度の分析
EP2891997A1 (en) * 2014-01-06 2015-07-08 Fujitsu Limited Methods and apparatus for including a confidential structural component in a third party remote product simulation
WO2015112979A1 (en) * 2014-01-26 2015-07-30 Coventor, Inc. Modeling pattern dependent effects for a 3-d virtual semiconductor fabrication environment
TWI624765B (zh) * 2014-04-14 2018-05-21 Asml Netherlands B. V. 用以改良微影程序之電腦實施方法及電腦程式產品
CN103970954B (zh) * 2014-05-13 2017-01-25 温州大学 一种基于鲁棒设计的高密度集成电路封装的优化方法
JP6318897B2 (ja) * 2014-06-17 2018-05-09 富士通株式会社 ポストレイアウト回路の歩留まり検証方法、歩留まり検証プログラム及び歩留まり検証装置
US10204188B2 (en) 2015-03-13 2019-02-12 Samsung Electronics Co., Ltd. Systems, methods and computer program products for analyzing performance of semiconductor devices
JP2017037441A (ja) 2015-08-07 2017-02-16 株式会社東芝 プロセスシミュレータ、レイアウトエディタ及びシミュレーションシステム
JP6477423B2 (ja) 2015-11-02 2019-03-06 オムロン株式会社 製造プロセスの予測システムおよび予測制御システム
EP3279735A1 (en) 2016-08-01 2018-02-07 ASML Netherlands B.V. Metrology method and apparatus, computer program and lithographic system
US20180095936A1 (en) 2016-10-05 2018-04-05 Board Of Regents, The University Of Texas System Optimizing a manufacturing or fabrication process using an integrated bayesian statistics and continuum model approach
US11144701B2 (en) 2017-06-18 2021-10-12 Coventor, Inc. System and method for key parameter identification, process model calibration and variability analysis in a virtual semiconductor device fabrication environment
KR102578644B1 (ko) 2017-08-30 2023-09-13 삼성전자주식회사 반도체 집적회로의 수율 예측 장치, 및 이를 이용한 반도체 장치 제조 방법
DE102017220872B4 (de) 2017-11-22 2022-02-03 Carl Zeiss Smt Gmbh Verfahren und System zur Qualifizierung einer Maske für die Mikrolithographie
US12423486B2 (en) 2019-05-10 2025-09-23 Coventor, Inc. System and method for process window optimization in a virtual semiconductor device fabrication environment
KR20230042056A (ko) 2020-07-17 2023-03-27 코벤터, 인크. 반도체 디바이스 가상 제조 환경에서 사양 한계들을 결정하는 시스템들 및 방법들
US20220198333A1 (en) 2020-12-18 2022-06-23 Applied Materials, Inc. Recipe optimization through machine learning
US12450520B2 (en) 2021-03-01 2025-10-21 Hitachi High-Tech Corporation Experiment point recommendation device, experiment point recommendation method, and semiconductor device manufacturing device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006178907A (ja) 2004-12-24 2006-07-06 Matsushita Electric Ind Co Ltd 回路シミュレーション方法および装置
US20090249263A1 (en) 2008-03-28 2009-10-01 Fujitsu Microelectronics Limited Semiconductor circuit design method and semiconductor circuit manufacturing method
US20120239178A1 (en) 2011-03-15 2012-09-20 Taiwan Semiconductor Manufacturing Co., Ltd. Device performance parmeter tuning method and system
US20170039308A1 (en) 2015-08-03 2017-02-09 Synopsys, Inc. Pre-Silicon Design Rule Evaluation

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