KR102323389B1 - 튜닝가능한 선택도를 갖는 등방성 실리콘 및 실리콘-게르마늄 에칭 - Google Patents

튜닝가능한 선택도를 갖는 등방성 실리콘 및 실리콘-게르마늄 에칭 Download PDF

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KR102323389B1
KR102323389B1 KR1020187028266A KR20187028266A KR102323389B1 KR 102323389 B1 KR102323389 B1 KR 102323389B1 KR 1020187028266 A KR1020187028266 A KR 1020187028266A KR 20187028266 A KR20187028266 A KR 20187028266A KR 102323389 B1 KR102323389 B1 KR 102323389B1
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silicon
layer
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germanium
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KR20180112869A (ko
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숩하딥 칼
엔 타필리 칸다바라
애런 모스덴
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도쿄엘렉트론가부시키가이샤
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H01L21/30608
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32357Generation remote from the workpiece, e.g. down-stream
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32715Workpiece holder
    • H01J37/32724Temperature
    • H01L21/0228
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    • HELECTRICITY
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901Materials
    • H10P14/2902Materials being Group IVA materials
    • H10P14/2905Silicon, silicon germanium or germanium
    • HELECTRICITY
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H10P14/6532Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour by exposure to a plasma
    • HELECTRICITY
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P36/00Gettering within semiconductor bodies
    • HELECTRICITY
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    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/20Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00Etching of wafers, substrates or parts of devices
    • H10P50/60Wet etching
    • H10P50/64Wet etching of semiconductor materials
    • H10P50/642Chemical etching
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    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/014Manufacture or treatment of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/40FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/43FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
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    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
    • H10D62/118Nanostructure semiconductor bodies
    • H10D62/119Nanowire, nanosheet or nanotube semiconductor bodies
    • H10D62/121Nanowire, nanosheet or nanotube semiconductor bodies oriented parallel to substrates

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
KR1020187028266A 2016-03-02 2017-03-02 튜닝가능한 선택도를 갖는 등방성 실리콘 및 실리콘-게르마늄 에칭 Active KR102323389B1 (ko)

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Application Number Priority Date Filing Date Title
US201662302584P 2016-03-02 2016-03-02
US201662302587P 2016-03-02 2016-03-02
US62/302,584 2016-03-02
US62/302,587 2016-03-02
PCT/US2017/020503 WO2017151958A1 (en) 2016-03-02 2017-03-02 Isotropic silicon and silicon-germanium etching with tunable selectivity

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KR20180112869A KR20180112869A (ko) 2018-10-12
KR102323389B1 true KR102323389B1 (ko) 2021-11-05

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US (1) US9984890B2 (https=)
JP (1) JP6827633B2 (https=)
KR (1) KR102323389B1 (https=)
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WO (1) WO2017151958A1 (https=)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6692202B2 (ja) * 2016-04-08 2020-05-13 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US10141189B2 (en) * 2016-12-29 2018-11-27 Asm Ip Holding B.V. Methods for forming semiconductors by diffusion
US10043674B1 (en) * 2017-08-04 2018-08-07 Applied Materials, Inc. Germanium etching systems and methods
US10685887B2 (en) * 2017-12-04 2020-06-16 Tokyo Electron Limited Method for incorporating multiple channel materials in a complimentary field effective transistor (CFET) device
US10714391B2 (en) * 2017-12-04 2020-07-14 Tokyo Electron Limited Method for controlling transistor delay of nanowire or nanosheet transistor devices
KR102823628B1 (ko) * 2018-05-08 2025-06-20 램 리써치 코포레이션 텔레센트릭 (tele-centric) 렌즈, 광학 빔 폴딩 어셈블리, 또는 다각형 스캐너를 갖는 렌즈 회로를 포함하는 원자 층 에칭 및 증착 프로세싱 시스템들
JP7072440B2 (ja) * 2018-05-16 2022-05-20 東京エレクトロン株式会社 シリコン含有膜のエッチング方法、コンピュータ記憶媒体、及びシリコン含有膜のエッチング装置
US10923356B2 (en) * 2018-07-20 2021-02-16 Tokyo Electron Limited Gas phase etch with controllable etch selectivity of silicon-germanium alloys
WO2020042254A1 (zh) * 2018-08-28 2020-03-05 中国科学院微电子研究所 一种高精度的刻蚀方法
CN112789710B (zh) * 2018-10-03 2025-03-04 朗姆研究公司 纳米线的选择性蚀刻
WO2020172208A1 (en) * 2019-02-20 2020-08-27 Tokyo Electron Limited Method for selective etching at an interface between materials
US10892158B2 (en) * 2019-04-01 2021-01-12 Hitachi High-Tech Corporation Manufacturing method of a semiconductor device and a plasma processing apparatus
TW202125622A (zh) 2019-08-28 2021-07-01 美商得昇科技股份有限公司 使用氟自由基處理工件的方法
JP7345334B2 (ja) 2019-09-18 2023-09-15 東京エレクトロン株式会社 エッチング方法及び基板処理システム
US12165848B2 (en) 2019-10-29 2024-12-10 Tokyo Electron Limited Substrate processing method, substrate processing apparatus, and method for producing nanowire or nanosheet transistor
JP7653666B2 (ja) * 2020-03-10 2025-03-31 パナソニックIpマネジメント株式会社 電子部品のクリーニング方法および素子チップの製造方法
JP7360979B2 (ja) * 2020-03-19 2023-10-13 東京エレクトロン株式会社 基板処理方法及び基板処理装置
US11424120B2 (en) * 2021-01-22 2022-08-23 Tokyo Electron Limited Plasma etching techniques
US11482423B2 (en) * 2021-01-28 2022-10-25 Tokyo Electron Limited Plasma etching techniques
US11538690B2 (en) * 2021-02-09 2022-12-27 Tokyo Electron Limited Plasma etching techniques
JP7771835B2 (ja) * 2021-05-31 2025-11-18 東京エレクトロン株式会社 基板処理方法及び基板処理装置
JP7803047B2 (ja) * 2021-06-15 2026-01-21 東京エレクトロン株式会社 エッチング方法及びエッチング装置
WO2022264380A1 (ja) * 2021-06-17 2022-12-22 株式会社日立ハイテク プラズマ処理方法および半導体装置の製造方法
FR3125915A1 (fr) * 2021-10-07 2023-02-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de gravure selective isotrope de silicium
US12272558B2 (en) * 2022-05-09 2025-04-08 Tokyo Electron Limited Selective and isotropic etch of silicon over silicon-germanium alloys and dielectrics; via new chemistry and surface modification
US12261053B2 (en) * 2022-08-10 2025-03-25 Tokyo Electron Limited Substrate processing with selective etching
US12512327B2 (en) 2022-09-15 2025-12-30 Tokyo Electron Limited Surface modification to achieve selective isotropic etch
US20240321584A1 (en) * 2023-03-22 2024-09-26 Applied Materials, Inc. Selective oxidation processes for gate-all-around transistors
CN116741630B (zh) * 2023-08-14 2023-12-22 北京北方华创微电子装备有限公司 干法刻蚀方法和半导体工艺设备
WO2025128543A1 (en) * 2023-12-15 2025-06-19 Lam Research Corporation Tunable selective lateral etch of silicon using radical species
FR3165338A1 (fr) 2024-07-31 2026-02-06 Soitec Procédé de fabrication d’un substrat de silicium en vue d’applications quantiques
WO2026062821A1 (ja) * 2024-09-19 2026-03-26 株式会社日立ハイテク エッチング方法および半導体装置の製造方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080108171A1 (en) 2006-09-20 2008-05-08 Rogers John A Release strategies for making transferable semiconductor structures, devices and device components
US20130267046A1 (en) 2012-04-09 2013-10-10 Zvi Or-Bach Method for fabrication of a semiconductor device and structure
US20140308816A1 (en) 2011-10-07 2014-10-16 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US20150126040A1 (en) 2013-11-04 2015-05-07 Applied Materials, Inc. Silicon germanium processing
US20150364603A1 (en) 2014-06-16 2015-12-17 International Business Machines Corporation Finfet and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858532B2 (en) * 2002-12-10 2005-02-22 International Business Machines Corporation Low defect pre-emitter and pre-base oxide etch for bipolar transistors and related tooling
KR100670782B1 (ko) 2004-11-09 2007-01-17 한국전자통신연구원 상변화 메모리 소자의 제조방법
JP2007056336A (ja) * 2005-08-25 2007-03-08 Tokyo Electron Ltd 基板処理装置,基板処理装置の基板搬送方法,プログラム,プログラムを記録した記録媒体
JP2007266455A (ja) * 2006-03-29 2007-10-11 Tokyo Electron Ltd 基板処理装置、基板処理方法及び記憶媒体
US20110061810A1 (en) * 2009-09-11 2011-03-17 Applied Materials, Inc. Apparatus and Methods for Cyclical Oxidation and Etching
US20120083127A1 (en) * 2010-09-30 2012-04-05 Tokyo Electron Limited Method for forming a pattern and a semiconductor device manufacturing method
KR101244953B1 (ko) 2011-07-18 2013-03-18 (재)한국나노기술원 전류 저지층 구조의 수직형 발광다이오드 소자 및 그 제조방법
US20140273525A1 (en) 2013-03-13 2014-09-18 Intermolecular, Inc. Atomic Layer Deposition of Reduced-Leakage Post-Transition Metal Oxide Films
US9576809B2 (en) * 2013-11-04 2017-02-21 Applied Materials, Inc. Etch suppression with germanium
US9613822B2 (en) * 2014-09-25 2017-04-04 Applied Materials, Inc. Oxide etch selectivity enhancement

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080108171A1 (en) 2006-09-20 2008-05-08 Rogers John A Release strategies for making transferable semiconductor structures, devices and device components
US20140308816A1 (en) 2011-10-07 2014-10-16 Applied Materials, Inc. Selective etch of silicon by way of metastable hydrogen termination
US20130267046A1 (en) 2012-04-09 2013-10-10 Zvi Or-Bach Method for fabrication of a semiconductor device and structure
US20150126040A1 (en) 2013-11-04 2015-05-07 Applied Materials, Inc. Silicon germanium processing
US20150364603A1 (en) 2014-06-16 2015-12-17 International Business Machines Corporation Finfet and nanowire semiconductor devices with suspended channel regions and gate structures surrounding the suspended channel regions

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JP2019507505A (ja) 2019-03-14
TWI625785B (zh) 2018-06-01
TW201738955A (zh) 2017-11-01
KR20180112869A (ko) 2018-10-12
WO2017151958A1 (en) 2017-09-08
US20170271165A1 (en) 2017-09-21
JP6827633B2 (ja) 2021-02-10
US9984890B2 (en) 2018-05-29

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