KR102223697B1 - 패키지 디바이스 칩의 제조 방법 - Google Patents

패키지 디바이스 칩의 제조 방법 Download PDF

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Publication number
KR102223697B1
KR102223697B1 KR1020170111659A KR20170111659A KR102223697B1 KR 102223697 B1 KR102223697 B1 KR 102223697B1 KR 1020170111659 A KR1020170111659 A KR 1020170111659A KR 20170111659 A KR20170111659 A KR 20170111659A KR 102223697 B1 KR102223697 B1 KR 102223697B1
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KR
South Korea
Prior art keywords
groove
wafer
package
mold resin
manufacturing
Prior art date
Application number
KR1020170111659A
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English (en)
Korean (ko)
Other versions
KR20180027356A (ko
Inventor
유타 요시다
Original Assignee
가부시기가이샤 디스코
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Application filed by 가부시기가이샤 디스코 filed Critical 가부시기가이샤 디스코
Publication of KR20180027356A publication Critical patent/KR20180027356A/ko
Application granted granted Critical
Publication of KR102223697B1 publication Critical patent/KR102223697B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
KR1020170111659A 2016-09-05 2017-09-01 패키지 디바이스 칩의 제조 방법 KR102223697B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2016-172886 2016-09-05
JP2016172886A JP6719341B2 (ja) 2016-09-05 2016-09-05 パッケージデバイスチップの製造方法

Publications (2)

Publication Number Publication Date
KR20180027356A KR20180027356A (ko) 2018-03-14
KR102223697B1 true KR102223697B1 (ko) 2021-03-04

Family

ID=61531634

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020170111659A KR102223697B1 (ko) 2016-09-05 2017-09-01 패키지 디바이스 칩의 제조 방법

Country Status (4)

Country Link
JP (1) JP6719341B2 (zh)
KR (1) KR102223697B1 (zh)
CN (1) CN107799468B (zh)
TW (1) TWI713100B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202343559A (zh) * 2019-04-05 2023-11-01 日商東京威力科創股份有限公司 基板處理系統

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053033A (ja) 1999-08-12 2001-02-23 Texas Instr Japan Ltd 半導体装置のダイシング方法
JP2002100709A (ja) 2000-09-21 2002-04-05 Hitachi Ltd 半導体装置及びその製造方法
JP2013074021A (ja) 2011-09-27 2013-04-22 Disco Abrasive Syst Ltd アライメント方法
US20130149841A1 (en) 2011-12-08 2013-06-13 International Business Machines Corporation Wafer dicing employing edge region underfill removal
JP2014053358A (ja) 2012-09-05 2014-03-20 Disco Abrasive Syst Ltd ウエーハの加工方法
JP2015018967A (ja) 2013-07-11 2015-01-29 富士通セミコンダクター株式会社 半導体装置の製造方法および支持基板付きウェハ
JP2015159136A (ja) 2014-02-21 2015-09-03 株式会社ディスコ Ｃｓｐウエーハの加工方法
JP2016015438A (ja) 2014-07-03 2016-01-28 株式会社ディスコ アライメント方法
JP5926632B2 (ja) 2012-06-28 2016-05-25 株式会社ディスコ 半導体チップの樹脂封止方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009224659A (ja) * 2008-03-18 2009-10-01 Disco Abrasive Syst Ltd ワークの分割方法
JP6339828B2 (ja) * 2014-03-13 2018-06-06 株式会社ディスコ ウエーハの加工方法

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001053033A (ja) 1999-08-12 2001-02-23 Texas Instr Japan Ltd 半導体装置のダイシング方法
JP2002100709A (ja) 2000-09-21 2002-04-05 Hitachi Ltd 半導体装置及びその製造方法
JP2013074021A (ja) 2011-09-27 2013-04-22 Disco Abrasive Syst Ltd アライメント方法
US20130149841A1 (en) 2011-12-08 2013-06-13 International Business Machines Corporation Wafer dicing employing edge region underfill removal
JP5926632B2 (ja) 2012-06-28 2016-05-25 株式会社ディスコ 半導体チップの樹脂封止方法
JP2014053358A (ja) 2012-09-05 2014-03-20 Disco Abrasive Syst Ltd ウエーハの加工方法
JP2015018967A (ja) 2013-07-11 2015-01-29 富士通セミコンダクター株式会社 半導体装置の製造方法および支持基板付きウェハ
JP2015159136A (ja) 2014-02-21 2015-09-03 株式会社ディスコ Ｃｓｐウエーハの加工方法
JP2016015438A (ja) 2014-07-03 2016-01-28 株式会社ディスコ アライメント方法

Also Published As

Publication number Publication date
JP6719341B2 (ja) 2020-07-08
TWI713100B (zh) 2020-12-11
CN107799468A (zh) 2018-03-13
JP2018041764A (ja) 2018-03-15
CN107799468B (zh) 2022-12-06
TW201820433A (zh) 2018-06-01
KR20180027356A (ko) 2018-03-14

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