KR102135073B1 - 에지 트리거 교정 - Google Patents

에지 트리거 교정 Download PDF

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Publication number
KR102135073B1
KR102135073B1 KR1020147028348A KR20147028348A KR102135073B1 KR 102135073 B1 KR102135073 B1 KR 102135073B1 KR 1020147028348 A KR1020147028348 A KR 1020147028348A KR 20147028348 A KR20147028348 A KR 20147028348A KR 102135073 B1 KR102135073 B1 KR 102135073B1
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South Korea
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edge
input
circuit
loop
output
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Korean (ko)
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KR20140136983A (ko
Inventor
데르 바그트 잔 파울 앤써니 반
로날드 에이. 사츠케프
그레고리 에이. 칸날
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테라다인 인코퍼레이티드
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27Structural arrangements therefor
    • H10P74/277Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31903Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191Calibration
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/319Tester hardware, i.e. output processing circuits
    • G01R31/31917Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922Timing generation or clock distribution

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Automation & Control Theory (AREA)
  • Manufacturing & Machinery (AREA)
KR1020147028348A 2012-03-28 2013-03-05 에지 트리거 교정 Active KR102135073B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201213433154A 2012-03-28 2012-03-28
US13/433,154 2012-03-28
US13/450,123 2012-04-18
US13/450,123 US9147620B2 (en) 2012-03-28 2012-04-18 Edge triggered calibration
PCT/US2013/029121 WO2013148085A1 (en) 2012-03-28 2013-03-05 Edge triggered calibration

Publications (2)

Publication Number Publication Date
KR20140136983A KR20140136983A (ko) 2014-12-01
KR102135073B1 true KR102135073B1 (ko) 2020-07-20

Family

ID=49235557

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147028348A Active KR102135073B1 (ko) 2012-03-28 2013-03-05 에지 트리거 교정

Country Status (5)

Country Link
US (1) US9147620B2 (https=)
JP (2) JP2015514211A (https=)
KR (1) KR102135073B1 (https=)
CN (1) CN104204822B (https=)
WO (1) WO2013148085A1 (https=)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140046475A1 (en) * 2012-08-09 2014-02-13 Applied Materials, Inc. Method and apparatus deposition process synchronization
US9244126B2 (en) * 2013-11-06 2016-01-26 Teradyne, Inc. Automated test system with event detection capability
KR20150117775A (ko) * 2014-04-10 2015-10-21 에스케이하이닉스 주식회사 테스트 장치 및 그의 동작 방법
US10996272B2 (en) * 2014-08-27 2021-05-04 Teradyne, Inc. One-shot circuit
US11131706B2 (en) * 2015-12-08 2021-09-28 International Business Machines Corporation Degradation monitoring of semiconductor chips
US12041713B2 (en) 2017-08-23 2024-07-16 Teradyne, Inc. Reducing timing skew in a circuit path
US10276229B2 (en) 2017-08-23 2019-04-30 Teradyne, Inc. Adjusting signal timing
CN109755147A (zh) * 2018-11-26 2019-05-14 北京铂阳顶荣光伏科技有限公司 薄膜光伏组件测试方法及薄膜光伏组件
US10942220B2 (en) 2019-04-25 2021-03-09 Teradyne, Inc. Voltage driver with supply current stabilization
US11119155B2 (en) 2019-04-25 2021-09-14 Teradyne, Inc. Voltage driver circuit
US10761130B1 (en) 2019-04-25 2020-09-01 Teradyne, Inc. Voltage driver circuit calibration
US11283436B2 (en) 2019-04-25 2022-03-22 Teradyne, Inc. Parallel path delay line
US11221365B2 (en) * 2020-03-11 2022-01-11 Teradyne, Inc. Calibrating an interface board
US11681324B2 (en) * 2021-10-01 2023-06-20 Achronix Semiconductor Corporation Synchronous reset deassertion circuit
US12278624B2 (en) * 2022-02-11 2025-04-15 Pratt & Whitney Canada Corp. Logic circuit for providing a signal value after a predetermined time period and method of using same
US11923853B2 (en) 2022-02-25 2024-03-05 Nvidia Corp. Circuit structures to measure flip-flop timing characteristics
CN118409627B (zh) * 2024-06-26 2024-09-27 悦芯科技股份有限公司 一种用于存储芯片ft测试机的校准板卡方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52144253A (en) * 1976-05-27 1977-12-01 Mitsubishi Electric Corp Flip-flop circuit
JPS62147371A (ja) * 1985-12-20 1987-07-01 Advantest Corp パルス幅測定器
IT1204621B (it) * 1987-05-15 1989-03-10 Montedison Spa Circuito flip-flop rs asincrono con scatto comandato dalle transizioni applicate agli ingressi
JPH01144719A (ja) * 1987-11-30 1989-06-07 Toshiba Corp リトリガブル・マルチバイブレータ
JP2813188B2 (ja) * 1989-01-27 1998-10-22 株式会社アドバンテスト Ic試験装置
JPH02214325A (ja) * 1989-02-15 1990-08-27 Nec Corp フリップフロップ回路
JPH0537306A (ja) * 1991-07-30 1993-02-12 Nec Corp フリツプフロツプ回路
JP3080701B2 (ja) * 1991-08-06 2000-08-28 日本電気アイシーマイコンシステム株式会社 セットリセット型フリップフロップ回路
JPH0548399A (ja) 1991-08-08 1993-02-26 Fujitsu Ltd 半導体装置
SE507139C2 (sv) * 1992-08-31 1998-04-06 Asea Brown Boveri Sätt och anordning för funktionskontroll av ljustända halvledarventilenheter i HVDC-ventilanläggningar
JP3688392B2 (ja) * 1996-05-31 2005-08-24 三菱電機株式会社 波形整形装置およびクロック供給装置
US6291981B1 (en) * 2000-07-26 2001-09-18 Teradyne, Inc. Automatic test equipment with narrow output pulses
US7187742B1 (en) * 2000-10-06 2007-03-06 Xilinx, Inc. Synchronized multi-output digital clock manager
JP2002260396A (ja) * 2001-03-02 2002-09-13 Kawasaki Microelectronics Kk 半導体記憶装置
US6380779B1 (en) 2001-07-12 2002-04-30 Hewlett-Packard Company Edge-triggered, self-resetting pulse generator
US7350132B2 (en) * 2003-09-10 2008-03-25 Hewlett-Packard Development Company, L.P. Nanoscale interconnection interface
US7873130B2 (en) * 2005-08-10 2011-01-18 Ludwig Lester F Frequency comparator utilizing enveloping-event detection via symbolic dynamics of fixed or modulated waveforms
US7737671B2 (en) * 2005-12-05 2010-06-15 Texas Instruments Incorporated System and method for implementing high-resolution delay
JP4295790B2 (ja) * 2006-02-02 2009-07-15 シャープ株式会社 パルス発生回路、半導体集積回路、及び、そのテスト方法
US20080232146A1 (en) 2007-03-23 2008-09-25 Texas Instruments Incorporated Efficient Power Supplies and Methods for Creating Such
US7653850B2 (en) 2007-06-05 2010-01-26 Intel Corporation Delay fault detection using latch with error sampling
US7795920B2 (en) 2008-03-31 2010-09-14 Kabushiki Kaisha Toshiba Semiconductor integrated circuit
JP5407551B2 (ja) * 2009-05-22 2014-02-05 富士通セミコンダクター株式会社 タイミング調整回路及びタイミング調整方法
US8228106B2 (en) * 2010-01-29 2012-07-24 Intel Mobile Communications GmbH On-chip self calibrating delay monitoring circuitry

Also Published As

Publication number Publication date
WO2013148085A1 (en) 2013-10-03
JP2015514211A (ja) 2015-05-18
US9147620B2 (en) 2015-09-29
KR20140136983A (ko) 2014-12-01
CN104204822B (zh) 2017-05-03
JP2018054628A (ja) 2018-04-05
US20130260485A1 (en) 2013-10-03
CN104204822A (zh) 2014-12-10

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