CN104204822B - 边缘触发的校准 - Google Patents

边缘触发的校准 Download PDF

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Publication number
CN104204822B
CN104204822B CN201380017389.4A CN201380017389A CN104204822B CN 104204822 B CN104204822 B CN 104204822B CN 201380017389 A CN201380017389 A CN 201380017389A CN 104204822 B CN104204822 B CN 104204822B
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CN
China
Prior art keywords
edge
input
loop
circuit
output
Prior art date
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Application number
CN201380017389.4A
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English (en)
Chinese (zh)
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CN104204822A (zh
Inventor
扬·保罗·安东尼·范德瓦特
罗纳德·A·萨特斯奇夫
格雷戈里·A·卡纳尔
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Teradyne Inc
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Teradyne Inc
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Publication date
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Publication of CN104204822A publication Critical patent/CN104204822A/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/27—Structural arrangements therefor
    • H10P74/277—Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31908—Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns
    • G01R31/3191—Calibration
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31917—Stimuli generation or application of test patterns to the device under test [DUT]
    • G01R31/31922—Timing generation or clock distribution

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Automation & Control Theory (AREA)
  • Manufacturing & Machinery (AREA)
CN201380017389.4A 2012-03-28 2013-03-05 边缘触发的校准 Active CN104204822B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201213433154A 2012-03-28 2012-03-28
US13/433,154 2012-03-28
US13/450,123 2012-04-18
US13/450,123 US9147620B2 (en) 2012-03-28 2012-04-18 Edge triggered calibration
PCT/US2013/029121 WO2013148085A1 (en) 2012-03-28 2013-03-05 Edge triggered calibration

Publications (2)

Publication Number Publication Date
CN104204822A CN104204822A (zh) 2014-12-10
CN104204822B true CN104204822B (zh) 2017-05-03

Family

ID=49235557

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380017389.4A Active CN104204822B (zh) 2012-03-28 2013-03-05 边缘触发的校准

Country Status (5)

Country Link
US (1) US9147620B2 (https=)
JP (2) JP2015514211A (https=)
KR (1) KR102135073B1 (https=)
CN (1) CN104204822B (https=)
WO (1) WO2013148085A1 (https=)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140046475A1 (en) * 2012-08-09 2014-02-13 Applied Materials, Inc. Method and apparatus deposition process synchronization
US9244126B2 (en) * 2013-11-06 2016-01-26 Teradyne, Inc. Automated test system with event detection capability
KR20150117775A (ko) * 2014-04-10 2015-10-21 에스케이하이닉스 주식회사 테스트 장치 및 그의 동작 방법
US10996272B2 (en) * 2014-08-27 2021-05-04 Teradyne, Inc. One-shot circuit
US11131706B2 (en) * 2015-12-08 2021-09-28 International Business Machines Corporation Degradation monitoring of semiconductor chips
US12041713B2 (en) 2017-08-23 2024-07-16 Teradyne, Inc. Reducing timing skew in a circuit path
US10276229B2 (en) 2017-08-23 2019-04-30 Teradyne, Inc. Adjusting signal timing
CN109755147A (zh) * 2018-11-26 2019-05-14 北京铂阳顶荣光伏科技有限公司 薄膜光伏组件测试方法及薄膜光伏组件
US10942220B2 (en) 2019-04-25 2021-03-09 Teradyne, Inc. Voltage driver with supply current stabilization
US11119155B2 (en) 2019-04-25 2021-09-14 Teradyne, Inc. Voltage driver circuit
US10761130B1 (en) 2019-04-25 2020-09-01 Teradyne, Inc. Voltage driver circuit calibration
US11283436B2 (en) 2019-04-25 2022-03-22 Teradyne, Inc. Parallel path delay line
US11221365B2 (en) * 2020-03-11 2022-01-11 Teradyne, Inc. Calibrating an interface board
US11681324B2 (en) * 2021-10-01 2023-06-20 Achronix Semiconductor Corporation Synchronous reset deassertion circuit
US12278624B2 (en) * 2022-02-11 2025-04-15 Pratt & Whitney Canada Corp. Logic circuit for providing a signal value after a predetermined time period and method of using same
US11923853B2 (en) 2022-02-25 2024-03-05 Nvidia Corp. Circuit structures to measure flip-flop timing characteristics
CN118409627B (zh) * 2024-06-26 2024-09-27 悦芯科技股份有限公司 一种用于存储芯片ft测试机的校准板卡方法

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JPS62147371A (ja) * 1985-12-20 1987-07-01 Advantest Corp パルス幅測定器
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JPH01144719A (ja) * 1987-11-30 1989-06-07 Toshiba Corp リトリガブル・マルチバイブレータ
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JP3688392B2 (ja) * 1996-05-31 2005-08-24 三菱電機株式会社 波形整形装置およびクロック供給装置
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US7187742B1 (en) * 2000-10-06 2007-03-06 Xilinx, Inc. Synchronized multi-output digital clock manager
JP2002260396A (ja) * 2001-03-02 2002-09-13 Kawasaki Microelectronics Kk 半導体記憶装置
US6380779B1 (en) 2001-07-12 2002-04-30 Hewlett-Packard Company Edge-triggered, self-resetting pulse generator
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US8228106B2 (en) * 2010-01-29 2012-07-24 Intel Mobile Communications GmbH On-chip self calibrating delay monitoring circuitry

Also Published As

Publication number Publication date
WO2013148085A1 (en) 2013-10-03
JP2015514211A (ja) 2015-05-18
US9147620B2 (en) 2015-09-29
KR20140136983A (ko) 2014-12-01
JP2018054628A (ja) 2018-04-05
US20130260485A1 (en) 2013-10-03
CN104204822A (zh) 2014-12-10
KR102135073B1 (ko) 2020-07-20

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