KR102095383B1 - 접합 웨이퍼의 제조방법 - Google Patents

접합 웨이퍼의 제조방법 Download PDF

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Publication number
KR102095383B1
KR102095383B1 KR1020157036519A KR20157036519A KR102095383B1 KR 102095383 B1 KR102095383 B1 KR 102095383B1 KR 1020157036519 A KR1020157036519 A KR 1020157036519A KR 20157036519 A KR20157036519 A KR 20157036519A KR 102095383 B1 KR102095383 B1 KR 102095383B1
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South Korea
Prior art keywords
wafer
bonded
bond
thickness
manufacturing
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Korean (ko)
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KR20160023712A (ko
Inventor
노리히로 코바야시
히로지 아가
Original Assignee
신에쯔 한도타이 가부시키가이샤
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Publication of KR20160023712A publication Critical patent/KR20160023712A/ko
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    • H01L21/76254—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H01L21/185—
    • H01L21/31155—
    • H01L21/324—
    • H01L22/12—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/12—Preparing bulk and homogeneous wafers
    • H10P90/16—Preparing bulk and homogeneous wafers by reclaiming or re-processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/11—Separation of active layers from substrates
    • H10P95/112—Separation of active layers from substrates leaving a reusable substrate, e.g. epitaxial lift off
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/90—Thermal treatments, e.g. annealing or sintering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
KR1020157036519A 2013-06-26 2014-05-19 접합 웨이퍼의 제조방법 Active KR102095383B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2013133868A JP5888286B2 (ja) 2013-06-26 2013-06-26 貼り合わせウェーハの製造方法
JPJP-P-2013-133868 2013-06-26
PCT/JP2014/002615 WO2014207988A1 (ja) 2013-06-26 2014-05-19 貼り合わせウェーハの製造方法

Publications (2)

Publication Number Publication Date
KR20160023712A KR20160023712A (ko) 2016-03-03
KR102095383B1 true KR102095383B1 (ko) 2020-03-31

Family

ID=52141364

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Application Number Title Priority Date Filing Date
KR1020157036519A Active KR102095383B1 (ko) 2013-06-26 2014-05-19 접합 웨이퍼의 제조방법

Country Status (8)

Country Link
US (1) US9859149B2 (https=)
EP (1) EP3016133B1 (https=)
JP (1) JP5888286B2 (https=)
KR (1) KR102095383B1 (https=)
CN (1) CN105283943B (https=)
SG (1) SG11201510639QA (https=)
TW (1) TWI567833B (https=)
WO (1) WO2014207988A1 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6136786B2 (ja) * 2013-09-05 2017-05-31 信越半導体株式会社 貼り合わせウェーハの製造方法
CN107112205B (zh) 2015-01-16 2020-12-22 住友电气工业株式会社 半导体衬底及其制造方法，组合半导体衬底及其制造方法
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
JP6686962B2 (ja) * 2017-04-25 2020-04-22 信越半導体株式会社 貼り合わせウェーハの製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963505A (en) 1987-10-27 1990-10-16 Nippondenso Co., Ltd. Semiconductor device and method of manufacturing same
US20060118935A1 (en) * 2003-04-02 2006-06-08 Eiji Kamiyama Laminated semiconductor substrate process for producing the same
WO2013057865A1 (ja) 2011-10-17 2013-04-25 信越半導体株式会社 剥離ウェーハの再生加工方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP3943782B2 (ja) 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
EP1807320B1 (en) 2004-10-11 2010-12-08 MeadWestvaco Corporation Slide card for child-resistant package
EP1667223B1 (en) 2004-11-09 2009-01-07 S.O.I. Tec Silicon on Insulator Technologies S.A. Method for manufacturing compound material wafers
JP4715470B2 (ja) 2005-11-28 2011-07-06 株式会社Sumco 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
JP5314838B2 (ja) * 2006-07-14 2013-10-16 信越半導体株式会社 剥離ウェーハを再利用する方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4963505A (en) 1987-10-27 1990-10-16 Nippondenso Co., Ltd. Semiconductor device and method of manufacturing same
US20060118935A1 (en) * 2003-04-02 2006-06-08 Eiji Kamiyama Laminated semiconductor substrate process for producing the same
WO2013057865A1 (ja) 2011-10-17 2013-04-25 信越半導体株式会社 剥離ウェーハの再生加工方法

Also Published As

Publication number Publication date
EP3016133A4 (en) 2017-03-01
TW201511141A (zh) 2015-03-16
CN105283943B (zh) 2018-05-08
CN105283943A (zh) 2016-01-27
US20160118294A1 (en) 2016-04-28
KR20160023712A (ko) 2016-03-03
US9859149B2 (en) 2018-01-02
TWI567833B (zh) 2017-01-21
JP2015012009A (ja) 2015-01-19
EP3016133A1 (en) 2016-05-04
SG11201510639QA (en) 2016-01-28
JP5888286B2 (ja) 2016-03-16
WO2014207988A1 (ja) 2014-12-31
EP3016133B1 (en) 2020-01-15

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