KR101937727B1 - 에칭 방법 - Google Patents

에칭 방법 Download PDF

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Publication number
KR101937727B1
KR101937727B1 KR1020160035300A KR20160035300A KR101937727B1 KR 101937727 B1 KR101937727 B1 KR 101937727B1 KR 1020160035300 A KR1020160035300 A KR 1020160035300A KR 20160035300 A KR20160035300 A KR 20160035300A KR 101937727 B1 KR101937727 B1 KR 101937727B1
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South Korea
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gas
region
plasma
process gas
generating
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KR1020160035300A
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Korean (ko)
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KR20160117220A (ko
Inventor
유스케 사이토
히로노부 이치카와
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도쿄엘렉트론가부시키가이샤
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    • H01L21/3065—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32—Gas-filled discharge tubes
    • H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082—Radio frequency generated discharge
    • H01J37/321—Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • H01L21/30621—
    • H01L21/31116—
    • H01L21/32136—
    • H01L21/32137—
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/246—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/405—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their composition, e.g. multilayer masks

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Plasma & Fusion (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
KR1020160035300A 2015-03-31 2016-03-24 에칭 방법 Active KR101937727B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015071502A JP6339961B2 (ja) 2015-03-31 2015-03-31 エッチング方法
JPJP-P-2015-071502 2015-03-31

Publications (2)

Publication Number Publication Date
KR20160117220A KR20160117220A (ko) 2016-10-10
KR101937727B1 true KR101937727B1 (ko) 2019-01-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020160035300A Active KR101937727B1 (ko) 2015-03-31 2016-03-24 에칭 방법

Country Status (3)

Country Link
US (1) US9793134B2 (enExample)
JP (1) JP6339961B2 (enExample)
KR (1) KR101937727B1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9997374B2 (en) * 2015-12-18 2018-06-12 Tokyo Electron Limited Etching method
JP6878174B2 (ja) * 2017-06-29 2021-05-26 東京エレクトロン株式会社 プラズマエッチング方法及びプラズマエッチング装置
JP6948181B2 (ja) * 2017-08-01 2021-10-13 東京エレクトロン株式会社 多層膜をエッチングする方法
US10727045B2 (en) 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
JP7022651B2 (ja) * 2018-05-28 2022-02-18 東京エレクトロン株式会社 膜をエッチングする方法及びプラズマ処理装置
JP7277225B2 (ja) 2019-04-08 2023-05-18 東京エレクトロン株式会社 エッチング方法、及び、プラズマ処理装置
WO2021171458A1 (ja) * 2020-02-27 2021-09-02 株式会社日立ハイテク プラズマ処理方法
CN111533461B (zh) * 2020-05-25 2022-12-13 福建和达玻璃技术有限公司 用于玻璃机壳金属质感表面处理的高精度控温装置及方法
CN112592069A (zh) * 2020-12-18 2021-04-02 安徽普恒光学材料有限公司 一种防眩光玻璃蚀刻工艺生产线
JP7653327B2 (ja) * 2021-03-31 2025-03-28 東京エレクトロン株式会社 エッチング方法及びエッチング処理装置
KR20240006574A (ko) * 2021-05-07 2024-01-15 도쿄엘렉트론가부시키가이샤 에칭 방법
US12048154B2 (en) * 2021-06-10 2024-07-23 Macronix International Co., Ltd. Memory device and manufacturing method thereof
US20230094212A1 (en) * 2021-09-30 2023-03-30 Tokyo Electron Limited Plasma etch process for fabricating high aspect ratio (har) features

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130043455A1 (en) 2011-08-15 2013-02-21 Unity Semiconductor Corporation Vertical Cross Point Arrays For Ultra High Density Memory Applications
US20130059450A1 (en) * 2011-09-06 2013-03-07 Lam Research Corporation Etch process for 3d flash structures
US20130256777A1 (en) 2012-03-30 2013-10-03 Seagate Technology Llc Three dimensional floating gate nand memory

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07263415A (ja) * 1994-03-18 1995-10-13 Fujitsu Ltd 半導体装置の製造方法
JP5038567B2 (ja) * 2001-09-26 2012-10-03 東京エレクトロン株式会社 エッチング方法
JP5640361B2 (ja) * 2009-12-03 2014-12-17 富士通セミコンダクター株式会社 半導体装置の製造方法
JP2012028431A (ja) * 2010-07-21 2012-02-09 Toshiba Corp 半導体装置の製造方法
JP2012151187A (ja) * 2011-01-17 2012-08-09 Toshiba Corp 半導体記憶装置の製造方法
KR102034556B1 (ko) * 2012-02-09 2019-10-21 도쿄엘렉트론가부시키가이샤 플라즈마 처리 방법
JP5968130B2 (ja) * 2012-07-10 2016-08-10 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
JP6154820B2 (ja) * 2012-11-01 2017-06-28 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
JP6211947B2 (ja) * 2013-07-31 2017-10-11 東京エレクトロン株式会社 半導体装置の製造方法
JP6140575B2 (ja) * 2013-08-26 2017-05-31 東京エレクトロン株式会社 半導体装置の製造方法
JP2015046425A (ja) * 2013-08-27 2015-03-12 株式会社東芝 パターン形成方法、および、それを用いた不揮発性記憶装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130043455A1 (en) 2011-08-15 2013-02-21 Unity Semiconductor Corporation Vertical Cross Point Arrays For Ultra High Density Memory Applications
US20130059450A1 (en) * 2011-09-06 2013-03-07 Lam Research Corporation Etch process for 3d flash structures
US20130256777A1 (en) 2012-03-30 2013-10-03 Seagate Technology Llc Three dimensional floating gate nand memory

Also Published As

Publication number Publication date
KR20160117220A (ko) 2016-10-10
US20160293439A1 (en) 2016-10-06
JP6339961B2 (ja) 2018-06-06
US9793134B2 (en) 2017-10-17
JP2016192483A (ja) 2016-11-10

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