KR101936980B1 - 확장가능 드라이버를 포함하는 장치 및 방법 - Google Patents

확장가능 드라이버를 포함하는 장치 및 방법 Download PDF

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KR101936980B1
KR101936980B1 KR1020147028604A KR20147028604A KR101936980B1 KR 101936980 B1 KR101936980 B1 KR 101936980B1 KR 1020147028604 A KR1020147028604 A KR 1020147028604A KR 20147028604 A KR20147028604 A KR 20147028604A KR 101936980 B1 KR101936980 B1 KR 101936980B1
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drivers
die
dies
delete delete
driver
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KR20140140076A (ko
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펭 린
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마이크론 테크놀로지, 인크.
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
KR1020147028604A 2012-03-27 2013-03-13 확장가능 드라이버를 포함하는 장치 및 방법 Active KR101936980B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/431,674 2012-03-27
US13/431,674 US8587340B2 (en) 2012-03-27 2012-03-27 Apparatuses including scalable drivers and methods
PCT/US2013/030900 WO2013148199A1 (en) 2012-03-27 2013-03-13 Apparatuses including scalable drivers and methods

Publications (2)

Publication Number Publication Date
KR20140140076A KR20140140076A (ko) 2014-12-08
KR101936980B1 true KR101936980B1 (ko) 2019-01-09

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KR1020147028604A Active KR101936980B1 (ko) 2012-03-27 2013-03-13 확장가능 드라이버를 포함하는 장치 및 방법

Country Status (7)

Country Link
US (3) US8587340B2 (https=)
EP (1) EP2831876B1 (https=)
JP (1) JP6082803B2 (https=)
KR (1) KR101936980B1 (https=)
CN (1) CN104285254B (https=)
TW (1) TWI570739B (https=)
WO (1) WO2013148199A1 (https=)

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US9397566B2 (en) * 2014-03-20 2016-07-19 Intel Corporation Master-slave digital voltage regulators
US9042160B1 (en) * 2014-07-03 2015-05-26 Sandisk Technologies Inc. Memory device with resistive random access memory (ReRAM)
KR20160043714A (ko) * 2014-10-14 2016-04-22 에스케이하이닉스 주식회사 관통 비아를 갖는 반도체 메모리 장치
US9455189B1 (en) 2015-06-14 2016-09-27 Darryl G. Walker Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture
US20210125040A1 (en) * 2019-10-24 2021-04-29 International Business Machines Corporation 3d neural inference processing unit architectures

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Also Published As

Publication number Publication date
US9564878B2 (en) 2017-02-07
US20140070860A1 (en) 2014-03-13
JP6082803B2 (ja) 2017-02-15
TW201403616A (zh) 2014-01-16
CN104285254B (zh) 2016-07-20
US8587340B2 (en) 2013-11-19
KR20140140076A (ko) 2014-12-08
TWI570739B (zh) 2017-02-11
EP2831876A1 (en) 2015-02-04
JP2015520432A (ja) 2015-07-16
EP2831876A4 (en) 2015-11-11
EP2831876B1 (en) 2019-08-28
US8836395B2 (en) 2014-09-16
US20150137866A1 (en) 2015-05-21
US20130257489A1 (en) 2013-10-03
CN104285254A (zh) 2015-01-14
WO2013148199A1 (en) 2013-10-03

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