CN105431939A - 堆栈存储器 - Google Patents

堆栈存储器 Download PDF

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CN105431939A
CN105431939A CN201480028461.8A CN201480028461A CN105431939A CN 105431939 A CN105431939 A CN 105431939A CN 201480028461 A CN201480028461 A CN 201480028461A CN 105431939 A CN105431939 A CN 105431939A
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memory cell
substrate
data dump
dump line
data
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安相旭
郑喜灿
李龙云
李道永
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SK Hynix System IC Inc
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Siliconfile Technologies Inc
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Abstract

本发明涉及一种堆栈存储器，其将多个基板叠层而形成半导体存储器，各基板的存储器单元通过数据转储线连接。在存储器单元和数据转储线之间可增加开关。在通过数据转储线转储各基板的数据时，使由寄生组件导致的速度下降和功耗增加的问题最小化。并且，包括存储器单元的核心电路可以设置在一个基板上，外围电路部可以设置在另一个基板上。

Description

堆栈存储器
技术领域
本发明涉及一种不同基板的存储器装置相互堆积(stack)而电连接的技术。尤其，涉及各基板的存储器单元共有数据转储线，且各数据转储线相互电连接的结构。
背景技术
过去数十年，随着半导体技术的快速发展，半导体存储器单元的集成度大幅提高。对于DRAM(DynamicRandomAccessMemory)而言，在一个硅基板上集成的元件数量达到了数十个亿。增加的元件数量必然会导致功耗的增加，同时还会因寄生效应而导致操作速度下降。然而，半导体基板材料或者半导体封装材料的特性根本无法满足这样的功率增加趋势，因此电路设计人员通过降低从外部向集成电路供给的电源电压或者在集成电路内部设置低于外部电源电压的内部电源电压来进行应对。低的内部电源电压使电路的电压摆幅低，从而能够大幅降低动态电流消耗(dynamiccurrentconsumption)，这对于驱动长数据线的电路来说是特别有效。如数学式1所示，导线的动态电流消耗IL与施加于导线的电压变化率dV/dt和导线电容性负载CL的乘积成正比。
数学式1
I L = C L d V d t
即使半导体存储装置的集成度提高，也无法减少因由金属或者多晶硅制成的导线长度增加而伴随的寄生组件，例如，寄生电阻或者寄生电容性负载(capacitiveload)。例如，集成度从1GbDRAM提高到4GbDRAM时，导线长度也随之增加4倍，从理论上讲寄生组件也随之增加4倍。当然，由于半导体制造技术越来越精细化，寄生组件实际上不会增加到理论上的倍数。即便这样，当线宽变细时每个单位长度的寄生电容将减少，但是每个单位长度的寄生电阻反而会增加，因此，依赖于R和C的乘积的时间常数的信号的总响应时间会随着集成度的增加而增加。
由此，操作速度的下降和功耗的增加现象在半导体存储装置上表现得尤其严重，这在最近出现的将多个基板堆积成三维的技术中也表现得比较明显。下面，对于这方面的问题进行更为具体的说明。
半导体存储装置中存储二进制信息的存储器单元向行(row)和列(column)方向阵列(array)，每当集成度增加时二进制信息进出存储器单元的路径的寄生电阻和寄生电容会快速增加。
图1a示出现有技术中的多种基板通过键合引线的键合来相互连接并封装的堆积结构。通过举这个例子说明存在的问题。图1a示出在由多个半导体基板形成的层的多层封装100中各半导体基板101、103、105通过键合引线的键合来相互连接的剖视图。如果各个半导体基板为半导体存储装置的情况下，具有如图2所示的形状的模块。
图2是假设存储二进制信息的存储器单元向行和列方向阵列而形成一个矩阵MAT_0～MAT_31，且32个矩阵又形成一个大的组111～114的图。当然，图2只不过是在半导体存储装置内部各个矩阵排列的一个例子。如果更详细地示出一个矩阵，则会是图3所示的结构。
各存储器单元(MC)向行和列方向阵列而形成矩阵，在列方向上位线共同地连接于存储器单元，并读写二进制信息。向存储器单元写入二进制信息的路径大致为：通过连接在半导体基板外部的针(pin)或者封装(package)，按照输入输出电路(IO电路)-全局数据线-本地数据线-位线-存储器单元的顺序进行。读取路径与写入路径的顺序相反。
如果将沿着读取和写入路径存在的寄生组件等效地简略表示，则如图4所示一样。
当图3为第一基板的半导体存储装置101，位线长度为400μm(微米)时，假设每个单位μm的电容为1nF(纳法)，则位线的总电容CBIT为0.4pF(皮法)。本地数据线的长度约为位线长度的十倍左右，因此本地数据线的总电容CLOC为4pF，当全局数据线长度为数据线长度的五倍时，全局数据线的总电容CGLO为20pF的较大的值。二进制信息经过位线-本地数据线-全局数据线路径时，应分别以0.4pF、4pF及20pF的顺序进行充电或者放电，这意味着数据传播延迟时间将增加。传播延迟时间与路径的时间常数成正比。为了便于计算，假设路径的总的寄生电阻为10Ω时，路径的时间常数为244ps(皮秒)的较大的值。
另外，从功耗的角度考虑，当一个周期为4ns(纳秒)时，如果数据线的电压变化达到1.2V，则根据数学式1的动态电流消耗为1.2mA(毫安)。此时，如果数据由32位组成，则成对(pair)组成的数据线的总数量为64个，结果在一个周期内32位数据线所消耗的总的动态电流就能达到1.2mA的64倍即76.8mA。并且，经过输入输出电路(IO电路)之后，基于引线键合(wirebonding)或者封装的引线框架的寄生组件CPKG达到几pF至几十pF，会导致上述的两种问题更加恶化。
如图1b所示，即使用穿透硅通孔(ThroughSiliconVia，TSV)技术将半导体存储装置的各基板连接，上述问题也不会消失。只是减少相当于基于引线键合或者封装的引线框架的寄生组件CPKG导致的传播延迟时间的增加量或者功耗的增加量的量。
因此，以三维堆积而提供的半导体装置或者半导体存储装置，需要通过传播延迟时间的降低来提高操作速度，并降低功耗。
发明内容
(一)要解决的技术问题
本发明所要解决的技术问题是提供一种堆栈存储器，所述堆栈存储器的结构为：在由包括至少一个以上的半导体存储装置的多个半导体基板堆积的情况下，在一个基板上形成的数据转储线与在另一个基板上形成的数据转储线电连接。
(二)技术方案
根据本发明的一个方面的堆栈存储器，在第一基板上包括第一类型存储器单元，在第二基板上包括第二类型存储器单元，并且这些存储器单元通过数据转储线相互电连接。
根据本发明的实施例，在第一类型存储器单元或者第二类型存储器单元与数据转储线之间可增加开关。各数据转储线电连接，所述电连接可以是如金属等导电性物质直接接触来实现，或者是利用众所周知的DBI等技术，或者是电连接部位通过垫板区域来实现。垫板区域的导电性物质的宽度可大于形成数据转储线的导电性物质的线的宽度。
根据本发明的实施例，第一类型存储器单元或者第二类型存储器单元可以是易失性存储器单元或者非易失性存储器单元。
根据本发明的实施例，在数据转储线和垫板之间可增加用于选择性地连接的转储开关。
根据本发明的另一个方面的堆栈存储器，在一个基板上设置有包括存储器单元、读出放大器列选择电路等的核心电路，在另一个基板上设置有负责输入和输出的输入输出电路，并且在各个基板之间可包括连接所述各基板的数据转储线。
根据本发明的实施例，第一类型存储器单元或者第二类型存储器单元与数据转储线之间可增加开关。
根据本发明的又一方面的堆栈存储器，在分别属于第一基板和第二基板的存储器单元通过数据转储线相互收发数据时，这些数据转储线与基板的外部收发数据时所需的线的位线或者字线无关，可以单独存在。
(三)有益效果
根据本发明，当多个半导体基板叠层时，各个基板之间的数据传输速度加快，且功耗下降。即使各个基板之间数据转储线一对一对应或者多个相对应时，通过能够选择数据转储线的开关，能够有效地实现数据转储，因此适合用作缓冲存储器。
附图说明
图1a是示出通过键合引线来连接各个基板的现有的结构的图。
图1b是示出通过穿透硅通孔(TSV)来连接各个基板的现有的结构的图。
图2是示出半导体存储器的设置形状的图。
图3是简略地示出存储器单元和数据路径的图。
图4是简略地示出沿着数据路径存在的寄生组件的图。
图5a是示出本发明的实施例的图。
图5b是示出本发明的另一实施例的图。
图5c是示出本发明的又一实施例的图。
图6是本发明的实施例中的一个实施例的剖视图。
图7a是本发明的另一实施例。
图7b是由图7a派生的本发明的另一实施例。
图7c是由图7a派生的本发明的又一实施例。
图8是俯视本发明的实施例的图。
图9是另外单独设置位线和数据转储线的本发明的另一实施例。
图10是在各个基板上设置存储器单元部分和外围电路部的本发明的另一实施例。
图11是表示能够堆积三个以上的基板的本发明的又一实施例。
具体实施方式
在说明书中对本发明的内容进行说明，其中，各个组成构件之间“电连接”、“连接”、“接合”等术语的意思不仅包括直接连接的意思，而且还包括在保持一定属性的情况下通过中间介质来实现连接的所有意思。各个信号“传输”、“得出”等术语也一样，不仅包括直接传输的意思，而且还包括在保持一定的信号属性的情况下通过中间介质间接地传输的所有意思。其他的比如电压或者信号“施加”、“输入”等术语的意思也应当如此地理解和使用。
并且，还可省略各组成构件的复数的表示。例如，可将由多个开关或者多个信号线组成的结构表示为“各开关”、“各信号线”，而且还可表示为单数形式的“开关”、“信号线”。这是因为开关有时互补地操作，有时单独操作，而且，信号线也由具有相同属性的信号线例如地址信号或者数据信号等信号线形成束，因此没必要一定区分为单数和复数。基于这点，上述记载是合适的。因此，在说明书中与上述情况类似的表述也应当以相同的含义来解释。
图5a是示出本发明的各种实施例中的一个实施例的图。
参照图5a，示出形成在半导体第一基板的存储器单元(MC)上写入或者读取二进制信息的第一数据转储线。为了便于说明，没有示出与存储器单元阵列连接的字线。存储器单元可以是如SRAM或者DRAM等易失性存储器单元或者如闪存等非易失性存储器单元。
第一基板的存储器单元以单元(cell)为单位与第二基板的存储器单元相对应且电连接。这样的电连接可以是公知的DBI(DirectBondInterconnect)技术，也可以是利用其它技术。在该实施例中，虽然只是将存储器单元用简单的模块来表示，但是所述存储器单元可以是如SRA等由多个晶体管组成的方式，或者采用如NAND闪存等由多个晶体管串联的方式。即便这样，通过数据转储线的连接结构也不会有变化，以下，本发明的所有实施例也同样如此。
构成第一基板的数据转储线和第二基板的数据转储线的导电性物质的线，其宽度可以非常非常窄，因此，为了顺利连接第一基板的数据转储线和第二基板的数据转储线，可分别形成宽的垫板区域来进行接合，所述垫板区域的连接部位的导电性物质比存储器单元阵列内部的数据转储线的导电性物质的线更宽。
与第一基板的存储器单元和第二基板的存储器单元一样，第一基板的数据转储线和第二基板的数据转储线也具有相同的间距(pitch)。
在从第一基板的存储器单元向第二基板的存储器单元转储数据时需要克服的寄生组件只有两个数据转储线所具有的寄生电阻和寄生电容。由于数据通过数据转储线被传输到其他基板的存储器单元，因此，以这种结构形成多层(multi-layer)基板并被堆积的半导体存储器适于应用在数据传输路径的寄生组件最小化而需响应中央处理器(CPU)的指令而快速操作的缓存(cache)系统。
上述实施例可扩展为如图5b所示。与图5a中以存储器单元为单位相互连接相比，图5b中以列(column)为单位连接。对此不做详细说明，不过在此情况下，将相互连接数据转储线的垫板无需设置在存储器单元阵列的中央，而可以设置在读出放大器或者用于选择列的电路附近。对此在后面进行说明，优选地，将数据转储线相互接合的区域设置在所谓的核心(core)电路部分，以避开存储器单元阵列。
图5a和图5b的实施例与图5c一样可以在垫板和数据转储线之间增加开关并实施。各基板的柱开关SW11-SW13、SW21-SW23，在第一基板和第二基板之间实现数据传输时，可根据地址信号或者其他选择信号适当地选择，而且只在某一个基板上也可以。会增加通过柱开关来可以单独选择各基板的数据转储线的功能。
虽然在图5a至图5c中未示出，但是根据情况，在各数据转储线和垫板之间可以增加开关。
下面，为了便于说明，分别将如图5a所示的以存储器单元为单位连接的结构称为“A类型”，将如图5b所示的以列为单位连接的结构称为“B类型”，将如图5c所示的增加柱开关的结构称为“C类型”。
图6是示出图5a的实施例的剖视图。在第一基板210和第二基板220上图示着形成半导体有源元件的栅极区域211、221和杂质扩散区域212、222，而且还画有用于电连接各半导体元件的第一金属层213、223和第二金属层214、224。杂质区域212、222、第一金属层213、223及第二金属层214、224可通过众所周知的TSV方式连接。当半导体有源元件为易失性存储装置或者非易失性存储装置时，可以是表示存储器单元的晶体管中的至少一部分晶体管。将第一基板和第二基板分别制作后相互接合。在图6中，通过第一基板的垫板215和第二基板的垫板225，两个基板的存储器单元相互连接。在垫板连接中使用的技术可以是DBI技术，在连接时使用的导电性物质优选为钨(W)、铝(Al)、铜(Cu)、钛(Ti)、钼(Mo)等在制造半导体时使用的金属物质，但并不限定于此。例如，也可以使用已充分地确保具有导电性的如多晶硅等具有适当的导电性的物质。在DBI连接的情况下，可以在常温或者高于常温的温度下进行，即使不是DBI连接的情况下，只要是在半导体制造工艺中使用的导电性物质的连接技术就都可以使用。为了容易连接垫板，优选为比由各数据转储线的导电性物质形成的线的宽度宽。
图7a示出本发明的另一实施例。图7a对应于如上所述的“A类型”。如图7a所示的实施例，根据存储器单元的大小或存储器单元的种类，在一个第一基板的数据转储线上可以连接多个第二基板的数据转储线。如果在一个第一基板的数据转储线上连接四个第二基板的数据转储线，则第一基板的数据转储线的间距和第二基板的数据转储线的间距可以不同。在重复的存储器单元阵列中，如果想要顺利地连接具有不同间距的存储器单元，优选地，一个基板的存储器单元间距为另一基板的存储器单元间距的整数倍。关于这方面，在图8中能够更加详细地理解。
与图7b一样，图7a也可以以列为单位扩展而实施为“B类型”，可以在第一基板或者第二基板上增加开关SW31、SW2、SW41-SW44、SW51-SW54来实施为“C类型”。各个开关根据用途可以在不同的时间运行，或者在相同的时间运行。
图8是俯视如图7a所示属于第一基板的一个存储器单元与属于第二基板的四个存储器单元相对应，在第二基板的各个存储器单元上增加开关的概念图。如上所述，在存储器单元和数据转储线之间增加开关时，在第一基板和第二基板上都可以增加开关，但是如图8所示，也可以只在一个基板上增加开关。由此，当第一基板的存储器单元的面积为第二基板的存储器单元的面积的四倍时，列方向的间距优选为二倍。
参照图9对本发明的另一实施例进行说明。该实施例是在上面说明的另一实施例的基础上发展的实施例。需要注意的是，各存储器单元分别包括位线(BL)和数据转储线。虽然没有另外进行说明，但是在上面说明的所有实施例中也应当可以分别包括位线和数据转储线。位线和字线并不是用于第一基板和第二基板之间的数据转储，而是主要用于从第一基板的外部或者第二基板的外部接收数据或者向第一基板的外部或者第二基板的外部传输数据。根据情况，可以只在第一基板或者第二基板的其中一个基板上具有位线和字线。
从第一基板的存储器单元向第二基板的存储器单元转储数据，或者与此相反地转储数据时，优选地，如图9所示包括用于转储的开关。为了转储数据，更优选地，第一基板的存储器单元或者第二基板的存储器单元采用锁存(latch)形式的电路。第二基板的各个存储器单元包括与位线连接的开关，这些开关通过字线信号来驱动。转储数据可以从第一基板向第二基板转储，也可以是与此相反地转储。
在第二基板的存储器单元和位线之间可包括开关。当单独包括用于转储数据的转储开关dump1～dump4和位线开关时，通过位线开关进行从第二基板的外部写入或者向外部读取的操作。由于数据转储线和位线互相区分开，因此与外部的读取和写入的操作与数据转储线不相关。
图10是本发明的又一实施例。在第一基板上形成有存储器单元阵列和读出放大器(SenseAmp)和写入电路(WriteDriver)，在第二基板上形成有用于数据的输入和输出的电路(IO电路)。与上面说明的本发明的实施例不同，可在一个基板上设置如存储器单元、读出放大器及写入电路等被称为核心电路(corecircuit)的电路，而在另一个基板上设置被称为外围电路(peripheralcircuiti)的输入输出电路等。
在本发明的所有实施例中，如图11所示，可以堆积三个以上的基板。在第一基板210上叠层第三基板230，并通过第三基板的垫板235与第一基板210的垫板217相互电连接。在第三基板上另外显示有晶体管等有源元件的栅极231和扩散区域232。如此，理论上并不限制半导体基板的堆积数量，越是叠层多个基板，可集成在狭窄的空间的半导体元件的数量就越增加。
在上述的本发明的所有实施例中，为了便于说明，适当地省略了对于与存储器单元临近设置的读出放大器、与列选择相关的电路及与行选择相关的电路的说明。
无论在上述的本发明的哪个实施例中，从第一基板的存储器单元向第二基板的存储器单元转储数据或者与此相反地转储数据时，由于不存在沿存储器单元阵列的字线方向延伸的本地数据线的寄生电容和连接各阵列矩阵的所谓全局数据线的寄生电容，因此无需克服这些。因此，如上所述的现有的例子，假设一个数据转储线的总电容为0.4pF、等效的寄生容量为10Ω时，即使第一基板的数据转储线和第二基板的数据转储线电连接，时间常数也不过是8ps。因此，在功耗更少的情况下也能够将数据传输速度提高至数十倍。
以上参照附图中示出的实施例对本发明进行了说明，但所述实施例仅仅是例示而已，在此基础上本发明所属领域的普通技术人员可以进行各种变形和可以实施等同的其他实施例。因此，本发明的实际保护范围应根据权利要求书记载的技术思想来决定。

Claims (14)

1.一种堆栈存储器，其特征在于，包括：
第一类型存储器单元，在第一基板上沿行方向和列方向以矩阵形式阵列；
第一数据转储线，传输向所述第一类型存储器单元输入和输出的数据，并共同地连接在所述第一类型存储器单元中的至少一个存储器单元上；
第二类型存储器单元，在第二基板上沿行方向和列方向以矩阵形式阵列；以及
第二数据转储线，传输向所述第二类型存储器单元输入和输出的数据，并共同地连接在所述第二类型存储器单元中的至少一个存储器单元上，
所述第一数据转储线与所述第二数据转储线电连接。
2.根据权利要求1所述的堆栈存储器，其特征在于，所述堆栈存储器还包括在所述第一基板和所述第一类型存储器单元之间或者所述第二基板和所述第二类型存储器单元之间形成的开关。
3.根据权利要求1或2所述的堆栈存储器，其特征在于，所述电连接是通过所述第一数据转储线的导电性物质和所述第二数据转储线的导电性物质的直接接触来实现。
4.根据权利要求1或2所述的堆栈存储器，其特征在于，所述电连接是通过面积大于形成所述第一数据转储线或者所述第二数据转储线的所述导电性物质的面积的导电性垫板来实现。
5.根据权利要求1或2所述的堆栈存储器，其特征在于，所述第一基板和所述第二基板以多层结构叠层。
6.根据权利要求1或2所述的堆栈存储器，其特征在于，所述第一类型存储器单元或者所述第二类型存储器单元中的至少一个以上的存储器单元与所述第一数据转储线或者所述第二数据转储线之间增加开关元件。
7.根据权利要求1或2所述的堆栈存储器，其特征在于，所述第一类型存储器单元和所述第二类型存储器单元的大小不同。
8.根据权利要求1或2所述的堆栈存储器，其特征在于，所述第一类型存储器单元或者所述第二类型存储器单元中的其中一个存储器单元为非易失性或者易失性存储器单元。
9.根据权利要求1或2所述的堆栈存储器，其特征在于，包括：
第一位线，其位于所述第一基板上，与所述第一数据转储线无关地，单独将所述第一类型存储器单元向列方向连接；
第一字线，其位于所述第一基板上，与所述第一数据转储线无关地，单独将所述第一类型存储器单元向行方向连接；
第二位线，其属于所述第二基板，与所述第二数据转储线无关地，单独将所述第二类型存储器单元向列方向连接；以及
第二字线，其属于所述第二基板，与所述第二数据转储线无关地，单独将所述第二类型存储器单元向行方向连接。
10.一种堆栈存储器，其特征在于，包括：
第一基板，设置有沿行方向和列方向阵列的存储器单元、用于感应从所述存储器单元输出的数据的读出放大器以及用于驱动输入于所述存储器单元的数据的写入驱动器；
第二基板，设置有用于传输向所述存储器单元输入和输出的数据的输入输出电路，
所述第一基板和所述第二基板通过在所述第一基板上形成的第一数据转储线和在所述第二基板上形成的第二数据转储线来电连接。
11.根据权利要求10所述的堆栈存储器，其特征在于，所述电连接是通过所述第一数据转储线的导电性物质和所述第二数据转储线的导电性物质的直接接触来实现。
12.根据权利要求10所述的堆栈存储器，其特征在于，所述电连接是通过面积大于形成所述第一数据转储线或者所述第二数据转储线的所述导电性物质的面积的导电性垫板来实现。
13.根据权利要求10所述的堆栈存储器，其特征在于，所述第一基板和所述第二基板以多层结构叠层。
14.根据权利要求10所述的堆栈存储器，其特征在于，所述存储器单元中的至少一个以上的存储器单元与所述第一数据转储线之间增加开关元件。
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