CN104285254B - 包含可缩放驱动器的设备及方法 - Google Patents

包含可缩放驱动器的设备及方法 Download PDF

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Publication number
CN104285254B
CN104285254B CN201380018180.XA CN201380018180A CN104285254B CN 104285254 B CN104285254 B CN 104285254B CN 201380018180 A CN201380018180 A CN 201380018180A CN 104285254 B CN104285254 B CN 104285254B
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Prior art keywords
drivers
die
driver
additional
semiconductor die
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Chinese (zh)
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CN104285254A (zh
Inventor
林峰
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Micron Technology Inc
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Micron Technology Inc
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
CN201380018180.XA 2012-03-27 2013-03-13 包含可缩放驱动器的设备及方法 Active CN104285254B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/431,674 2012-03-27
US13/431,674 US8587340B2 (en) 2012-03-27 2012-03-27 Apparatuses including scalable drivers and methods
PCT/US2013/030900 WO2013148199A1 (en) 2012-03-27 2013-03-13 Apparatuses including scalable drivers and methods

Publications (2)

Publication Number Publication Date
CN104285254A CN104285254A (zh) 2015-01-14
CN104285254B true CN104285254B (zh) 2016-07-20

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN201380018180.XA Active CN104285254B (zh) 2012-03-27 2013-03-13 包含可缩放驱动器的设备及方法

Country Status (7)

Country Link
US (3) US8587340B2 (https=)
EP (1) EP2831876B1 (https=)
JP (1) JP6082803B2 (https=)
KR (1) KR101936980B1 (https=)
CN (1) CN104285254B (https=)
TW (1) TWI570739B (https=)
WO (1) WO2013148199A1 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8587340B2 (en) 2012-03-27 2013-11-19 Micron Technology, Inc. Apparatuses including scalable drivers and methods
US9153312B2 (en) 2013-08-23 2015-10-06 Micron Technology, Inc. Methods and apparatuses including transmitter circuits
US9397566B2 (en) * 2014-03-20 2016-07-19 Intel Corporation Master-slave digital voltage regulators
US9042160B1 (en) * 2014-07-03 2015-05-26 Sandisk Technologies Inc. Memory device with resistive random access memory (ReRAM)
KR20160043714A (ko) * 2014-10-14 2016-04-22 에스케이하이닉스 주식회사 관통 비아를 갖는 반도체 메모리 장치
US9455189B1 (en) 2015-06-14 2016-09-27 Darryl G. Walker Package including a plurality of stacked semiconductor devices including a capacitance enhanced through via and method of manufacture
US20210125040A1 (en) * 2019-10-24 2021-04-29 International Business Machines Corporation 3d neural inference processing unit architectures

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1574356A (zh) * 2003-06-03 2005-02-02 日立环球储存科技荷兰有限公司 超低成本固态存储器
CN1734669A (zh) * 2004-06-22 2006-02-15 三星电子株式会社 半导体存储器件及其阵列内部电源电压产生方法
CN101060010A (zh) * 2006-04-21 2007-10-24 松下电器产业株式会社 半导体存储装置
US20110161748A1 (en) * 2009-12-31 2011-06-30 Bryan Casper Systems, methods, and apparatuses for hybrid memory
CN102376356A (zh) * 2010-08-12 2012-03-14 台湾积体电路制造股份有限公司 带有减小的栅极电阻的字线驱动器器件及其制造方法
CN102386172A (zh) * 2010-08-27 2012-03-21 海力士半导体有限公司 半导体集成电路

Family Cites Families (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0679330B2 (ja) 1987-11-11 1994-10-05 富士通株式会社 イメージセンサの画素分解能検査方法
JPH07170171A (ja) * 1993-12-14 1995-07-04 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JPH10312230A (ja) * 1997-05-14 1998-11-24 Oki Data:Kk 駆動能力切換機能付出力バッファ装置
JPH1125678A (ja) * 1997-06-27 1999-01-29 Samsung Electron Co Ltd 出力ドライバ及び半導体メモリ装置
US6051995A (en) 1998-09-11 2000-04-18 Sharp Electronics Corporation Constant impedance, low noise CMOS buffer
US6255899B1 (en) * 1999-09-01 2001-07-03 International Business Machines Corporation Method and apparatus for increasing interchip communications rates
US6704818B1 (en) * 2000-12-29 2004-03-09 Intel Corporation Voltage-mode driver with pre-emphasis, slew-rate control and source termination
US7277382B1 (en) * 2001-01-09 2007-10-02 Urbain A. von der Embse Hybrid walsh encoder and decoder for CDMA
US6908784B1 (en) * 2002-03-06 2005-06-21 Micron Technology, Inc. Method for fabricating encapsulated semiconductor components
US20040263203A1 (en) * 2003-06-27 2004-12-30 Intel Corporation Signal compensation
US7129567B2 (en) * 2004-08-31 2006-10-31 Micron Technology, Inc. Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements
US7671630B2 (en) * 2005-07-29 2010-03-02 Synopsys, Inc. USB 2.0 HS voltage-mode transmitter with tuned termination resistance
KR100668515B1 (ko) 2005-09-28 2007-01-12 주식회사 하이닉스반도체 슬루-레이트가 제어된 오픈-루프 출력 드라이버
KR100666177B1 (ko) * 2005-09-30 2007-01-09 삼성전자주식회사 모드 레지스터 셋트를 이용하여 초기강화 드라이버의 임피던스 및 강도를 제어하는 출력 드라이버
US7737003B2 (en) * 2005-10-11 2010-06-15 International Business Machines Corporation Method and structure for optimizing yield of 3-D chip manufacture
KR100738961B1 (ko) * 2006-02-22 2007-07-12 주식회사 하이닉스반도체 반도체 메모리의 출력 드라이빙 장치
JP4901286B2 (ja) * 2006-04-24 2012-03-21 株式会社東芝 半導体装置及びメモリ回路システム
US8384417B2 (en) * 2008-09-10 2013-02-26 Qualcomm Incorporated Systems and methods utilizing redundancy in semiconductor chip interconnects
US7796446B2 (en) * 2008-09-19 2010-09-14 Qimonda Ag Memory dies for flexible use and method for configuring memory dies
US20100121994A1 (en) 2008-11-10 2010-05-13 International Business Machines Corporation Stacked memory array
US8259461B2 (en) * 2008-11-25 2012-09-04 Micron Technology, Inc. Apparatus for bypassing faulty connections
US7888968B2 (en) * 2009-01-15 2011-02-15 International Business Machines Corporation Configurable pre-emphasis driver with selective constant and adjustable output impedance modes
KR20100105040A (ko) * 2009-03-20 2010-09-29 주식회사 하이닉스반도체 반도체 메모리 장치
KR101048795B1 (ko) 2009-07-10 2011-07-15 주식회사 하이닉스반도체 반도체 장치
US9160349B2 (en) 2009-08-27 2015-10-13 Micron Technology, Inc. Die location compensation
US8315068B2 (en) * 2009-11-12 2012-11-20 International Business Machines Corporation Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same
US8943224B2 (en) 2010-03-15 2015-01-27 Rambus Inc. Chip selection in a symmetric interconnection topology
KR20110119087A (ko) 2010-04-26 2011-11-02 삼성전자주식회사 스택형 반도체 장치
CN102709272B (zh) * 2011-03-28 2015-01-21 财团法人工业技术研究院 硅通孔的容错单元与方法
US8587340B2 (en) * 2012-03-27 2013-11-19 Micron Technology, Inc. Apparatuses including scalable drivers and methods

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1574356A (zh) * 2003-06-03 2005-02-02 日立环球储存科技荷兰有限公司 超低成本固态存储器
CN1734669A (zh) * 2004-06-22 2006-02-15 三星电子株式会社 半导体存储器件及其阵列内部电源电压产生方法
CN101060010A (zh) * 2006-04-21 2007-10-24 松下电器产业株式会社 半导体存储装置
US20110161748A1 (en) * 2009-12-31 2011-06-30 Bryan Casper Systems, methods, and apparatuses for hybrid memory
CN102376356A (zh) * 2010-08-12 2012-03-14 台湾积体电路制造股份有限公司 带有减小的栅极电阻的字线驱动器器件及其制造方法
CN102386172A (zh) * 2010-08-27 2012-03-21 海力士半导体有限公司 半导体集成电路

Also Published As

Publication number Publication date
US9564878B2 (en) 2017-02-07
US20140070860A1 (en) 2014-03-13
JP6082803B2 (ja) 2017-02-15
TW201403616A (zh) 2014-01-16
KR101936980B1 (ko) 2019-01-09
US8587340B2 (en) 2013-11-19
KR20140140076A (ko) 2014-12-08
TWI570739B (zh) 2017-02-11
EP2831876A1 (en) 2015-02-04
JP2015520432A (ja) 2015-07-16
EP2831876A4 (en) 2015-11-11
EP2831876B1 (en) 2019-08-28
US8836395B2 (en) 2014-09-16
US20150137866A1 (en) 2015-05-21
US20130257489A1 (en) 2013-10-03
CN104285254A (zh) 2015-01-14
WO2013148199A1 (en) 2013-10-03

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