KR101674274B1 - Iii-v 에피택셜층들을 성장시키는 방법 - Google Patents

Iii-v 에피택셜층들을 성장시키는 방법 Download PDF

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KR101674274B1
KR101674274B1 KR1020147003437A KR20147003437A KR101674274B1 KR 101674274 B1 KR101674274 B1 KR 101674274B1 KR 1020147003437 A KR1020147003437 A KR 1020147003437A KR 20147003437 A KR20147003437 A KR 20147003437A KR 101674274 B1 KR101674274 B1 KR 101674274B1
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조프 델륀
스테판 디그루트
마리안느 제르맹
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에피간 엔브이
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
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    • H01L21/76213Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
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    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H10D30/471High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H10D30/4755High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
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    • H10D62/8503Nitride Group III-V materials, e.g. AlN or GaN

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  • Junction Field-Effect Transistors (AREA)
KR1020147003437A 2011-07-18 2012-07-06 Iii-v 에피택셜층들을 성장시키는 방법 Active KR101674274B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GBGB1112327.0A GB201112327D0 (en) 2011-07-18 2011-07-18 Method for growing III-V epitaxial layers
GB1112327.0 2011-07-18
PCT/EP2012/063317 WO2013010828A1 (en) 2011-07-18 2012-07-06 Method for growing iii-v epitaxial layers

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KR20140063593A KR20140063593A (ko) 2014-05-27
KR101674274B1 true KR101674274B1 (ko) 2016-11-08

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US (2) US9230803B2 (enExample)
EP (1) EP2735030B1 (enExample)
JP (1) JP6120841B2 (enExample)
KR (1) KR101674274B1 (enExample)
CN (1) CN103765592B (enExample)
GB (1) GB201112327D0 (enExample)
WO (1) WO2013010828A1 (enExample)

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US10074721B2 (en) * 2016-09-22 2018-09-11 Infineon Technologies Ag Method of fabricating a semiconductor wafer that includes producing a planarised surface having both a mesa surface and an insulating layer surface
US10734303B2 (en) * 2017-11-06 2020-08-04 QROMIS, Inc. Power and RF devices implemented using an engineered substrate structure
JP2021525961A (ja) * 2018-05-29 2021-09-27 アイキューイー ピーエルシーIQE plc 緩衝材にわたって形成される光電子デバイス
US10741666B2 (en) * 2018-11-19 2020-08-11 Vanguard International Semiconductor Corporation High electron mobility transistor and method for forming the same
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WO2022217539A1 (zh) * 2021-04-15 2022-10-20 苏州晶湛半导体有限公司 半导体结构及其制作方法
WO2024113095A1 (en) * 2022-11-28 2024-06-06 Innoscience (suzhou) Semiconductor Co., Ltd. Nitride-based semiconductor device and method for manufacturing the same
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US9230803B2 (en) 2016-01-05
US20160099309A1 (en) 2016-04-07
EP2735030A1 (en) 2014-05-28
US9748331B2 (en) 2017-08-29
KR20140063593A (ko) 2014-05-27
EP2735030B1 (en) 2017-03-15
US20140167114A1 (en) 2014-06-19
WO2013010828A1 (en) 2013-01-24
CN103765592B (zh) 2017-09-19
GB201112327D0 (en) 2011-08-31
JP6120841B2 (ja) 2017-04-26
JP2014521229A (ja) 2014-08-25
CN103765592A (zh) 2014-04-30

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