KR101573812B1 - Ｓｏｉ 웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼 - Google Patents

Ｓｏｉ 웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼 Download PDF

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KR101573812B1
KR101573812B1 KR1020117004285A KR20117004285A KR101573812B1 KR 101573812 B1 KR101573812 B1 KR 101573812B1 KR 1020117004285 A KR1020117004285 A KR 1020117004285A KR 20117004285 A KR20117004285 A KR 20117004285A KR 101573812 B1 KR101573812 B1 KR 101573812B1
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South Korea
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wafer
layer
soi
soi wafer
thickness
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Korean (ko)
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KR20110047201A (ko
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사토시 오카
수수무 쿠와바라
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신에쯔 한도타이 가부시키가이샤
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/24—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using chemical vapour deposition [CVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium

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  • Recrystallisation Techniques (AREA)
KR1020117004285A 2008-08-28 2009-07-29 Ｓｏｉ 웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼 Active KR101573812B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JPJP-P-2008-219981 2008-08-28
JP2008219981A JP4666189B2 (ja) 2008-08-28 2008-08-28 Ｓｏｉウェーハの製造方法
PCT/JP2009/003573 WO2010023816A1 (ja) 2008-08-28 2009-07-29 Ｓｏｉウェーハの製造方法およびｓｏｉウェーハ

Publications (2)

Publication Number Publication Date
KR20110047201A KR20110047201A (ko) 2011-05-06
KR101573812B1 true KR101573812B1 (ko) 2015-12-02

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KR1020117004285A Active KR101573812B1 (ko) 2008-08-28 2009-07-29 Ｓｏｉ 웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼

Country Status (7)

Country Link
US (1) US8497187B2 (https=)
EP (1) EP2320450B1 (https=)
JP (1) JP4666189B2 (https=)
KR (1) KR101573812B1 (https=)
CN (1) CN102119435B (https=)
TW (1) TWI453819B (https=)
WO (1) WO2010023816A1 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5447111B2 (ja) * 2010-04-07 2014-03-19 信越半導体株式会社 Ｓｏｉウェーハの熱処理温度を求める方法及びランプ加熱型の気相成長装置における反応炉の温度管理方法
JP5440693B2 (ja) * 2010-04-08 2014-03-12 信越半導体株式会社 シリコンエピタキシャルウエーハ、シリコンエピタキシャルウエーハの製造方法、及び半導体素子又は集積回路の製造方法
JP6086031B2 (ja) * 2013-05-29 2017-03-01 信越半導体株式会社 貼り合わせウェーハの製造方法
WO2017218536A1 (en) * 2016-06-14 2017-12-21 Quora Technology, Inc. Engineered substrate structure for power and rf applications
JP6824115B2 (ja) * 2017-06-19 2021-02-03 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN107265399A (zh) * 2017-07-03 2017-10-20 上海先进半导体制造股份有限公司 硅片密封腔体的制作方法
TWI751570B (zh) * 2020-06-02 2022-01-01 合晶科技股份有限公司 半導體基板及其形成方法
CN113764433B (zh) * 2020-06-02 2025-02-07 合晶科技股份有限公司 半导体基板及其形成方法
JP7611718B2 (ja) * 2021-01-29 2025-01-10 浜松ホトニクス株式会社 レーザ加工装置、レーザ加工方法、及び貼合ウエハ
FR3119849B1 (fr) * 2021-02-12 2024-01-12 Soitec Silicon On Insulator Méthode de configuration pour ajuster les conditions de température d’un procédé d’épitaxie

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194539A (ja) * 2006-01-23 2007-08-02 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法およびｓｏｉウエーハ

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
JP2000349266A (ja) 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
JP2004247610A (ja) * 2003-02-14 2004-09-02 Canon Inc 基板の製造方法
JP4251054B2 (ja) * 2003-10-01 2009-04-08 株式会社デンソー 半導体装置の製造方法
KR101111436B1 (ko) * 2004-09-13 2012-02-15 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ 웨이퍼의 제조 방법 및 ｓｏｉ 웨이퍼
JP4587034B2 (ja) * 2005-03-16 2010-11-24 信越半導体株式会社 Ｓｏｉウェーハの設計方法
JP5082299B2 (ja) * 2006-05-25 2012-11-28 株式会社Ｓｕｍｃｏ 半導体基板の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007194539A (ja) * 2006-01-23 2007-08-02 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法およびｓｏｉウエーハ

Also Published As

Publication number Publication date
KR20110047201A (ko) 2011-05-06
US20110117727A1 (en) 2011-05-19
CN102119435B (zh) 2014-06-18
CN102119435A (zh) 2011-07-06
TWI453819B (zh) 2014-09-21
EP2320450B1 (en) 2013-08-28
WO2010023816A1 (ja) 2010-03-04
TW201025444A (en) 2010-07-01
JP4666189B2 (ja) 2011-04-06
US8497187B2 (en) 2013-07-30
JP2010056311A (ja) 2010-03-11
EP2320450A4 (en) 2011-09-28
EP2320450A1 (en) 2011-05-11

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