KR101499974B1 - 배선기판 및 그의 제조방법 - Google Patents

배선기판 및 그의 제조방법 Download PDF

Info

Publication number
KR101499974B1
KR101499974B1 KR1020080109006A KR20080109006A KR101499974B1 KR 101499974 B1 KR101499974 B1 KR 101499974B1 KR 1020080109006 A KR1020080109006 A KR 1020080109006A KR 20080109006 A KR20080109006 A KR 20080109006A KR 101499974 B1 KR101499974 B1 KR 101499974B1
Authority
KR
South Korea
Prior art keywords
semiconductor element
insulating layer
stiffener
wiring board
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020080109006A
Other languages
English (en)
Korean (ko)
Other versions
KR20090048328A (ko
Inventor
아키오 호리우치
히로시 요코타
Original Assignee
신코 덴키 코교 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 신코 덴키 코교 가부시키가이샤 filed Critical 신코 덴키 코교 가부시키가이샤
Publication of KR20090048328A publication Critical patent/KR20090048328A/ko
Application granted granted Critical
Publication of KR101499974B1 publication Critical patent/KR101499974B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/40—Fillings or auxiliary members in containers, e.g. centering rings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
KR1020080109006A 2007-11-08 2008-11-04 배선기판 및 그의 제조방법 Active KR101499974B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007290789A JP5224784B2 (ja) 2007-11-08 2007-11-08 配線基板及びその製造方法
JPJP-P-2007-290789 2007-11-08

Publications (2)

Publication Number Publication Date
KR20090048328A KR20090048328A (ko) 2009-05-13
KR101499974B1 true KR101499974B1 (ko) 2015-03-06

Family

ID=40640740

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020080109006A Active KR101499974B1 (ko) 2007-11-08 2008-11-04 배선기판 및 그의 제조방법

Country Status (4)

Country Link
US (1) US8119929B2 (https=)
JP (1) JP5224784B2 (https=)
KR (1) KR101499974B1 (https=)
TW (1) TWI442860B (https=)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2886415B2 (ja) 1993-05-28 1999-04-26 東洋シヤッター株式会社 建物及び建物の改装方法
JP2886414B2 (ja) 1993-05-28 1999-04-26 東洋シヤッター株式会社 建物及び建物の改装方法
JP2905668B2 (ja) 1993-06-01 1999-06-14 東洋シヤッター株式会社 建物及び建物の改装方法
JP2886417B2 (ja) 1993-06-01 1999-04-26 東洋シヤッター株式会社 建物及び建物の改装方法
JP2886418B2 (ja) 1993-06-01 1999-04-26 東洋シヤッター株式会社 建物及び建物の改装方法
KR100704919B1 (ko) * 2005-10-14 2007-04-09 삼성전기주식회사 코어층이 없는 기판 및 그 제조 방법
US20110084375A1 (en) * 2009-10-13 2011-04-14 Freescale Semiconductor, Inc Semiconductor device package with integrated stand-off
JP2011138869A (ja) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd 多層配線基板の製造方法及び多層配線基板
JP2011138868A (ja) * 2009-12-28 2011-07-14 Ngk Spark Plug Co Ltd 多層配線基板
JP5302234B2 (ja) * 2010-02-08 2013-10-02 ルネサスエレクトロニクス株式会社 半導体装置
JP2011181542A (ja) 2010-02-26 2011-09-15 Ngk Spark Plug Co Ltd 多層配線基板及びその製造方法
US8609995B2 (en) 2010-07-22 2013-12-17 Ngk Spark Plug Co., Ltd. Multilayer wiring board and manufacturing method thereof
TWI419277B (zh) * 2010-08-05 2013-12-11 日月光半導體製造股份有限公司 線路基板及其製作方法與封裝結構及其製作方法
JPWO2012029526A1 (ja) * 2010-08-30 2013-10-28 住友ベークライト株式会社 半導体パッケージおよび半導体装置
WO2012029579A1 (ja) * 2010-08-30 2012-03-08 住友ベークライト株式会社 半導体パッケージおよび半導体装置
JPWO2012029549A1 (ja) * 2010-08-30 2013-10-28 住友ベークライト株式会社 半導体パッケージおよび半導体装置
JP2012069739A (ja) * 2010-09-24 2012-04-05 Shinko Electric Ind Co Ltd 配線基板の製造方法
US9282626B2 (en) * 2010-10-20 2016-03-08 Lg Innotek Co., Ltd. Printed circuit board and method for manufacturing the same
US20130241058A1 (en) * 2012-03-16 2013-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Wire Bonding Structures for Integrated Circuits
JP2014045025A (ja) * 2012-08-24 2014-03-13 Sony Corp 配線基板及び配線基板の製造方法
TWI473552B (zh) * 2012-11-21 2015-02-11 欣興電子股份有限公司 具有元件設置區之基板結構及其製程
US9263376B2 (en) * 2013-04-15 2016-02-16 Intel Deutschland Gmbh Chip interposer, semiconductor device, and method for manufacturing a semiconductor device
US9832860B2 (en) 2014-09-26 2017-11-28 Intel Corporation Panel level fabrication of package substrates with integrated stiffeners
KR102359873B1 (ko) * 2015-06-16 2022-02-08 삼성전자주식회사 패키지 기판 및 이를 포함하는 반도체 패키지
US10177060B2 (en) 2016-10-21 2019-01-08 Powertech Technology Inc. Chip package structure and manufacturing method thereof
KR102894105B1 (ko) * 2020-07-13 2025-12-02 삼성전자주식회사 반도체 패키지
EP4432345B1 (en) * 2023-03-16 2025-05-07 Hitachi Energy Ltd Insulated metal substrate and method for producing an insulated metal substrate
WO2025243529A1 (ja) * 2024-05-24 2025-11-27 株式会社レゾナック 半導体パッケージを製造する方法、半導体パッケージ用熱硬化性接着剤、半導体パッケージ、及び半導体モジュール

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020062970A1 (en) * 2000-11-30 2002-05-30 International Business Machines Corporation I/c chip assembly

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1050877A (ja) * 1996-07-30 1998-02-20 Toshiba Corp 半導体パッケージ
US5900312A (en) * 1996-11-08 1999-05-04 W. L. Gore & Associates, Inc. Integrated circuit chip package assembly
US5940277A (en) * 1997-12-31 1999-08-17 Micron Technology, Inc. Semiconductor device including combed bond pad opening, assemblies and methods
US6224711B1 (en) * 1998-08-25 2001-05-01 International Business Machines Corporation Assembly process for flip chip package having a low stress chip and resulting structure
US6569710B1 (en) * 1998-12-03 2003-05-27 International Business Machines Corporation Panel structure with plurality of chip compartments for providing high volume of chip modules
JP2000243869A (ja) 1999-02-18 2000-09-08 Ngk Spark Plug Co Ltd 配線基板
JP3635219B2 (ja) 1999-03-11 2005-04-06 新光電気工業株式会社 半導体装置用多層基板及びその製造方法
US6437436B2 (en) * 2000-01-20 2002-08-20 Ang Technologies Inc. Integrated circuit chip package with test points
KR100394809B1 (ko) * 2001-08-09 2003-08-14 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP4390541B2 (ja) * 2003-02-03 2009-12-24 Ｎｅｃエレクトロニクス株式会社 半導体装置及びその製造方法
US20050121757A1 (en) * 2003-12-04 2005-06-09 Gealer Charles A. Integrated circuit package overlay
US7189929B2 (en) * 2004-01-16 2007-03-13 Hewlett-Packard Development Company, L.P. Flexible circuit with cover layer
JP4528062B2 (ja) * 2004-08-25 2010-08-18 富士通株式会社 半導体装置およびその製造方法
US20080099910A1 (en) * 2006-08-31 2008-05-01 Ati Technologies Inc. Flip-Chip Semiconductor Package with Encapsulant Retaining Structure and Strip

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020062970A1 (en) * 2000-11-30 2002-05-30 International Business Machines Corporation I/c chip assembly

Also Published As

Publication number Publication date
KR20090048328A (ko) 2009-05-13
TW200934347A (en) 2009-08-01
US8119929B2 (en) 2012-02-21
JP2009117703A (ja) 2009-05-28
JP5224784B2 (ja) 2013-07-03
US20090126981A1 (en) 2009-05-21
TWI442860B (zh) 2014-06-21

Similar Documents

Publication Publication Date Title
KR101499974B1 (ko) 배선기판 및 그의 제조방법
KR101985020B1 (ko) 배선기판의 제조방법
JP5144222B2 (ja) 配線基板及びその製造方法
KR101412720B1 (ko) 배선 기판, 그 제조 방법, 및 배선 기판을 가지는 반도체 장치
KR101610969B1 (ko) 배선기판 및 그 제조방법
US8450853B2 (en) Semiconductor device and a method of manufacturing the same, and an electronic device
KR20050077270A (ko) 상하도전층의 도통부를 갖는 반도체장치 및 그 제조방법
US7946856B2 (en) Connector for interconnecting surface-mount devices and circuit substrates
KR20060053087A (ko) 기판, 반도체 장치, 기판 제조 방법, 및 반도체 장치 제조방법
KR20090069852A (ko) 패키지용 기판 및 그 제조방법
JP2009231635A (ja) 配線基板及びその製造方法、及び半導体装置及びその製造方法
TW201832298A (zh) 電子封裝構件及其製作方法
KR100346899B1 (ko) 반도체장치 및 그 제조방법
CN100376030C (zh) 电路装置及其制造方法
US7171744B2 (en) Substrate frame
JP2011243457A (ja) ソケット
JP4065145B2 (ja) 電子部品用ソケットの製造方法
JP5386647B2 (ja) 配線基板
CN113784529B (zh) 电路板及其制作方法
JP7715590B2 (ja) 配線基板及び配線基板の製造方法
JP4064829B2 (ja) 半導体装置およびこれに用いる回路基板
KR100891652B1 (ko) 반도체 칩 실장용 기판
JP2006339276A (ja) 接続用基板及びその製造方法
JP2024154171A (ja) 半導体装置およびその製造方法
JP2025117290A (ja) 配線基板及び配線基板の製造方法

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

FPAY Annual fee payment

Payment date: 20180219

Year of fee payment: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

FPAY Annual fee payment

Payment date: 20200129

Year of fee payment: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000