CN100376030C - 电路装置及其制造方法 - Google Patents
电路装置及其制造方法 Download PDFInfo
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Abstract
一种电路装置及其制造方法,构成焊盘(12)的侧面露出的电路装置(10)。电路装置(10)包括:垫板(11)及焊盘(12);在垫板(11)上固定的电路元件(9);密封垫板(11)、焊盘(12)及电路元件(9)的绝缘性树脂(14),其中,在绝缘性树脂(14)侧面部部分地形成凹部(15),形成配置在周边部的导电图案的侧面部自凹部(15)露出的结构。通过在侧面露出形成和外部连接的连接电极的焊盘(12),在电路装置(10)的安装中,由焊剂(19)形成的轮廓在装置的侧部形成。
Description
技术领域
本发明涉及自对整体进行密封的绝缘性树脂的侧面露出作为电极的导电图案的电路装置及其制造方法。
背景技术
以往,由于在电子设备上设置的电路装置被使用在手机、笔记本电脑等上,因而寻求小型化、薄型化及轻量化。现有型的电路装置中,有被称为CSP(Chip Size Package芯片尺寸封装)的装置(例如参照专利文献1)。
图18中,采用玻璃环氧树脂衬底51作为支撑衬底,显示比芯片尺寸大若干的CSP50。在此,说明在玻璃环氧树脂衬底51上安装有晶体管芯片56的情况。
在该玻璃环氧树脂衬底51的表面形成第一电极52、第二电极53及垫板57,在其背面形成第一背面电极54和第二背面电极55。而后,所述第一电极52和第一背面电极54与第二电极53和第二背面电极55介由通孔59电连接。另外,在垫板57上固定所述裸的晶体管芯片56,并介由金属细线58连接晶体管发射极电极和第一电极52,介由金属细线58连接晶体管基极和第二电极53。另外,在玻璃环氧树脂衬底51上设置树脂层60,以覆盖晶体管芯片T。
所述CSP50采用玻璃环氧树脂衬底51,但和晶片级CSP不同,自芯片T至外部连接用背面电极54、55的延伸结构简单,具有可廉价制造的优点。
专利文献
特开平2001-339151号公报(第一页,图1)
发明内容
在所述CSP等现有型电路装置中,和外部进行电连接的第一背面电极54及第二背面电极55被设置在装置的背面。而后,利用回流工序等,通过在背面电极上黏附焊锡等焊剂,进行装置向母板等的安装。但是,在安装后,由于在CSP50背面和母板的微小的间隙形成焊剂,故视觉判定焊剂是否呈恰当形状是困难的。
另外,第一背面电极54及第二背面电极55形成在玻璃环氧树脂衬底51的背面,以其厚度的量凸状形成。由此,在搬运完成的CSP50的工序中,具有凸状形成的背面电极会剥离的问题。
本发明是鉴于这样的问题而开发的,本发明的目的在于,提供自密封整体的绝缘性树脂侧面露出导电图案的电路装置及其制造方法。
本发明第一方面提供一种电路装置,其包括:导电图案;电路元件,其固定在所述导电图案上;绝缘性树脂,至少露出所述导电图案的下面,密封所述导电图案及所述电路元件,其中,在所述绝缘性树脂侧面部局部形成凹部,在周边部配置的所述导电图案的下面及侧面部自所述凹部露出。通过露出周边部配置的导电图案的侧面,可在露出的导电图案的侧面部黏附焊锡等焊剂,进行电路装置安装,可视觉地判定安装的优劣。
本发明第二方面提供一种电路装置的制造方法,其包括如下工序:准备导电箔,在至少除去形成多个电路元件搭载部的导电图案外的区域的所述导电箔上形成比所述导电箔厚度浅的分离槽的工序;在所需的所述导电图案的所述各搭载部上固定电路元件的工序;由绝缘性树脂共同模制,将各搭载部的所述电路元件一并覆盖,并在所述分离槽中填充的工序;将未设置所述分离槽的厚度部分的所述导电箔除去,直至所述绝缘性树脂露出的工序;通过除去与所述各搭载部分界线对应的位置的所述导电图案形成槽,从而使所述导电图案侧面部露出的工序;通过沿所述分界线切割将所述绝缘性树脂分离的工序。
本发明第三方面提供一种电路装置的制造方法,其包括如下工序:准备导电箔,在至少除去形成多个电路元件搭载部的导电图案外的区域的所述导电箔上形成比所述导电箔厚度浅的分离槽的工序;在所需的所述导电图案的所述各搭载部上固定电路元件的工序;由绝缘性树脂共同模制,将各搭载部的所述电路元件一并覆盖,并在所述分离槽中填充的工序;通过除去所述分离槽的残留的厚度部分,将所述导电图案电分离,且通过除去与所述各搭载部分界线对应的位置的所述导电图案形成槽,从而使所述导电图案侧面部露出的工序;通过沿所述分界线切割,将所述绝缘性树脂分离的工序。
附图说明
图1是说明本发明电路装置的立体图;
图2是说明本发明电路装置的平面图(A)、剖面图(B);
图3是说明本发明电路装置的平面图(A)、剖面图(B);
图4是说明本发明电路装置的平面图(A)、剖面图(B);
图5是说明本发明电路装置的立体图(A)、剖面图(B);
图6是说明本发明电路装置制造方法的剖面图(A)、平面图(B);
图7是说明本发明电路装置制造方法的剖面图;
图8是说明本发明电路装置制造方法的剖面图(A)、平面图(B);
图9是说明本发明电路装置制造方法的剖面图(A)、平面图(B);
图10是说明本发明电路装置制造方法的剖面图(A)、平面图(B);
图11是说明本发明电路装置制造方法的剖面图;
图12是说明本发明电路装置制造方法的剖面图;
图13是说明本发明电路装置制造方法的剖面图;
图14是说明本发明电路装置制造方法的剖面图;
图15是说明本发明电路装置制造方法的剖面图;
图16是说明本发明电路装置制造方法的剖面图;
图17是说明本发明电路装置制造方法的剖面图(A)、平面图(B);
图18是说明现有电路装置的剖面图。
具体实施方式
说明电路装置10的结构的第一实施例
参照图1及图2说明本发明电路装置10的构成等。图1是电路装置10的立体图,图2(A)是电路装置10的平面图,图2(B)是其剖面图。
参照图1,电路装置10具有如下结构,其包括:导电图案;电路装置9,其被固定在导电图案上;绝缘性树脂14,至少露出导电图案的下面,密封导电图案及电路元件9,其中,在绝缘性树脂14侧面部部分地形成凹部15,周边部配置的导电图案的侧面部自凹部15露出。同图中,导电图案由垫板11及焊盘12构成,在装置周边部配置的焊盘12的侧面自树脂侧面露出。以下说明上述各构成要素。
由导电图案形成的垫板11及焊盘12由铜等金属构成,露出下面,埋入绝缘性树脂14。垫板11被配置在装置的中央部,在其上部通过焊剂固定电路元件9。另外,垫板11露出背面,由绝缘性树脂14密封。参照图2(A),焊盘12被包围垫板11配置在周边部。在周边部配置的焊盘12中,面向外部的侧面和下面自绝缘性树脂14露出,未面向外部的三个侧面和上面由绝缘性树脂密封。另外,焊盘12侧面露出的位置的绝缘性树脂14的侧面形成凹部15,由该凹部15露出焊盘12的侧面。另外,在垫板11及焊盘12上面形成镀膜17。
参照图2(B),自垫板11及焊盘12的绝缘性树脂14露出的面设有采用铜等形成的镀层18。具体地说,焊盘12在下面设有镀层18。焊盘12面向外部的侧面及下面利用镀层18覆盖。
作为电路元件9,在此采用半导体元件,介由焊剂固定在垫板11上。电路元件9的电极和焊盘12介由金属细线13电连接。另外,作为半导体元件的电路元件9也可以通过面朝下法安装。另外,也可以取代半导体元件安装多个其它的有源元件或无源元件。
露出导电图案的背面,绝缘性树脂14密封整体。在此,密封电路元件9、金属细线13、垫板11及焊盘12。作为绝缘性树脂14的材料,可采用利用传递模形成的热硬性树脂或利用注入模形成的热塑性树脂。在本发明中,在由绝缘性树脂14构成的电路装置10的侧面部形成凹部15。自凹部15露出焊盘12的侧面部。另外,参照图2(B),镀膜17自凹部15露出。
参照图3说明其它形态的电路装置10A的构成。同图显示的电路装置10A包括:导电图案,其由槽16电分离;电路元件9,其固定在导电图案上;绝缘性树脂14,至少露出导电图案的下面,密封导电图案及电路元件9,其中,在绝缘性树脂14的侧面部部分地形成凹部15,在周边部配置的导电图案的侧面部自凹部15露出。在同图中,导电图案由垫板11及焊盘12构成,配置在装置周边部的焊盘12的侧面自树脂的侧面露出。
下面说明和图1及图2显示的电路装置10的不同点。电路装置10A中形成垫板11及焊盘12的导电图案的形状和电路装置10不同。在同图显示的电路装置10A中,垫板11及焊盘12延伸在分离槽8中填充的绝缘性树脂14的下方。垫板11及焊盘12利用槽16电分离。
参照图3(B),垫板11侧面部的一部分和底面自绝缘性树脂14露出,由镀层18覆盖。垫板11自绝缘性树脂14露出面向外部的侧面部和下面。另外,关于垫板11的不面向外部的侧面,其局部自绝缘性树脂14露出。自绝缘性树脂14露出的焊盘12的侧面及下面由镀层18覆盖。
参照图4说明其它形态电路装置10的结构。在此显示的电路装置10的结构和图1显示的电路装置具有基本相同的结构,不同点在于,由垫板11及焊盘12构成的导电图案的上面由被覆树脂7覆盖。被覆树脂7除导电图案的上面外,还覆盖分离槽8的表面。在各焊盘12的上面形成开口部7A,自开口部7A底部部分地露出焊盘12的表面。介由金属细线13电连接露出的焊盘12的表面和电路元件13。
作为被覆树脂7的材料,可全部采用热硬性树脂或热塑性树脂。另外,作为被覆树脂7,可采用感光性树脂或非感光性树脂。在被覆树脂7是感光性树脂时,可通过进行曝光及显影形成开口部7A。被覆树脂7是非感光性树脂时,可通过激光形成开口部7A。
参照图5说明将图1显示的电路装置10固定在安装衬底9上的状态。
参照图5(A)及图5(B),可在电路装置10侧面部露出的焊盘12的侧面部利用黏附焊锡等焊剂19进行安装衬底5上的导电路6和电路装置10的电连接。在此,焊剂19和露出的焊盘12的侧面在导电路6的表面接触,形成焊接轮廓。
本发明的特征在于,焊盘12的侧面由绝缘性树脂14露出。具体地说,自绝缘性树脂14侧面上形成的凹部15露出焊盘12的侧面。因此,在安装衬底5上的导电路6上安装电路装置10时,在露出的焊盘12的侧面和导电部6上可形成由焊剂19形成的轮廓。这样,由于由焊剂19形成的轮廓形成在电路装置10的周边部,故可视觉地确认是否恰当地形成焊剂19。
另外,本发明的特征在于,在焊盘12露出的绝缘性树脂14的侧面形成凹部15。具体地说,在露出外部的焊盘12的侧面位于形成装置外形的绝缘性树脂14的侧面的内侧。由此,在运送作为成品的电路装置10时,可防止焊盘12自绝缘性树脂脱落。另外,由于由在安装电路装置10时形成的焊剂19形成的轮廓的上端部也被容纳在凹部15内,故可最大限度地防止焊剂19的脱落。
说明电路装置10制造方法的第二实施例。
本发明的电路装置10由如下的工序制造。即,包括:准备导电箔20,在至少除去形成多个电路元件9的搭载部25的导电图案的区域外的导电箔20上形成比导电箔20厚度浅的分离槽8的工序;在规定的所述导电图案的各搭载部25上固定电路元件9的工序;将各搭载部25的电路元件9一并覆盖,并填充分离槽8,由绝缘性树脂13共同模制的工序;将未设置分离槽8的厚度部分的导电箔20除去的工序;通过除去与各搭载部25分界线对应的位置的导电图案形成槽,使所述导电图案侧面部露出的工序;通过沿所述分界线切割将所述绝缘性树脂分离的工序。
另外,电路装置10也可由如下工序制造。即,包括:准备导电箔20,在至少除去形成多个电路元件9的搭载部25的导电图案的区域外的导电箔20上形成比导电箔20厚度浅的分离槽8的工序;在规定的导电图案的各搭载部25上固定电路元件9的工序;将各搭载部25的电路元件9一并覆盖,并填充所述分离槽8,由绝缘性树脂13共同模制的工序;通过除去分离槽8的残留的厚度部分将所述导电图案电分离,通过除去与各搭载部25的分界线对应的位置的导电图案形成槽16,使导电图案侧面部露出的工序;通过沿分界线切割将所述绝缘性树脂13分离的工序。以下参照图6~图17说明本发明的各工序。
本发明的第一工序在于,如图6~图8所示,准备导电箔20,在至少除去形成多个电路元件9的搭载部25的导电图案的区域外的导电箔20上形成比导电箔20厚度浅的分离槽8。
在本工序中,首先,如图6(A),准备片状导电箔20。该导电箔20考虑焊剂的黏附性、接合性及镀敷性选择其材料,作为材料采用以Cu为主材料的导电箔、以Al为主材料的导电箔或由Fe-Ni等合金构成的导电箔等。导电箔20的厚度考虑以后的蚀刻,最好为10um~300um,但是,即使在300um以上10um以下也基本可以。如后所述,只要能形成比导电箔20的厚度浅的分离槽8即可。
具体地说,如图6(B)所示,在矩形导电箔20上间隔排列4~5个形成多个搭载部25的模块22。在各模块22之间设置缝隙23,吸收模制工序等的加热处理产生的导电箔20的应力。另外,在导电箔20的上下周端以一定的间隔设置标示孔24,用于各工序的定位。然后形成导电图案。
首先,如图7所示,在导电箔20上对光致抗蚀剂PR制图,以使除去作为构成焊盘12及垫板11的导电图案的区域外的导电箔20露出。而后,如图8(A)所示,选择地蚀刻导电箔20。
图8(B)显示具体的导电图案。本图是放大图6(B)中显示的一个模块22的图。虚线包围的区域是一个搭载部25,在一个模块22上两行两列矩阵状地配列多个搭载部25,在每个各搭载部25上设置同一导电图案。在各模块周边设置框状图案26,与其稍分开,在其内侧设置切割时的对位标记27。框状图案26用于和模制模型的嵌合,另外,在导电箔20的背面蚀刻后,具有加强绝缘性树脂14的作用。在此,导电图案构成各搭载部25的垫板11及焊盘12。另外,矩阵状邻接的各搭载部25的焊盘12连续细长地形成。细长形成的焊盘12在以后的工序中利用蚀刻被电分离。
如图9所示,本发明的第二工序在于,在规定导电图案的各搭载部25上固定电路元件9,将电路元件9的电极和规定的导电图案引线接合。
在此,作为电路元件9,在垫板11上固定半导体元件。其后,将各搭载部的电路元件9的各电极,利用采用热压装进行的球形接合及采用超声波进行的楔形接合一并进行引线接合。
如图10所示,本发明的第三工序在于,将各搭载部25的电路元件9一并覆盖,并在分离槽8中填充,由绝缘性树脂13共同模制。
在本工序中,如图10(A)所示,绝缘性树脂14完全覆盖电路元件9及多个导电图案,在分离槽8中填充绝缘性树脂14,和分离槽8嵌合而紧固地结合。利用绝缘性树脂14支撑导电图案。
另外,本工序可利用传递模、注入模或浇注实现。作为树脂材料,环氧树脂等热硬性树脂可由传递模实现,聚酰亚胺树脂、硫化聚苯等热塑性树脂可由注入模实现。
在本工序中,当进行传递模或注入模封装时,如图10(B)所示,各模块22在一个共同的模制模型中收纳搭载部63,按每个模块利用一个绝缘性树脂14共同地进行模制。
本发明的特征在于,在覆盖绝缘性树脂14之前,将形成导电图案的导电箔20作为支撑衬底。另外,由于分离槽8比导电箔的厚度更浅地形成,故导电箔20未作为图案一个个地分离。从而,片状导电箔20可整体处理,在模制绝缘性树脂时,向模型的搬运、向模型的安装的作业非常轻松。
本发明的第四工序在于,参照图11~图13,除去未设置分离槽8的厚度部分的导电箔20,利用除去与各搭载部25分界线对应的位置的导电图案形成槽16,使导电图案的侧面部露出。
本工序是化学及/或物理除去导电箔20的背面,作为导电图案分离的工序。该工序利用研磨、研削、蚀刻、激光金属蒸发等施行。在实验中,整面湿蚀导电箔20,自分离槽8露出绝缘性树脂14。其结果形成垫板11及焊盘12并电分离。该结果形成在绝缘性树脂14上露出导电图案背面的结构。
其次,参照图12,为除去与各搭载部25分界线对应的位置的焊盘12,在背面覆盖抗蚀剂。在各搭载部25的分界部,设置抗蚀剂30的开口部,该开口部宽度的形成比进行切割的刀片的宽度大。另外,该开口部的宽度也可以形成得比切割刀的宽度加上其位置精度的长度更大。
其次,参照图13,通过进行蚀刻,将与各搭载部25分界线相对应的位置的焊盘12除去,形成槽16。另外,形成槽16,以使位于模块22周端部的焊盘12的侧面露出。这样,将抗蚀剂开口部的宽度设定为比进行切割的刀片更宽进行蚀刻,可在进行切割的工序仅切除绝缘性树脂14。从而,可防止因切割金属产生毛刺的现象。由此,在焊盘12的侧面露出的位置的绝缘性树脂14上形成凹部15。
参照图14及图15说明本发明的其它形态的第四工序。本工序在于,通过除去分离槽8的残留的厚度部分,电分离导电图案,通过除去与各搭载部25的分界线对应的位置的导电图案形成槽16,使导电图案的侧面部露出。
首先,参照图14,将形成分离槽8的位置的导电箔20背面和对应各搭载部25的分界线的位置的导电箔20的背面露出,形成抗蚀剂30。
而后,如图15所示,通过进行蚀刻,形成第一槽16A及第二槽16B,将各导电图案电分离。第一槽16A由各搭载部25的分界线将焊盘12电分离。而第二槽16B具有将各搭载部25的垫板11和焊盘12电分离的作用。
在上述说明中,不进行导电箔20背面的整面除去,形成第一槽16A及第二槽16B。但是,也可以进行导电箔20背面的整面除去,使导电箔20一定程度形成得较薄,然后形成第一槽16A及第二槽16B。
本发明的第五工序在于,如图16所示,在自绝缘性树脂14露出的导电图案的表面形成镀层18。
在本工序中,在自密封整体的绝缘性树脂14露出的垫板11及焊盘12上形成镀层18。垫板11在从绝缘性树脂14露出的下面形成镀层18。焊盘12在从绝缘性树脂14露出的侧面及下面形成镀层18。在此,镀层18的形成可利用电解电镀法或无电解镀敷法进行。另外,在利用电解电镀法进行镀膜18的形成时,由于焊盘12及垫板11利用金属细线13及镀膜17电连接,故可将一个焊盘12或垫板11作为电极使用。
本发明的第六工序在于,如图17所示,按每一个各搭载部25通过切割分离绝缘性树脂14。
在本工序中,在切割装置的载置台上利用真空吸附模块22,利用切割刀49沿各搭载部25之间的切割线(点划线)切割分离槽8的绝缘性树脂14,分离出一个个电路装置。
在本工序中,切割刀49以大致切断绝缘性树脂14的切割深度进行切割,在由切割装置取下模块22后,由滚子进行分片即可。切割时预先确认所述的第一工序设置的各模块的对位标记47,以其为基准进行切割,
如上所述,由于在对应切割线的位置形成槽16,该位置的焊盘12被除去,故在此除去绝缘性树脂14和镀膜17。形成槽16的位置的焊盘12的侧面形成由树脂露出的结构。
另外,在所述的说明中,说明了利用绝缘性树脂13覆盖导电图案的方法,但是,在制造图4显示的电路装置时,利用被覆树脂7覆盖导电图案,形成开口部7A,然后形成绝缘性树脂13。这样,通过在焊盘12上设置开口部7A,形成被覆树脂7,可仅在开口部7A的位置形成镀层。
本发明可达到如下所示的效果。
第一,由于形成与外部连接的连接电极的焊盘12的侧面自绝缘性树脂14露出,故在使用焊剂19进行电路装置安装时,在电路装置的侧面形成由焊剂19形成的轮廓。从而,在进行安装后可视觉地进行焊剂黏附的良否确认。
第二,在焊盘12的侧面露出的位置的绝缘性树脂14的侧面形成凹部15。因此,由于露出的焊盘12的侧面被收纳在绝缘性树脂14的内部,故可防止焊盘12自绝缘性树脂14剥落。
第三,在模块22上以矩阵状形成多个搭载部25,通过除去与搭载部25的分界线对应的位置的导电图案,可使各搭载部25的导电图案侧面自侧部露出。
第四,通过由镀膜17电连接邻接的各搭载部25的焊盘12,可通过将导电箔20的一部分作为电极使用,用电解电镀法形成镀层18。
Claims (18)
1.一种电路装置,其特征在于,其包括:导电图案;电路元件,其固定在所述导电图案上;绝缘性树脂,至少露出所述导电图案的下面,密封所述导电图案及所述电路元件,其中,在所述绝缘性树脂的侧面部局部形成凹部,在周边部配置的所述导电图案的侧面部自所述凹部露出。
2.如权利要求1所述的电路装置,其特征在于,通过在露出的所述导电图案的所述侧面部及下面黏附焊剂进行电路装置的安装。
3.如权利要求1所述的电路装置,其特征在于,所述电路元件是半导体元件,在周边部配置的所述导电图案和所述半导体元件被电连接。
4.如权利要求1所述的电路装置,其特征在于,所述导电图案由固定所述电路元件的垫板及包围所述垫板配置的焊盘构成。
5.如权利要求1所述的电路装置,其特征在于,在由所述绝缘性树脂露出的所述导电图案的背面及侧面形成镀层。
6.如权利要求1所述的电路装置,其特征在于,在所述导电图案的表面形成覆盖树脂,介由所述覆盖树脂上设置的开口部将所述电路元件和所述导电图案电连接。
7.如权利要求6所述的电路装置,其特征在于,所述覆盖树脂由感光性树脂构成。
8.一种电路装置的制造方法,其特征在于,包括如下工序:准备导电箔,在所述导电箔的至少除去形成多个电路元件搭载部的导电图案外的区域上形成比所述导电箔厚度浅的分离槽的工序;在规定的所述导电图案的所述各搭载部上固定电路元件的工序;由绝缘性树脂共同模制,将各搭载部的所述电路元件一并覆盖,并在所述分离槽中填充的工序;将未设置所述分离槽的厚的部分的所述导电箔除去,直至所述绝缘性树脂露出的工序;通过除去与所述各搭载部的分界线对应的位置的所述导电图案形成槽,使所述导电图案的侧面部露出的工序;通过沿所述分界线切割将所述绝缘性树脂分离的工序。
9.如权利要求8所述的电路装置的制造方法,其特征在于,利用在所述导电图案表面上形成的镀膜将所述导电图案电连接,在从所述绝缘性树脂露出的所述导电图案的面上利用电镀法形成镀层。
10.如权利要求8所述的电路装置的制造方法,其特征在于,所述导电图案形成安装电路元件的垫板和与所述垫板邻接设置的焊盘。
11.如权利要求8所述的电路装置的制造方法,其特征在于,在从所述绝缘性树脂露出的所述导电图案的下面及侧面部黏附焊剂,进行电路装置的安装。
12.如权利要求8所述的电路装置的制造方法,其特征在于,通过使所述槽的宽度比进行所述切割的切割刀的宽度大,在从所述绝缘性树脂露出的所述导电图案的侧面部形成凹部。
13.如权利要求8所述的电路装置的制造方法,其特征在于,所述槽通过蚀刻形成。
14.一种电路装置的制造方法,其特征在于,包括如下工序:准备导电箔,在所述导电箔的至少除去形成多个电路元件搭载部的导电图案外的区域上形成比所述导电箔厚度浅的分离槽的工序;在所需的所述导电图案的所述各搭载部上固定电路元件的工序;由绝缘性树脂共同模制,将各搭载部的所述电路元件一并覆盖,并在所述分离槽中填充的工序;通过除去所述分离槽的残留的厚度部分将所述导电图案电分离,且通过除去与所述各搭载部的分界线对应的位置的所述导电图案形成槽,从而使所述导电图案侧面部露出的工序;通过沿所述分界线切割将所述绝缘性树脂分离的工序。
15.如权利要求14所述的电路装置的制造方法,其特征在于,所述导电图案形成安装电路元件的垫板和与所述垫板邻接设置的焊盘。
16.如权利要求14所述的电路装置的制造方法,其特征在于,在从所述绝缘性树脂露出的所述导电图案的下面及侧面部黏附焊剂,进行电路装置的安装。
17.如权利要求14所述的电路装置的制造方法,其特征在于,通过使所述槽的宽度比进行所述切割的切割刀的宽度大,在从所述绝缘性树脂露出的所述导电图案的侧面部形成凹部。
18.如权利要求14所述的电路装置的制造方法,其特征在于,所述槽利用蚀刻形成。
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US9899349B2 (en) | 2009-01-29 | 2018-02-20 | Semiconductor Components Industries, Llc | Semiconductor packages and related methods |
US20150035166A1 (en) * | 2009-01-29 | 2015-02-05 | Semiconductor Components Industries, Llc | Method for manufacturing a semiconductor component and structure |
US10199311B2 (en) | 2009-01-29 | 2019-02-05 | Semiconductor Components Industries, Llc | Leadless semiconductor packages, leadframes therefor, and methods of making |
US10163766B2 (en) | 2016-11-21 | 2018-12-25 | Semiconductor Components Industries, Llc | Methods of forming leadless semiconductor packages with plated leadframes and wettable flanks |
US8420447B2 (en) * | 2011-03-23 | 2013-04-16 | Stats Chippac Ltd. | Integrated circuit packaging system with flipchip leadframe and method of manufacture thereof |
CN103325745B (zh) * | 2012-03-23 | 2016-03-16 | 株式会社东芝 | 半导体装置 |
US8890301B2 (en) * | 2012-08-01 | 2014-11-18 | Analog Devices, Inc. | Packaging and methods for packaging |
US9070669B2 (en) | 2012-11-09 | 2015-06-30 | Freescale Semiconductor, Inc. | Wettable lead ends on a flat-pack no-lead microelectronic package |
US8535982B1 (en) | 2012-11-29 | 2013-09-17 | Freescale Semiconductor, Inc. | Providing an automatic optical inspection feature for solder joints on semiconductor packages |
US20140151865A1 (en) * | 2012-11-30 | 2014-06-05 | Thomas H. Koschmieder | Semiconductor device packages providing enhanced exposed toe fillets |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5623123A (en) * | 1993-06-10 | 1997-04-22 | Texas Instruments Incorporated | Semiconductor device package with small die pad and method of making same |
CN1253378A (zh) * | 1998-11-06 | 2000-05-17 | 日本电气株式会社 | 球栅阵列型半导体器件封装 |
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US6342730B1 (en) * | 2000-01-28 | 2002-01-29 | Advanced Semiconductor Engineering, Inc. | Low-pin-count chip package and manufacturing method thereof |
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US6281047B1 (en) * | 2000-11-10 | 2001-08-28 | Siliconware Precision Industries, Co., Ltd. | Method of singulating a batch of integrated circuit package units constructed on a single matrix base |
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US6608366B1 (en) * | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
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US5623123A (en) * | 1993-06-10 | 1997-04-22 | Texas Instruments Incorporated | Semiconductor device package with small die pad and method of making same |
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