JP4050200B2 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
- Publication number
- JP4050200B2 JP4050200B2 JP2003271700A JP2003271700A JP4050200B2 JP 4050200 B2 JP4050200 B2 JP 4050200B2 JP 2003271700 A JP2003271700 A JP 2003271700A JP 2003271700 A JP2003271700 A JP 2003271700A JP 4050200 B2 JP4050200 B2 JP 4050200B2
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- protrusion
- lead
- resin
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
請求項2にかかる発明の半導体装置は、裏面側に突出するようプレス成形された第1の突起部(12a)を延長部(12)に有するダイアイランド部(11)、該ダイアイランド部(11)の所定の辺に沿う方向に配列され、前記裏面側に突出するようプレス成形された第2の突起部(13a)を有する複数のリード部(13)からなるリードフレーム(10)と、前記ダイアイランド部(11)に搭載された半導体素子(40)と、前記半導体素子(40)と前記複数のリード部(13)とを接続する配線材料(50)と、前記第1の突起部(12a)と前記第2の突起部(13a)が裏面に露出するように前記リードフレーム(10)の裏面に配設された連結絶縁材料(30)と、前記リードフレーム(10)の前記半導体素子(40)および前記配線材料(50)側を封止するよう形成された樹脂(60)と、を備え、前記第1の突起部(12a)と前記第2の突起部(13a)の端面は、前記樹脂(60)の切断面と略同一面となるように、凹形状で側面に露出していることを特徴とする。
20:第1の連結絶縁材料
30:第2の連結絶縁材料
40:半導体素子
50:配線材料
60:封止樹脂
70:リードフレーム固定台
80:印刷用スクリーン
90:ペースト状の絶縁材料
100:スキージ
110,120:モールド金型、111:樹脂注入口
130:絶縁テープ
140:加圧ローラ
150:絶縁テープ
160:加圧ローラ
Claims (2)
- 裏面側に突出する第1の突起部(12a)がプレス成形された延長部(12)を有するダイアイランド部(11)と、該ダイアイランド部(11)の所定の辺に沿う方向に配列され裏面側に突出する第2の突起部(13a)がプレス成形された複数のリード部(13)と、前記延長部(12)および前記各リード部(13)と連続する枠部(14)と、前記延長部(12)、前記ダイアイランド部(11)、前記リード部(13)、および前記枠部(14)を区画する間隙部(15)の一部と、を1単位とし複数単位が連続する形状にリードフレーム(10)を加工する第1の工程と、
前記第1の突起部(12a)と前記第2の突起部(13a)が露出するよう前記リードフレーム(10)の裏面に連結絶縁材料(30)を配設する第2の工程と、
前記リードフレーム(10)の前記ダイアイランド部(11)に半導体素子(40)を搭載し、該半導体素子(40)の電極と前記リード部(13)とを配線材料(50)により接続する第3の工程と、
前記リードフレーム(10)の前記半導体素子(40)および前記配線材料(50)側を樹脂(60)で封止する第4の工程と、
前記樹脂(60)および前記リードフレーム(10)を前記第1の突起部(12a)と前記第2の突起部(13a)の切断面が前記樹脂(60)の切断面と略同一面となるように切断して、前記第1の突起部(12a)と前記第2の突起部(13a)の切断面が凹形状で露出するように前記単位毎に分離する第5の工程と、
を具備することを特徴とする半導体装置の製造方法。 - 裏面側に突出するようプレス成形された第1の突起部(12a)を延長部(12)に有するダイアイランド部(11)、該ダイアイランド部(11)の所定の辺に沿う方向に配列され、前記裏面側に突出するようプレス成形された第2の突起部(13a)を有する複数のリード部(13)からなるリードフレーム(10)と、
前記ダイアイランド部(11)に搭載された半導体素子(40)と、
前記半導体素子(40)と前記複数のリード部(13)とを接続する配線材料(50)と、
前記第1の突起部(12a)と前記第2の突起部(13a)が裏面に露出するように前記リードフレーム(10)の裏面に配設された連結絶縁材料(30)と、
前記リードフレーム(10)の前記半導体素子(40)および前記配線材料(50)側を封止するよう形成された樹脂(60)と、を備え、
前記第1の突起部(12a)と前記第2の突起部(13a)の端面は、前記樹脂(60)の切断面と略同一面となるように、凹形状で側面に露出していることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003271700A JP4050200B2 (ja) | 2003-07-08 | 2003-07-08 | 半導体装置の製造方法および半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003271700A JP4050200B2 (ja) | 2003-07-08 | 2003-07-08 | 半導体装置の製造方法および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005033043A JP2005033043A (ja) | 2005-02-03 |
JP4050200B2 true JP4050200B2 (ja) | 2008-02-20 |
Family
ID=34209480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003271700A Expired - Fee Related JP4050200B2 (ja) | 2003-07-08 | 2003-07-08 | 半導体装置の製造方法および半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4050200B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329358A (ja) * | 2006-06-08 | 2007-12-20 | Apic Yamada Corp | 半導体切断装置および半導体切断方法 |
JP2008258411A (ja) * | 2007-04-05 | 2008-10-23 | Rohm Co Ltd | 半導体装置および半導体装置の製造方法 |
TW200941684A (en) * | 2008-03-06 | 2009-10-01 | Mitsubishi Electric Corp | Leadframe board, semiconductor module, and method for making a leadframe board |
US20210296216A1 (en) * | 2020-03-17 | 2021-09-23 | Powertech Technology Inc. | Semiconductor device, lead frame, and method for manufacturing semiconductor device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3304705B2 (ja) * | 1995-09-19 | 2002-07-22 | セイコーエプソン株式会社 | チップキャリアの製造方法 |
JPH09321173A (ja) * | 1996-05-27 | 1997-12-12 | Shinko Electric Ind Co Ltd | 半導体装置用パッケージ及び半導体装置とそれらの製造方法 |
JP3072291B1 (ja) * | 1999-04-23 | 2000-07-31 | 松下電子工業株式会社 | リ―ドフレ―ムとそれを用いた樹脂封止型半導体装置およびその製造方法 |
JP2001326295A (ja) * | 2000-05-15 | 2001-11-22 | Rohm Co Ltd | 半導体装置および半導体装置製造用フレーム |
JP4189161B2 (ja) * | 2002-03-15 | 2008-12-03 | 新日本無線株式会社 | リードフレーム及び半導体装置並びにそれらの製造方法 |
-
2003
- 2003-07-08 JP JP2003271700A patent/JP4050200B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005033043A (ja) | 2005-02-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6861734B2 (en) | Resin-molded semiconductor device | |
KR100836303B1 (ko) | 반도체 소자 및 패키지와 그 제조방법 | |
KR100324333B1 (ko) | 적층형 패키지 및 그 제조 방법 | |
JP3793628B2 (ja) | 樹脂封止型半導体装置 | |
US9859197B2 (en) | Integrated circuit package fabrication | |
US8133759B2 (en) | Leadframe | |
US20050284658A1 (en) | Components with posts and pads | |
EP0751561A1 (en) | Semiconductor package manufacturing method and semiconductor package | |
JP2002076228A (ja) | 樹脂封止型半導体装置 | |
EP3440697B1 (en) | Flat no-leads package with improved contact leads | |
US6608369B2 (en) | Lead frame, semiconductor device and manufacturing method thereof, circuit board and electronic equipment | |
US6617200B2 (en) | System and method for fabricating a semiconductor device | |
KR20020070107A (ko) | 표면에 장착 가능한 칩형 반도체 장치 및 그 제조 방법 | |
JP4050200B2 (ja) | 半導体装置の製造方法および半導体装置 | |
CN101937850B (zh) | 封装制造方法和半导体装置 | |
JP4189161B2 (ja) | リードフレーム及び半導体装置並びにそれらの製造方法 | |
JP2001035961A (ja) | 半導体装置及びその製造方法 | |
US20030124775A1 (en) | Semiconductor device, semiconductor device manufacturing method, circuit board, and electronic device | |
KR100623606B1 (ko) | 비지에이형 반도체 장치의 제조방법, 비지에이형 반도체 장치용 티에이비 테이프, 및 비지에이형 반도체 장치 | |
JP4185665B2 (ja) | ウェーハレベルパッケージ | |
JP2005303107A (ja) | リードフレームおよび半導体装置並びにそれらの製造方法 | |
JPH1126648A (ja) | 半導体装置およびそのリードフレーム | |
JP4840305B2 (ja) | 半導体装置の製造方法 | |
JP2001077275A (ja) | リードフレームとそれを用いた樹脂封止型半導体装置の製造方法 | |
JP2503029B2 (ja) | 薄型構造の半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20060509 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20061109 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20070828 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20071023 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20071120 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20071128 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4050200 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101207 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111207 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111207 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121207 Year of fee payment: 5 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131207 Year of fee payment: 6 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |