KR101380681B1 - 클럭 정보를 포함하도록 인코딩된 신호를 통신하는 송수신기 - Google Patents

클럭 정보를 포함하도록 인코딩된 신호를 통신하는 송수신기 Download PDF

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KR101380681B1
KR101380681B1 KR1020120061479A KR20120061479A KR101380681B1 KR 101380681 B1 KR101380681 B1 KR 101380681B1 KR 1020120061479 A KR1020120061479 A KR 1020120061479A KR 20120061479 A KR20120061479 A KR 20120061479A KR 101380681 B1 KR101380681 B1 KR 101380681B1
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KR
South Korea
Prior art keywords
clock
sampling
timing
period
transmission data
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KR1020120061479A
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English (en)
Korean (ko)
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KR20120136308A (ko
Inventor
히데키 가시마
도모히사 기시가미
나오지 가네코
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가부시키가이샤 덴소
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Publication of KR20120136308A publication Critical patent/KR20120136308A/ko
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/403—Bus networks with centralised control, e.g. polling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0697—Synchronisation in a packet node
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4902—Pulse width modulation; Pulse position modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
KR1020120061479A 2011-06-08 2012-06-08 클럭 정보를 포함하도록 인코딩된 신호를 통신하는 송수신기 KR101380681B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2011-128222 2011-06-08
JP2011128222A JP5541234B2 (ja) 2011-06-08 2011-06-08 トランシーバ

Publications (2)

Publication Number Publication Date
KR20120136308A KR20120136308A (ko) 2012-12-18
KR101380681B1 true KR101380681B1 (ko) 2014-04-02

Family

ID=47220754

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120061479A KR101380681B1 (ko) 2011-06-08 2012-06-08 클럭 정보를 포함하도록 인코딩된 신호를 통신하는 송수신기

Country Status (5)

Country Link
US (1) US8848767B2 (ja)
JP (1) JP5541234B2 (ja)
KR (1) KR101380681B1 (ja)
CN (1) CN102820900B (ja)
DE (1) DE102012209636B4 (ja)

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JP5609930B2 (ja) 2012-07-31 2014-10-22 株式会社デンソー トランシーバ
WO2015068213A1 (ja) * 2013-11-05 2015-05-14 株式会社安川電機 モータ制御装置、モータ制御システム及びモータ制御方法
FR3023661B1 (fr) * 2014-07-11 2017-09-01 Somfy Sas Procede d'ajustement d'un signal de cadence d'un circuit d'emission/reception, dispositif de controle, systeme de controle, actionneur et unite de commande associes
DE102014110082B3 (de) * 2014-07-17 2015-10-15 Infineon Technologies Ag Empfänger, Verfahren zur Detektion eines Fehlers in einem Signal, welches einen Datenwert umfasst, Verfahren zur Übertragung eines Datenwerts und Verfahren zur Detektion eines Fehlers in einem Signal
JP6378966B2 (ja) * 2014-08-13 2018-08-22 ラピスセミコンダクタ株式会社 調歩同期式シリアルデータ取得装置及び調歩同期式シリアルデータ取得方法
DE102014116909B4 (de) * 2014-11-19 2016-07-28 Infineon Technologies Ag Empfänger, Sender, Verfahren zum Wiedergewinnen eines zusätzlichen Datenwerts aus einem Signal und Verfahren zum Übertragen eines Datenwerts und eines zusätzlichen Datenwerts in einem Signal
FR3029661B1 (fr) * 2014-12-04 2016-12-09 Stmicroelectronics Rousset Procedes de transmission et de reception d'un signal binaire sur un lien serie, en particulier pour la detection de la vitesse de transmission, et dispositifs correspondants
US10425268B2 (en) * 2015-06-23 2019-09-24 Microchip Technology Incorporated UART with line activity detector
US9628255B1 (en) * 2015-12-18 2017-04-18 Integrated Device Technology, Inc. Methods and apparatus for transmitting data over a clock signal
US9479182B1 (en) 2015-07-02 2016-10-25 Integrated Device Technology, Inc. Methods and apparatus for synchronizing operations using separate asynchronous signals
DE102016219663B4 (de) 2016-10-11 2018-08-02 Conti Temic Microelectronic Gmbh Verfahren zur Überwachung eines Netzwerks auf Anomalien
US10635619B2 (en) * 2016-10-12 2020-04-28 Cirrus Logic, Inc. Encoding for multi-device synchronization of devices
US10439639B2 (en) * 2016-12-28 2019-10-08 Intel Corporation Seemingly monolithic interface between separate integrated circuit die
CN108958092B (zh) * 2017-05-23 2022-11-04 佛山市顺德海尔电器有限公司 单片机时钟异常检测方法及装置、计算机可读存储介质、设备
DE102017214421A1 (de) * 2017-08-18 2019-02-21 Robert Bosch Gmbh Verfahren und Vorrichtung zur Synchronisation von Prozessen auf wenigstens zwei Prozessoren
US10447464B2 (en) * 2017-12-05 2019-10-15 Qualcomm Incorporated Super-speed UART with pre-frame bit-rate and independent variable upstream and downstream rates
CN110231783B (zh) * 2019-04-29 2020-10-27 东风商用车有限公司 一种总线式dcm休眠静态电流控制系统及控制方法
CN113242167B (zh) * 2021-04-12 2023-04-25 成都尼晟科技有限公司 一种基于单比特位同步的半异步can总线控制方法及控制器
US20240120908A1 (en) * 2022-10-11 2024-04-11 AyDeeKay LLC dba Indie Semiconductor Local Interconnected Network Bus Repeater Delay Compensation

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JP2002232404A (ja) 2001-02-02 2002-08-16 Nec Corp データ伝送システム及びデータ伝送方法
KR20080053171A (ko) * 2006-12-08 2008-06-12 한국전자통신연구원 클럭 위상 정렬 장치 및 그 방법
KR20090123933A (ko) * 2007-03-08 2009-12-02 샌디스크 아이엘 엘티디 바이어스 및 랜덤 지연 소거

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JPH0898284A (ja) * 1994-07-25 1996-04-12 Nippondenso Co Ltd データ受信装置，送信装置および通信装置
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JP2001077799A (ja) * 1999-07-08 2001-03-23 Denso Corp 非同期シリアル通信装置を有するマイクロコンピュータ装置
JP2002232404A (ja) 2001-02-02 2002-08-16 Nec Corp データ伝送システム及びデータ伝送方法
KR20080053171A (ko) * 2006-12-08 2008-06-12 한국전자통신연구원 클럭 위상 정렬 장치 및 그 방법
KR20090123933A (ko) * 2007-03-08 2009-12-02 샌디스크 아이엘 엘티디 바이어스 및 랜덤 지연 소거

Also Published As

Publication number Publication date
DE102012209636B4 (de) 2023-03-30
JP5541234B2 (ja) 2014-07-09
CN102820900A (zh) 2012-12-12
US20120314738A1 (en) 2012-12-13
US8848767B2 (en) 2014-09-30
DE102012209636A1 (de) 2012-12-13
KR20120136308A (ko) 2012-12-18
CN102820900B (zh) 2015-03-11
JP2012257035A (ja) 2012-12-27

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