KR101357068B1 - 비휘발성 메모리들에 대한 바디 효과 감지 방법 - Google Patents
비휘발성 메모리들에 대한 바디 효과 감지 방법 Download PDFInfo
- Publication number
- KR101357068B1 KR101357068B1 KR1020087015402A KR20087015402A KR101357068B1 KR 101357068 B1 KR101357068 B1 KR 101357068B1 KR 1020087015402 A KR1020087015402 A KR 1020087015402A KR 20087015402 A KR20087015402 A KR 20087015402A KR 101357068 B1 KR101357068 B1 KR 101357068B1
- Authority
- KR
- South Korea
- Prior art keywords
- state
- memory cells
- voltage
- bit line
- word line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/565—Multilevel memory comprising elements in triple well structure
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/321,996 US7349264B2 (en) | 2005-12-28 | 2005-12-28 | Alternate sensing techniques for non-volatile memories |
| US11/320,917 US7616481B2 (en) | 2005-12-28 | 2005-12-28 | Memories with alternate sensing techniques |
| US11/320,917 | 2005-12-28 | ||
| US11/321,996 | 2005-12-28 | ||
| PCT/US2006/062513 WO2007076451A2 (en) | 2005-12-28 | 2006-12-21 | Body effect sensing method for non-volatile memories |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20080096644A KR20080096644A (ko) | 2008-10-31 |
| KR101357068B1 true KR101357068B1 (ko) | 2014-02-03 |
Family
ID=38197637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020087015402A Expired - Fee Related KR101357068B1 (ko) | 2005-12-28 | 2006-12-21 | 비휘발성 메모리들에 대한 바디 효과 감지 방법 |
Country Status (5)
| Country | Link |
|---|---|
| EP (1) | EP1966800A2 (enExample) |
| JP (1) | JP4568365B2 (enExample) |
| KR (1) | KR101357068B1 (enExample) |
| TW (1) | TWI323464B (enExample) |
| WO (1) | WO2007076451A2 (enExample) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7616481B2 (en) | 2005-12-28 | 2009-11-10 | Sandisk Corporation | Memories with alternate sensing techniques |
| US7349264B2 (en) | 2005-12-28 | 2008-03-25 | Sandisk Corporation | Alternate sensing techniques for non-volatile memories |
| KR100923810B1 (ko) * | 2007-02-22 | 2009-10-27 | 주식회사 하이닉스반도체 | 메모리 소자와 그 동작 방법 |
| US8416624B2 (en) | 2010-05-21 | 2013-04-09 | SanDisk Technologies, Inc. | Erase and programming techniques to reduce the widening of state distributions in non-volatile memories |
| KR20150128823A (ko) * | 2013-03-14 | 2015-11-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 구동 방법 및 반도체 장치 |
| US11049557B2 (en) * | 2019-07-19 | 2021-06-29 | Macronix International Co., Ltd. | Leakage current compensation in crossbar array |
| KR102775482B1 (ko) * | 2021-01-19 | 2025-02-28 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | 반도체 메모리 디바이스 |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602789A (en) * | 1991-03-12 | 1997-02-11 | Kabushiki Kaisha Toshiba | Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08249893A (ja) * | 1995-03-07 | 1996-09-27 | Toshiba Corp | 半導体記憶装置 |
| KR0169267B1 (ko) * | 1993-09-21 | 1999-02-01 | 사토 후미오 | 불휘발성 반도체 기억장치 |
| JP3476952B2 (ja) * | 1994-03-15 | 2003-12-10 | 株式会社東芝 | 不揮発性半導体記憶装置 |
| JP2697665B2 (ja) * | 1995-03-31 | 1998-01-14 | 日本電気株式会社 | 半導体記憶装置及び半導体記憶装置からのデータ読み出し方法 |
| US5687114A (en) * | 1995-10-06 | 1997-11-11 | Agate Semiconductor, Inc. | Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
| JP4246831B2 (ja) * | 1999-02-08 | 2009-04-02 | 株式会社東芝 | 半導体集積回路装置のデータ判別方法 |
| US6259627B1 (en) * | 2000-01-27 | 2001-07-10 | Multi Level Memory Technology | Read and write operations using constant row line voltage and variable column line load |
| US7630237B2 (en) * | 2003-02-06 | 2009-12-08 | Sandisk Corporation | System and method for programming cells in non-volatile integrated memory devices |
-
2006
- 2006-12-21 WO PCT/US2006/062513 patent/WO2007076451A2/en not_active Ceased
- 2006-12-21 EP EP06848820A patent/EP1966800A2/en not_active Withdrawn
- 2006-12-21 KR KR1020087015402A patent/KR101357068B1/ko not_active Expired - Fee Related
- 2006-12-21 JP JP2008548823A patent/JP4568365B2/ja not_active Expired - Fee Related
- 2006-12-28 TW TW095149528A patent/TWI323464B/zh not_active IP Right Cessation
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5602789A (en) * | 1991-03-12 | 1997-02-11 | Kabushiki Kaisha Toshiba | Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1966800A2 (en) | 2008-09-10 |
| KR20080096644A (ko) | 2008-10-31 |
| TWI323464B (en) | 2010-04-11 |
| WO2007076451A3 (en) | 2007-09-20 |
| WO2007076451A2 (en) | 2007-07-05 |
| JP4568365B2 (ja) | 2010-10-27 |
| JP2009522706A (ja) | 2009-06-11 |
| TW200741718A (en) | 2007-11-01 |
Similar Documents
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| US7616481B2 (en) | Memories with alternate sensing techniques | |
| US7177184B2 (en) | Selective operation of a multi-state non-volatile memory system in a binary mode | |
| US6456528B1 (en) | Selective operation of a multi-state non-volatile memory system in a binary mode | |
| JP4510031B2 (ja) | 非揮発性メモリの雑/ファインプログラミングのための効率的ベリフィケーション | |
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| JP4726807B2 (ja) | 非揮発性メモリの雑/ファインプログラミングのための可変電流シンキング | |
| CN1701383B (zh) | 位线串扰误差得到减少的非易失性存储器及方法 | |
| US7920422B2 (en) | All-bit-line erase verify and soft program verify | |
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| CN101107671B (zh) | 存储器感测电路及用于低电压操作的方法 | |
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| KR101357068B1 (ko) | 비휘발성 메모리들에 대한 바디 효과 감지 방법 | |
| KR19990013057A (ko) | 단일 비트 데이터와 다중 비트 데이터를 동일한 칩에 선택적으로 저장하는 플래시 메모리 장치의 독출 및 기입 방법 | |
| JP2002367381A (ja) | 不揮発性半導体メモリ装置およびその書き込み方法 |
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