TW200741718A - Alternate sensing techniques for non-volatile memories - Google Patents
Alternate sensing techniques for non-volatile memoriesInfo
- Publication number
- TW200741718A TW200741718A TW095149528A TW95149528A TW200741718A TW 200741718 A TW200741718 A TW 200741718A TW 095149528 A TW095149528 A TW 095149528A TW 95149528 A TW95149528 A TW 95149528A TW 200741718 A TW200741718 A TW 200741718A
- Authority
- TW
- Taiwan
- Prior art keywords
- bit line
- cell
- voltage
- shut
- charge
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/564—Miscellaneous aspects
- G11C2211/565—Multilevel memory comprising elements in triple well structure
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Read Only Memory (AREA)
Abstract
The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/320,917 US7616481B2 (en) | 2005-12-28 | 2005-12-28 | Memories with alternate sensing techniques |
US11/321,996 US7349264B2 (en) | 2005-12-28 | 2005-12-28 | Alternate sensing techniques for non-volatile memories |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200741718A true TW200741718A (en) | 2007-11-01 |
TWI323464B TWI323464B (en) | 2010-04-11 |
Family
ID=38197637
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095149528A TWI323464B (en) | 2005-12-28 | 2006-12-28 | Alternate sensing techniques for non-volatile memories |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1966800A2 (en) |
JP (1) | JP4568365B2 (en) |
KR (1) | KR101357068B1 (en) |
TW (1) | TWI323464B (en) |
WO (1) | WO2007076451A2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7349264B2 (en) | 2005-12-28 | 2008-03-25 | Sandisk Corporation | Alternate sensing techniques for non-volatile memories |
US7616481B2 (en) | 2005-12-28 | 2009-11-10 | Sandisk Corporation | Memories with alternate sensing techniques |
KR100923810B1 (en) * | 2007-02-22 | 2009-10-27 | 주식회사 하이닉스반도체 | Memory device and method of operating the same |
US8416624B2 (en) | 2010-05-21 | 2013-04-09 | SanDisk Technologies, Inc. | Erase and programming techniques to reduce the widening of state distributions in non-volatile memories |
KR20150128823A (en) | 2013-03-14 | 2015-11-18 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Method for driving semiconductor device and semiconductor device |
US11049557B2 (en) * | 2019-07-19 | 2021-06-29 | Macronix International Co., Ltd. | Leakage current compensation in crossbar array |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08249893A (en) * | 1995-03-07 | 1996-09-27 | Toshiba Corp | Semiconductor memory |
US5602789A (en) * | 1991-03-12 | 1997-02-11 | Kabushiki Kaisha Toshiba | Electrically erasable and programmable non-volatile and multi-level memory systemn with write-verify controller |
KR0169267B1 (en) * | 1993-09-21 | 1999-02-01 | 사토 후미오 | Nonvolatile semiconductor memory device |
JP3476952B2 (en) * | 1994-03-15 | 2003-12-10 | 株式会社東芝 | Nonvolatile semiconductor memory device |
JP2697665B2 (en) * | 1995-03-31 | 1998-01-14 | 日本電気株式会社 | Semiconductor storage device and method of reading data from semiconductor storage device |
US5687114A (en) * | 1995-10-06 | 1997-11-11 | Agate Semiconductor, Inc. | Integrated circuit for storage and retrieval of multiple digital bits per nonvolatile memory cell |
JP4246831B2 (en) * | 1999-02-08 | 2009-04-02 | 株式会社東芝 | Data identification method for semiconductor integrated circuit device |
US6259627B1 (en) * | 2000-01-27 | 2001-07-10 | Multi Level Memory Technology | Read and write operations using constant row line voltage and variable column line load |
US7630237B2 (en) * | 2003-02-06 | 2009-12-08 | Sandisk Corporation | System and method for programming cells in non-volatile integrated memory devices |
-
2006
- 2006-12-21 EP EP06848820A patent/EP1966800A2/en not_active Withdrawn
- 2006-12-21 JP JP2008548823A patent/JP4568365B2/en not_active Expired - Fee Related
- 2006-12-21 KR KR1020087015402A patent/KR101357068B1/en active IP Right Grant
- 2006-12-21 WO PCT/US2006/062513 patent/WO2007076451A2/en active Application Filing
- 2006-12-28 TW TW095149528A patent/TWI323464B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JP4568365B2 (en) | 2010-10-27 |
KR101357068B1 (en) | 2014-02-03 |
JP2009522706A (en) | 2009-06-11 |
KR20080096644A (en) | 2008-10-31 |
WO2007076451A3 (en) | 2007-09-20 |
TWI323464B (en) | 2010-04-11 |
WO2007076451A2 (en) | 2007-07-05 |
EP1966800A2 (en) | 2008-09-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | Annulment or lapse of patent due to non-payment of fees |