KR20080096644A - Alternate sensing techniques for non-volatile memories - Google Patents

Abstract

The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing the cell bit line to charge up. The bit line of the memory cell will then charge up until the bit line voltage becomes sufficiently high to shut off any further cell conduction. The rise of the bit line voltage will occur at a rate and to a level dependent upon the data state of the cell, and the cell will then shut off when the bit line reaches a high enough level such that the body effect affected memory cell threshold is reached, at which point the current essentially shuts off. A particular embodiment performs multiple such sensing sub-operations, each with a different control gate voltage, but with multiple states being sensed in each operation by charging the previously discharged cells up through their source.

Description

Alternating current sensing technologies for nonvolatile memories {ALTERNATE SENSING TECHNIQUES FOR NON-VOLATILE MEMORIES}

The present invention generally relates to nonvolatile memories and the operation of the memories, and in particular to techniques for reading the memories.

The principles of the present invention have applications for various types of nonvolatile memories, and what is currently planned and planned to use the new technology has been developed. However, implementations of the present invention have been described with reference to flash electrically erasable and programmable read only memory (EEPROM), where the storage elements are illustratively floating gates.

Current commercial products in which each floating gate storage element of a flash EEPROM array stores a single bit of data by operating in binary mode are common, where the threshold levels of the two ranges of floating gate transistors are defined as storage levels. The threshold levels of the floating gate transistor correspond to the range of charge levels stored on the floating gates. In addition to reducing the size of memory arrays, there is a trend to further increase the data storage density of such memory arrays by storing one or more data bits in each floating gate transistor. This is accomplished by defining two or more threshold levels as storage states for each floating gate transistor, and four such states (two bits of data per floating gate storage element) are now included in commercial products. More storage states are considered, such as 8 or even 16 states per storage element. Each floating gate memory transistor has a specific total range (window) of threshold voltages that can actually be operated, the range being one range for the number of states plus the margins between states so that they are clearly distinguished from each other. Divided into.

As the number of states stored in each memory cell increases, the tolerance of any shifts in the programmed charge level on the floating gate storage elements decreases. As the number of states stored on each memory cell storage element increases, programming must be performed with an increased precision range and allowed because the charge ranges designed for each storage state are necessarily narrowed and placed more closely together. The magnitude of any post program shifts in the stored charge levels that can be reduced, in case of actual or apparent shifts. The actual shifts of charge stored in one cell will read, program, and erase the same column or row, and other cells with some degree of electrical coupling with the cell, such as sharing a line or node. When it can be confusing.

Apparent shifts of stored charge occur due to field coupling between storage elements. This degree of coupling necessarily increases due to the reduction in the size of the memory cell arrays and the improvement of integrated circuit fabrication techniques. The problem occurs most remarkably between two adjacent sets of cells that have been programmed at different times. One set of cells is programmed to add one charge level to floating gates corresponding to a set of data. After the second set of cells is programmed with the second set of data, the charge levels read from the floating gates of the first set of cells are charged on the second set of floating gates in combination with the first set of floating gates. The effect is different from that programmed. This is described in US Pat. Nos. 5,867,429 and 5,930,167, which are incorporated herein by reference in their entirety. These patents consider the effect of charge on the second set of floating gates when physically insulating the two sets of floating gates or reading the first set of floating gates. In addition, patent 5,930,167 describes methods for selectively programming portions of a multi-state memory, such as cache memory, only two states or reduced margins, in order to shorten the time required to initially program the data. This data is later read and in two or more states, or reprogrammed into memory with increased margin.

This effect is provided for various types of flash EEPROM cell arrays. A NOR array of one design has memory cells connected between control gates connected to adjacent bit (column) lines and word (row) lines. The individual cells comprise one floating gate transistor with or without a select transistor formed in series, or two floating gate transistors separated by a single select transistor. Examples of such arrays and use in storage systems are given in the following US patents and pending applications of SanDisk Corporation, which is hereby incorporated by reference in its entirety: Patent Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332 , 5,712,180, 5,890,192 and 6,151,248 and serial numbers 09 / 505,555 filed February 17, 2000 and 09 / 667,344 filed September 22, 2000.

A NAND array of one design has multiple memories, such as 8, 16 or even 32, connected in series along each string formed between one bit line and one reference potential line through select transistors at either end. Have cells. Word lines are connected to the control gates of the cells and are formed on other series strings. Relevant examples and operation of the arrays are provided in U.S. Patents incorporated herein by reference in their entirety as references 5,570,315, 5,774,397 and 6,046,935. In summary, two bits of data from different logical pages of incoming data program the cell in one state according to the first one bit of data, and then if data is needed, according to the second bits of incoming data. It is programmed to one of four states of individual cells in two steps of reprogramming the cell to another of the states.

In addition to improving memory performance by programming faster, performance can be improved by accelerating the sensing process. Shortening the sensing times will improve performance during read and verify operations; And if the memory can accelerate the verification, this will improve the write speed. This is especially true in multi-state memories, where the verify step is required between any two consecutive pulses, and the multi-state memories require several sensing steps in each verify operation. The performance of nonvolatile memory systems can be improved if these disadvantages can be reduced or eliminated.

In summary, the present invention provides a method of sensing memory cells that are particularly useful for improving performance in multilevel nonvolatile memory systems. This sets the initial state of the selected memory cells by discharging the channels to ground, placing a voltage level on a conventional source (such as a common electrode that connects the same ends of the NAND strings together in one block) and a control gate, This is accomplished by charging the cell bit line for some time as a result of the conduction of current through the cell during the signal integration period. The bit line of the memory cell will then be charged until the bit line voltage is large enough to block any additional cell conduction. The rise in the bit line voltage occurs at any speed and level depending on the data state of the cell, and then the cell is forced to reach the body effect of the source to the NAND string to be affected by the memory cell threshold at which the current is essentially blocked. It will shut off when the performing bit line voltage reaches a sufficiently high level. More particularly, the exemplary embodiment uses this technique for sensing in verify steps for write operations and read operations. A plurality of cells along the same word line are sensed simultaneously by placing a constant, data independent voltage on the word line and placing a constant, data independent common voltage level of these cells on the source side. The source side serves as a drain on the side where the voltage is higher than the bit line side. The bit lines of previously discharged cells will cause a voltage on each bit line that points to the respective data content.

In a sub aspect of the present invention, the present invention allows a single pass of verify operation to verify the state of all cells to be programmed regardless of the cell target state. The level at which the corresponding bit line will rise will depend on the state of the cell due to the body effect. This level can be compared with a reference value corresponding to each target value. This improves performance over the prior art, which requires multiple charge-discharge, signal integration cycles after each program pulse, and one cycle for each target state requires a verify operation.

In another sub aspect of the present invention, read performance is improved because all data levels can be determined based on a single discharge-charge cycle. When the levels on the given cells bit line reach an asymptotic value determined by the data content, if these levels reach a level on the bit line that can be compared with a set of reference levels, the comparing step It is performed sequentially or simultaneously.

In a further sub aspect of the present invention, and in a set of embodiments, the peripheral circuit supplies the reference voltages sequentially to the bit line comparators. The reference values may be used simultaneously in a multiplexing circuit that supplies other values, or the line supplying the reference values to the comparator itself receives various reference values in a multiplexed manner. Although this recent technology requires a change in the voltage level on the reference supply line, this can be affected faster than recharging and discharging the bit lines at each data level.

Another aspect of the present invention performs multi-sense sub-operations for states of multi-state memory cells each having a different control gate voltage by charging cells previously discharged through the source, but having multiple states sensed in each operation. By sensing. By combining elements of the two various sensing techniques, the sensing operation is accelerated when multiple states are read in each sense sub-operation, and the use of multiple word line voltages provides sufficient dynamic range to solve all data states.

Particular embodiments of these aspects are based on flash memory with a NAND architecture. Cells along the selected word line are connected to the common source line along the bit lines. Any or all of the bit line architectures can be used when the bit lines are divided into alternatingly sensed sets.

Additional aspects, features, advantages and applications of the present invention are included in the following description of exemplary embodiments, which description should be taken in conjunction with the accompanying drawings.

1 is a block diagram of a nonvolatile memory system in which various aspects of practicing the invention are described.

FIG. 2 shows a conventional circuit and configuration of the memory array of FIG. 1 when the memory cell array is of NAND type.

3 illustrates a stage along a column of a NAND type memory array formed on a semiconductor substrate.

4 is a cross-sectional view of the memory array of FIG. 3 taken in section 4-4.

5 is a cross-sectional view of the memory array of FIG. 3 taken in section 5-5.

FIG. 6 provides Table 1 of exemplary operating voltages of the NAND memory cell array of FIGS. 2-5.

FIG. 7 illustrates other features of the NAND memory cell arrays of FIGS. 2-5.

8 shows an example of the current distribution of threshold voltages of the NAND memory cell array of FIGS. 2-5 when operated in four states.

9A and 9B illustrate exemplary program voltage signals that may be used in the memory cell arrays of FIGS. 2-5.

10 illustrates a dynamic sensing technique based on discharging selected memory elements.

11 illustrates a sensing technique in accordance with an exemplary embodiment of the present invention.

12 illustrates a portion of a memory array and peripheral circuits in accordance with the present invention.

13A-C show a variation on the peripheral circuit of FIG. 12.

14 illustrates a hybrid sensing technique in accordance with an exemplary embodiment of the present invention.

Nonvolatile Memory System Example

1-7, certain nonvolatile memory systems are described in which various aspects of the invention are practiced to provide obvious embodiments. 1 is a block diagram of a flash memory system. The memory cell array 1 comprising a plurality of memory cells M arranged in a matrix comprises a column control circuit 2, a row control circuit 3, a c-source control circuit 4 and a cp-well control circuit ( Is controlled by 5). The column control circuit 2 reads the data stored in the memory cells M, determines the state of the memory cells M during the program operation, and the potential of the bit lines BL to advance the programming or suppress the programming. The bit lines BL of the memory cell array 1 are connected to control the levels. The row control circuit 3 selects one of the word lines WL, applies read voltages, applies program voltages coupled with bit line potential levels controlled by the column control circuit 2, and stores the memory. The cells M are connected to the word lines WL to apply an erase voltage coupled with the voltage of the p-type region (“cp-well” 11 in FIG. 3) where the cells M are formed. The c source control circuit 4 controls the common source line (“c-source” in FIG. 2) connected to the memory cells M. FIG. The c-p-well control circuit 5 controls the c-p-well voltage.

Data stored in the memory cells M is read by the column control circuit 2 and output to the external I / O lines through the I / O line and the data input / output buffer 6. The program data to be stored in the memory cells is input to the data input / output buffer 6 via external I / O lines and transferred to the column control circuit 2. External I / O lines are connected to the controller 20.

Command data for controlling the flash memory device is input to a command interface connected to external control lines connected to the controller 20. The command data informs the flash memory of what operation is required. The input command is a state machine 8 which controls the column control circuit 2, row control circuit 3, c-source control circuit 4, cp-well control circuit 5 and data input / output buffer 6; Is delivered). The state machine 8 may output state data in flash memory such as READY / BUSY or PASS / FAIL.

The controller 20 may or may be connected to a host system such as a personal computer, a digital camera, or a personal digital assistant. It is the host that initiates instructions such as storing or reading data to or from the memory array 1 and provides or receives such data. The controller converts these commands into command signals that can be interpreted and executed by the command circuits 7. The controller also typically includes a buffer memory for user data written to or read from the memory array. A typical memory system includes one integrated circuit chip 21 including a controller 20 and one or more integrated circuit chips 22 each including a memory array and associated control, input / output and state machine circuits. . Of course, the trend is to integrate the controller circuits of a memory array and a system together on one or more integrated circuit chips. The memory system can be embedded as part of the host system or included in a memory card that can be removably inserted into a mating socket of the host systems. Such a card may comprise the entire memory system or the controller and memory array with associated peripheral circuits may be provided as separate cards.

2, an exemplary structure of the memory cell array 1 is described. A flash EEPROM of the NAND type is described by way of example. Memory cells M are divided into 1,024 blocks in a particular embodiment. Data stored in each block is erased at the same time. Thus, a block is the smallest unit of multiple cells that can be erased simultaneously. In each block, in this embodiment, there are 8,512 columns that are divided into even columns and odd columns. The bit lines are divided into even bit lines BLe and odd bit lines BLO. Four memory cells connected to word lines WL0 and WL3 at each gate electrode are connected in series to form a NAND cell unit or a NAND string. One terminal of the NAND cell unit is connected to the corresponding bit line BL through a first select transistor coupled with a gate electrode to the first select gate line SGD, and the other terminal has a gate electrode connected to the second select gate line ( Is connected to the c-source via a second select transistor coupled to SGS). Although four floating gate transistors are shown included in each cell unit for simplicity, a larger number of transistors such as 8, 16, 32 or even 64 are used.

During the user data read and programming operation, 4,256 cells M are simultaneously selected in this embodiment. The selected cells M have the same word line WL, for example WL2, and the same kind of bit line BL, for example even bit lines BLe0, BLe2 to BLe4254. Therefore, 532 bytes of data can be read or programmed simultaneously and this data unit is called a page. In this embodiment, one block can store at least eight pages because each NAND string contains four cells and there are two bit lines per sense amplifier. When each memory cell M stores two data bits, that is, when storing a multi-level cell, one block stores 16 pages. In this embodiment, the storage element of each of the memory cells, in this case the floating gate of each of the memory cells, stores two bits of user data.

FIG. 3 shows a cross-sectional view of a NAND cell unit of the type shown schematically in FIG. 2 in the direction of the bit line BL. At the surface of the p-type semiconductor substrate 9, a p-type region cp-well 11 is formed, and the cp-well is surrounded by the n-type region 10 to electrically insulate the cp-well from the p-type substrate. All. The n-type region 10 is connected to a c-p-well line made of the first metal M0 through the conductor filling the first contact hole CB and the n-type diffusion layer 12. The p type region c-p-well 11 is connected to the c-p-well line through the first contact portion CB and the p type diffusion layer 13. The c-p-well line is connected to the c-p-well control circuit 5 (FIG. 1).

Each memory cell has a floating gate (FG) for storing an amount of charge corresponding to data stored in the cell, a word line (WL) for forming a gate electrode, and a drain and source electrodes consisting of an n-type diffusion layer (12). Floating gate FG is formed on the surface of the c-p-well through tunnel oxide film 14. The word line WL is stacked on the floating gate FG through the insulator film 15. The source electrode is connected to the common source line (c-source) made of the first metal M0 through the second selection transistor S and the first contact hole CB. The common source line is connected to the c-source control circuit 4. The drain electrode is formed of the bit line BL, the first contact hole CB, the first metal M0 and the second contact hole V1 made of the second metal M1 through the first selection transistor S. It is connected to an intermediate wiring board. The bit line is connected to the column control circuit 2.

4 and 5 show cross-sectional views of the memory cell (section 4-4 of FIG. 3) and the selection transistor (section 5-5 of FIG. 3), respectively, in the direction of the word line WL2. Each column is formed in a substrate and insulated from neighboring columns by a trench filled with an insulating material known as shallow trench isolation (STI). The floating gates FG are insulated from each other by the STI and insulator film 15 and the word line WL. The spacing between the floating gates FG may be about 0.1 μm, and capacitive coupling between the floating gates may be important. Since the gate electrode SG of the select transistor is formed in the same forming processes as the floating gate FG and the word line WL, the stacked gate structure is shown. These two layers forming the select gate lines SG are subjected to one contact for each select gate since the poly-1 layer in the STI embodiment is etched into insulated strips during the STI definition. And shorted together electrically. When the word lines are etched, the poly 1 strips are etched away, leaving poly 1 gates remaining on the select gate channels as insulated conductors. However, the poly 2 layer will form a conductive line and connect the individual poly 1 select gates to each other to form select gate lines extending in a direction parallel with the word lines.

Table I of FIG. 6 summarizes the voltages applied to operate the memory cell array 1 having one of states “11”, “10”, “01”, “00”, and in a particular embodiment, respectively, The floating gate of the memory cell of stores two bits. This table shows the case where the word line "WL2" and the bit lines "BLe" are selected for reading and programming. By raising the c-p-well to an erase voltage of 20V and grounding the word lines WL of the selected block, the data of the selected block is erased. Since all word lines WL, bit lines BL, select lines SG, and c-source of unselected blocks are in a floating state, they are intermediate voltages due to cp-well and capacitive coupling. , For example to 8V. Therefore, a strong electric field is applied only to the tunnel oxide films 14 (FIGS. 4 and 5) of the selected memory cells M, and the data of the selected memory cells are erased when the tunnel current flows across the tunnel oxide film 14. do. The erased cell is one of four possible states, i.e., "11" in this embodiment.

In order to store the electrons in the floating gate FG during the programming operation, the selected word line WL2 is connected to the program pulse Vpgm and the selected bit lines BLe are grounded. On the other hand, in order to suppress the programming on the memory cells M in which no programming has occurred, the corresponding bit lines BLe are connected to a positive voltage Vdd at the start of programming, for example, to isolate the string channels. For example, it is connected to 3V and floats up to the above suppression conditions. This program suppression is performed on all of the unselected bit lines BLo. The unselected word lines WL0, WL1, and WL3 are connected to 10V, the first select gate SGD is connected to Vdd, and the second select gate SGS is grounded. As a result, the channel potential of the programmed memory cell M is set to 0V. The channel potential of the suppressed cell is raised to about 8V as a result of the channel potential being pulled up by the capacitive coupling with the word lines WL. As described above, a strong electric field is applied only to the tunnel oxide films 14 of the memory cells M during programming, the tunnel current flows across the tunnel oxide film 14 in the reverse direction compared to the erase, and the logic state is Is changed from "11" to one of the other states "10", "01", or "00". Various other coding methods are chosen to represent these states such that the names E (erasure), A (lowest threshold program state), B (higher threshold value than A), and C (highest threshold program state) are used for later discussion. Can be.

In read and verify operations, select gates SGD and SGS and unselected word lines WL0, WL1 and WL3 are 4.5 to ensure that current between the bit line and the common source line can be passed. It rises to the read pass voltage of V. The selected word line WL2 is connected to one voltage, the level of which is specified for read and verify operations, respectively, to determine if the threshold voltage of the associated memory cell has reached this level. For example, in READ 10 operation (state A), the selected word line WL2 is grounded to detect whether the threshold voltage is higher than 0V. In the case of such a read, it can be said that the read level is 0V. In VERIFY01 operation (state C), the selected word line WL2 is connected to 2.4V to verify that the threshold voltage has reached 2.4V. For this verification, it can be said that the verification level is 2.4V.

The selected bit lines BLe are precharged to a high level, for example 0.7V. If the threshold voltage is higher than the read or verify level, the potential level of the associated bit line BLe remains high due to the non-conductive memory cell M. On the other hand, if the threshold voltage is lower than the read or verify level, the potential level of the associated bit line BLe decreases to a lower level, for example 0.5 V or less, because of the conductive memory cells M. . Other details of read and verify operations are described below.

FIG. 7 shows a part of the column control circuit 2 of FIG. 1. Each pair of bit lines BLe and BLo is coupled to a data storage portion 16 that includes two data storage DS1 and DS2 registers, each of which may store one bit of data. The data storage portion 16 senses the potential level of the selected bit line BL during a read or verify operation, stores the data in a binary manner, and controls the bit line voltage during program operation. The data storage portion 16 is selectively connected to the selected bit line BL by selecting one of the signals of "EVENBL" and "ODDBL". The data storage portion 16 is also coupled to the I / O line to output read data and to store program data. The I / O line is connected to the data input / output buffer 6 as described above in connection with FIG.

Save Element  Memory system operation with more than 2 states per state

FIG. 8 shows threshold voltage distributions for the memory cell array 1 when each floating gate storage element stores two bits of data, ie four data states, in each memory cell M. FIG. Curve 33 shows the distribution of threshold levels V _T of cells in array 1 that are in an erased state (E data state), which are negative threshold voltage levels. Threshold voltage distributions 34 and 35 of memory cells storing A and B user data are shown as being between V _VA and V _{VB and} between V _VB and V _VC , respectively. Curve 36 shows the distribution of cells programmed to the C data state, which is the highest threshold voltage level setting above 2V and below 4.5V of the read pass voltage.

In this embodiment, each two bits stored in a single memory cell M are from a different logical page. That is, each bit of the two bits stored in each memory cell has a different logical page address than the other. The lower page bits shown in FIG. 8 are accessed when an even page address (= 0, 2, 4, ..., N / 2) is input, where N is the logical page capacity of the memory. The upper page bits are accessed when an odd page address (= 1, 3, 5, ..., [N / 2] + 1) is input. Using the example coding shown in FIG. 8, state E is represented as an "11" state, state A is represented as a "10" state, state B is represented as a "00" state, and , State C is represented as the " 01 " state, where the first binary digit represents a value stored in the upper page and the second binary digit represents a value stored in the lower page. Note that even and odd page addresses should not be confused with even and odd bit lines.

In order to provide improved reliability, it is preferable that the individual distributions become strict (narrowed critical distributions), because a stricter distribution produces a wider read margin (distance between them). In accordance with the present invention, the distribution width remains more stringent without significant quality degradation of the programming speed.

According to the article "Fast and Accurate Programming Method for Multi-level NAND EEPROMs", Digest of 1995 Symposium on VLSI Technology, pp129-130, incorporated herein by reference, limiting the distribution to 0.2V width is a common use for repetitive programming pulses. Requires 0.2V increase between steps. 9A shows a conventional programming pulse technique. The programming voltage Vpgm waveform is shown. The programming voltage Vpgm is divided into many pulses and increased by 0.2V with a pulse by pulse. The starting level of Vpgm is 12V in this particular embodiment.

In the periods between the pulses, verify (read) operations are performed. That is, the programmed level of each cell programmed in parallel is read between each programming pulse to determine whether it is equal to or higher than the programmed verify level. This is shown in Figure 9B, which is a more detailed version of Figure 9A for a memory that stores four bits per cell. If it is determined that the threshold voltage of a given memory cell exceeds the verify level, programming is stopped or suppressed for the bit by raising the voltage of the bit line to which the series cell unit of the given cell is connected from 0V to Vdd. Programming of other of the cells programmed in parallel on the same page continues until the cells reach verify levels. When the threshold voltage moves below the verify level and above the verify level during the cell's last programming pulse, the shift of the threshold voltage is equal to the Vpgm step size of 0.2V. Therefore, the threshold voltages are controlled within 0.2V width.

One particular existing technique for programming four state NAND memory cells in an array of the type described above is now described. Upon passing the first programming, the threshold level of the cell is set according to the bit from the lower logical page. If the bit is "1", nothing is done because it stays in that state due to the previous erase. However, if the bit is "0", the cell's level is increased to A programmed state 34 using V _VA as a verify voltage to inhibit further programming. This completes the first programming pass.

Upon passing the second programming, the threshold level of the cell is set according to the bits stored in the cell from the upper logical page. If "1", programming does not occur because the cell is in one of states 33 or 34 according to the programming of the lower page bits, all of which have an upper page bit of "1". However, if the upper page bit is "0", the cell is programmed at the second time. The first pass is a cell if it remains in the erased or E state 33, the cell is programmed in the highest threshold state 36 (state C) from the state as shown by the upper arrow in Fig. 8 V _VC Is used as a verification condition to suppress further programming. If the cell has been programmed to state 34 (state A), as a result of the first programming pass, the cell is in that state using V _VB as the verify condition as shown by the lower arrow of FIG. (State B) is further programmed into the second pass. The result of the second pass is to program the cell to the specified state to store "0" from the upper page without changing the logic value written during the first pass programming. During the second programming cycle, the cell's threshold distribution remains in state (E or A) or shifts to state (B or C). Because there are two different target threshold states occurring in different cells at the same time during the same programming cycle, two different verify levels V _VB and V _VC must be checked after each programming pulse. In some systems V _VC may only be checked during subsequent voltage pulses to accelerate the total program cycle.

Of course, if the memory is operated in four or more states, there will be multiple distributions within the defined voltage threshold window of the memory cells equal to the number of states. In addition, although specific bit patterns have been assigned to respective distributions, other bit patterns may be assigned, in which case the states between which programming takes place may differ from those described above. Some of the above variants are discussed in the patterns previously referenced in the background for NAND systems. In addition, other types of memory arrays operating in multiple states and techniques for reducing the results of adjacent cell combining in NAND are described in US Pat. No. 6,522,580, incorporated herein by reference in its entirety.

Nearly intermediate voltages V _RA , V _RB and V _RC between adjacent portions of distributions 33-36 are used to read data from the memory cell array. There are threshold voltages to which the threshold voltage states of each cell read are compared. This is accomplished by comparing the reference currents or voltages with the current or voltage measured from the cell, respectively. Margins exist between these read voltages and the programmed threshold voltage distributions, so that the distributions from confusion or the like as described above, unless the distributions overlap any read voltages V _RA , V _RB and V _RC . Some spreads of the are allowed. However, as the number of storage state distributions increases, this margin is reduced and programming is preferably performed more precisely to prevent this spread.

The previous description assumes that there are two logical pages in one physical page and that only the lower logical page or upper logical page is programmed for a given programming cycle. U.S. Patent Application Publication 2003/0112663, incorporated herein by reference, entitled "Method and System for Programming and Inhibiting Multi-Level Non-Volatile Memory Cells" refers to programming all of the physical states of a page during one programming operation. Describe. For four states per cell as shown in FIG. 8, all cells to be programmed to any program states A, B, or C are first programmed to state A as previously described. After all cells to be programmed to any of these states have been verified to have reached state A and the data for upper states B and C are already present in the data latches DS1 and DS2 of FIG. 7. Because of this, the programming cycle can continue without interruption or reloading of new data, and the cells to be programmed in states B and C can continue to be programmed in state B. Once all cells have reached this level, only those cells needed for C can remain in this state. As described in the patent application, upon transition from programming from state (A) to state (B) and similarly at programming transition from state (B) to state (C) than others ("slow bits") It is observed that some fast bits ("fast bits") program and actually some reduction in wordline voltage is desirable.

Although specific programming methods have been described, there are other possibilities that can be used. For example, US Pat. No. 6,046,935 describes programming methods in which selected cells are programmed from state E to state B during a first programming cycle. Cells are programmed from state (E) to state (A) to state (C) during the second programming cycle. US Pat. No. 6,657,891 teaches this method by teaching that the initial distribution of state B extends to the lower threshold limit and even overlaps with the final state A at the end of the first programming cycle, which becomes strict with the distribution only during the second programming cycle. Explain. In addition, the binary coding used to represent the states E, A, B and C may be chosen differently than shown in FIG. Both patents 6,046,935 and 6,657,891 are incorporated herein by reference.

Alternating  Verification and Reading Techniques

As noted in the background, it is desirable to improve the performance of multi-state nonvolatile memories. This section deals with improving the sensing operations as occurring during the read operations and the verify phase of the program operation. As described above with respect to FIG. 9B, each program pulse is followed by a verify operation of (N-1), each of which applies a different value of control gate voltage to the selected word line, where N is in the MLC embodiment. The number of states. For example, in four storage states per cell, corresponding to two bits per cell, three verify read operations are typically followed by every program pulse. Each of these verify operations typically takes place at successively higher read voltages applied to the selected word line. Although the following techniques can all be executed in binary memories, the advantages are most fully realized in multi-state applications.

Upon sensing the nonvolatile memory cell, there will typically be several steps as part of the read operation of the program operation or as part of the verify step. These include applying voltages to the cell such that they are properly biased to the correct initial conditions for the data content to be sensed or measured following an integration period measuring parameters related to the state of the cell. In an EEPROM cell, the parameter is typically a voltage or source-drain current, but can also be a time or frequency managed by the state of the cell. One exemplary embodiment for the sense voltages of this measurement process is shown schematically in FIG. 10.

FIG. 10 illustrates a voltage level on a bit line of a memory array, which is one of the bit lines shown in FIG. 2. The first step sets the gate voltages of the cells. In the second step, the bit lines of the cells to be read are charged to a predetermined level. The integration time is the third step starting at time t = 0 when the bit line discharges through the cell and the voltage level decays at an arbitrary rate depending on the state of the cell. After time t = t ', the voltage level on the bit line is measured in relation to the reference level V _ref . If the voltage is at or above V _ref as in line 501, the cell is considered to be off. If the voltage is below V _ref as in line 503, the cell is considered to be on, and consequently the voltage on the control gate is greater than the threshold voltage of the cell. This technique, along with other techniques for reading memory cells, is further described in US Pat. Nos. 6,222,762, 6,538,922 and 6,747,892, all of which are incorporated and incorporated by reference in these applications.

The use of sensing techniques requires a balance in the selection of t 'and the reference voltage V _ref , and V _ref is used to sense the state of the cell: if t' is chosen too short, 501 and 503 are not sufficiently separated. If t 'is selected too long, 503 and 501 reach ground; Similarly, if V _ref is too high, it may be misread as on due to low level leakage currents even in the off cell, and if V _ref is chosen too low, because on cells can deliver a finite amount of current even in the on cell It may be misread as off. (The question to be determined is whether the applied control gate voltage V _CG is higher or lower than the cell threshold, since it is not known before the measurement is made, there is no V _CG in the range of previous, too high or too low values; ie It is not wrong to _grant other V _CG values, but it is wrong to choose an inappropriate t 'or V _ref ). This problem is exacerbated in multi-state memories where closely placed levels must be distinguished. As a result, this is typically done by precharging and discharging (and corresponding V _ref ) for each state or target value.

As shown in Fig. 9B, during a multi-state programming operation, this reading process needs to be performed to verify the state of the memory cell for each target state. In order to increase the write performance by slightly reducing the number of verify operations following each program pulse, during the first few programming pulses the verify operations applying higher control gate voltages are skipped and lower during the last few program pulses. Verification operations that apply control gate voltages may also be skipped. These skips track the track of the highest programmed and lowest programmed cell in each write block at any given time during a programming operation, when the distribution of VT steps into each of the higher voltage program pulses applied to the selected control gate. By doing so, it can be done more intelligently, safely and more efficiently. For example, the verify operation for state 3 may be skipped as long as the cell has not yet been verified while reaching state 2. This "smart verification" technique is described in US Patent Publication 2004-0109362-A1, incorporated by reference and published on June 10, 2004. Although previous verification operations have described previous improvements and how to be more efficient, they still require multiple verify operations between pulses. The inventive concept of the present invention improves this situation.

When applied to the write process, the principles aspect of the present invention replaces (N-1) (or somewhat fewer) verify operations per program pulse with only a single verify operation. This applies a single fixed, high value read voltage (e.g., 2.4V, a typical word line voltage for discriminating between the highest programmed threshold state and other lower programmed states) to the selected word line, This is accomplished by verifying each cell against its target state by taking advantage of the body effect in the following way: For example, a voltage of 2V is applied to a typical source line of the NAND array (Figure 2) and the SGS transistors It is turned on to deliver this voltage to the conventional source sides of the NAND strings in the selected block. Typical drains (ie, bit lines) are discharged to ground before the start of the signal integration period by grounding the bit lines and applying a sufficiently high voltage to the SGDs to ensure that all the bit lines are precharged. The cells that initially conduct during the integration period experience a rise in each bit line voltage until each cell reaches a threshold voltage and blocks further charging of each bit line, after which the bit line voltage is substantially random. There will be no further rise. It is important that the bit lines serve as a source for the memory cell, and as such, the threshold voltage of each memory cell will be a function of the source voltage through the body effect. This is schematically shown in FIG.

FIG. 11 shows the voltage V _WL supplied by the word line to the control gates of the cells in the selected row (FIG. 11A), where the voltage is supplied to the common source line of the selected cells (FIG. 11B), and 3 of these Shows the voltage levels for the bit line (FIG. 11C) in response to a sensing operation, with reference levels (FIG. 11D) for when the dog is fed sequentially to the reference voltage input side of the sense amplifiers via a single reference voltage carrying bus line. do. 11A-C show the voltages at the control gate V _WL , the source V _source , and the drain V _BL of the selected storage elements, respectively. Various details of NAND array operations that may be incorporated in example embodiments may be found in the following US patents and patent publications, all of which are incorporated herein by reference: 6,373,746, 5,570,315; 5,652,719; 5,521,865; 5,870,334; 5,949,714; 6,134,140; 6,208,560; 6,434,055; 6,549,464; 6,798,698; 20050013169; 5,969,985; 6,044,013; 6,282,117; 6,363,010; And 6,545,909.

In addition to the control gate, source and drain voltages for the selected element, other voltages required on the NAND string in the NAND embodiment will need to be set: the other storage elements in the string will need to be turned fully, and the drain side select gate (SGD) will need to be turned on at the latest by the start of the precharge (or more precisely pre-discharge) phase, and the source side select gate SGS will need to be turned on at least until time t = 0. The relative values for these other voltages after t = 0 are schematically shown by the dotted lines on FIG. 11A. V _SGS , V _SGD and V _READ correspond to the source side select gate voltage, the drain side select gate voltage, and the voltage applied to unselected word lines in the block during a read operation, respectively. For example, V _SGS and V _SGD may be at 5V to ensure that these transistors are on despite the body effect, V _WL is 3.5V (or whatever the highest V _TH comparison voltage is), and v _read can be higher than V _WL . V _READ is higher than typical 5V (eg 7V) and potentially the highest program state such that all other cells along the NAND strings are “on” despite the body effect rising thresholds. (These values before t = 0 were discussed as some options but not explicitly shown.) These values will in particular be discussed further below.

Figure 11 begins in the initial state, step 1, depending on what the process has been going on before. V _BL is shown as having some initial value and all others are shown as low, but this is an arbitrary starting point. Step (2) is a precharge (more precisely pre-discharge) step in which the bit line is grounded to set an initial condition in preparation for the sensing process of step (3) starting at t = 0. In the NAND array, the drain side select transistor SGD is turned on and charge flows out and is maintained through the process, and the bit line is charged again in steps 3 and 4. Before time t = 0, the source line is charged so that when the cell is turned on, current can flow to charge the bit line depending on the state of the cell. At time t = 0 the word line voltage V _WL is raised, so that the bit lines are charged in step (3). The bit lines held to ground before t = 0 during step (3) are separated from the ground and floated, and the charge is charged to a higher voltage in accordance with the cell current.

As shown in Fig. 11C, once the word line is taken high at t = 0, the bit lines start to charge. When the same V _WL is applied to all cells along the word line, all cells of the read set (or read page) are charged. As a result, this is described in many of the NAND references described above, US patent application Ser. No. 10 / 751,097, filed Dec. 31, 2003, all of which are even or odd bit lines of the architecture type, incorporated herein by reference, or 2002. All bit lines, or ABL type architecture, of all bit lines described in US patent application Ser. No. 10 / 254,483, filed September 24, and incorporated herein by reference. In another embodiment, both source voltage V _CS and word line voltage V _WL can be raised before t = 0, and one of the select lines is used to turn on the process at t = 0.

If the same V _WL is applied to all cells, the bit line of a given cell will be charged towards the asymmetric voltage value based on the data state stored on the cell at any rate due to the body effect. This is shown for four state cells along the time axis of FIG. 11C during step (3). When these bit line voltages begin to separate, other data states can be distinguished. At some time t 'the V _BL values can be compared with reference values. Although reading immediately after t = 0 can reduce the reading time, it causes more inaccuracy than when the values still rise; As a result, it is desirable to improve accuracy by waiting for values to begin to flatten at or near asymmetric values. Although this may be somewhat later than just starting reading, it is still faster than the discharge method described above with reference to FIG. 10 only when a single bit line charge process is needed to read all data states. Unlike the dynamic readout type based on the cell discharge rate, in the process of FIG. 11 all states can be sensed simultaneously when the bit line values flatten to different values depending on the state of the cell being measured. In contrast, the dynamic sensing of FIG. 10 needs to proceed through a complete charge-discharge cycle at different comparison points.

At t = t ', the level on each bit line can be compared with multiple reference values simultaneously or sequentially during the read process of step 4. 12 schematically illustrates an array portion and peripheral circuitry for one embodiment.

12 shows a portion of two blocks of an array in every bit line (ABL) array. As shown, block i is a common source line for block i, c-source_i 111 is on top of block i higher than select gate line SGS_i and in turn on memory cells. On the side in which it is flipped with respect to block i + 1, block i + 1 is arranged with the common source line, c-source_i + 1, at the bottom. In this case, the memory cells are read along the word line WL1_i 109. In this case, the voltage V _WL of FIG. 11A is applied to WL1_i 109 and the voltage of FIG. 11B is applied to c-source_i 111, and the unselected word lines and select gates on the source and drain sides are at least late. Turn on at t = 0. In this and the following figures, sense amplifier circuits are all shown on the top side of the array for simplicity of representation. In practice, the circuit for alternating bit lines may be placed on the bottom side of the array as described in US patent application Ser. No. 11 / 078,173, filed March 11, 2005, which is incorporated herein by reference. .

All NAND strings in the selected read page are the same V _source applied when they are at the rest of the voltages associated with the selected NAND block (unselected word lines and select gates). And the same V _WI : the other is the charge stored on the floating gates of the cells of the selected row that determines how fast and how far the voltage level on the corresponding bit line will rise, which is the other lines of FIG. 11C. Corresponds to. For example, in cell 113 on bit line j, this would control the level on bit line BLj 107 and then the corresponding comparator 101j in accordance with global bit line GBLj 105. Is communicated with). The comparison values are supplied to the comparators along line (or lines) 103. While these other comparison values are supplied to the line (s) 103 at previous times and stabilized, the comparison operation can be performed during step 4 after time t 'as shown in FIG. 11D. As described later in connection with FIG. 13, line 103 may be a single line with other comparison values V _comp supplied later or separate lines for various comparison values and multiplexed to the comparators. In another variation, the level of each global bit line can be supplied to multiple comparators for comparing with other V _comp values in parallel.

The advantage of sensing all levels simultaneously includes the performance gains due to the parallelization of the comparison operations. However, sensing all levels simultaneously involves the area side penalty and the complexity of the sense amplifiers, where each sense amplifier includes (N-1) comparators. In addition, (N-1) bus lines will be required to carry the (N-1) reference voltages required to simultaneously sense N states and to discriminate from one another. Alternatively, if the compare operations are performed sequentially, the sense amplifiers can be designed to be simpler and occupy smaller portions of the die. In a typical ABL architecture, it should be noted that all global bit lines have dedicated sense amplifiers, and in more typical odd / even detection, one amplifier is dedicated to all global bit line pairs. Another advantage of performing the comparison step in a sequential manner is that a single bus line extending in the same direction as the word lines is used to deliver the reference voltages in a time multiplexed manner to all sense amplifiers remaining at the ends of each memory plane. Can be. This saves die area. However, there will be some performance and power / energy penalties associated with charging reference bus line voltage (N-1) times. It is also possible to design the memory to time multiplex comparison operations to use several reference voltage bus lines. For example, an eight state memory (N = 8) can have four bus lines, sense amplifiers can be designed to sense two states at the same time using two of the reference bus lines at the same time and the other two reference bus lines Combinations that are charged with a pair of reference voltages to reduce the performance impact of the charge time of the reference bus line are also possible. It is important to note that the bit line charge or discharge step is a relatively slow process that takes several microseconds. This time is represented by the equation I = C dV / dt, where I is a current that may not be greater than the saturation current of the memory cell transistor (for an on cell, typically the value for I is on the order of micro amps or less). Is the bit line capacitance typically managed by the global bit line capacitance, and dV is the minimum change in sense node voltage required for reliability and noiseless operation, which is in the range [50 mV, 500 mV]. United States Patent Publications US-2005-0169082-A1 and 2004-0057318-A1, incorporated herein by reference, describe the use of sense nodes other than global bit lines in, for example, ABL architectures; As a result, this kind of arrangement allows for faster sensing since the sensing node's capacitance is significantly less than the global bit line capacitance. The comparison operation of comparing the reference voltage with the sense node voltage is a very fast operation that takes several nanoseconds or tens of nanoseconds. These example numbers are increased by proceeding from using (N-1) sequential sensing operations to using a single sensing operation that can use (N-1) sequential comparison operations.

The above discussion can be found primarily in the case of four state memory cells, each storing two bits of data. However, when more states are stored in each cell, it is not possible to distinguish all states by using a single word line voltage. Even when it is possible to determine all possible data states, it may be desirable to break the process into one or more reads if there are three, four, or more such states. For example, distinguishing all states at once may require bias conditions that result in a higher number of read disturbs. In order to be able to read multiple data states by using the same word line voltage and varying the amount of body effect delivered from the bit lines, the VREAD voltage applied to the non-selected word lines of the NAND block is a typical read of NAND memories. It will be overdriven to a higher amount than necessary for. The higher VREAD value should be selected so that it can be read with a positive source bias to turn on the memory cells that were programmed to the highest threshold voltage and further raise the high threshold values. As a result, higher VREAD values may be needed. These high VREAD values make the chaos readable. To alleviate this problem, read scrubbing (as described in US Pat. No. 5,532,962, incorporated herein by reference) is a frequency that ensures that the block does not experience sufficient read confusion exposure before data is rewritten. It can be performed in. This rewriting of data is performed by moving the data to another block as performed in wasteful leveling schemes (US Pat. No. 6,230,233, Publication No. US-2004-0083335-A1, and Application No. 10 / 990,189). And 10 / 281,739, all of which are incorporated herein by reference). It is also possible to design a hybrid sensing method wherein (N-1) sensing operations are performed in M (M <N) sequential sensing operations, each M operations requiring discharging / charging of sensing nodes. This hybrid method can be used to alleviate problems that may arise from the lack of dynamic range availability at allowed source / drain voltages, where the magnitude of the body effect, together with confusion and reliability issues, can be reduced to a single or more verify operation. N-1) may require analysis of a single test for comparisons. Although this hybrid sensing method requires combining two apparently opposite methods (using multiple word line read voltages, it also senses multiple states at once by charging the cells through the sources), which is related to FIG. It may be very desirable for multi-state applications as described below.

The following set of example values will help explain the new read method: External instruments using DC biases of 0 V on the source and 0.5 V on the drain can measure the threshold voltage of the memory cell. The sweep of the control gate voltage will result in a drain-to-source current, a drain-to-source-current vs. control-gate-voltage characteristic. Appropriate current values, such as 100 nA, may be selected to define the threshold voltage of the cell. Cells that are erased and subsequently soft programmed in state E will have negative thresholds in the range -1.5V to -0.5V, in state A the cells will have V _thS in the range 0.3V to 0.9V, and in state B The cells will have a VT in the range 1.5V to 2.1V, and in state C the cells will have a V _th s in the range of 2.7V to 3.3V as measured by this static method. Real memory chips typically use dynamic sensing, which precharges the bit lines (drains) before the start of integration and includes some amount of discharge of the bit lines during the integration period indicating whether the sensed cell is on or off. . The parameters of dynamic sensing may be selected such that V _th measured by the dynamic sensing type described above with respect to FIG. 10 is equal to or close to V _th of the cell measured by the static method.

Providing the above distribution of threshold values, a typical read operation for four state memories using the dynamic sensing method described above with respect to FIG. 10 is 3 with the following control gate voltages: 0V, 1.2V and 2.4V, respectively. It consists of pre-charging and integration sequences. Due to OV on the control gate, the ON result of the sensing operation indicates that the state of the cell is E, and the OFF result indicates that the state of the cell is A, B or C. Due to 1.2V on the control gate, the ON result of the sensing operation will indicate that the cell is in state E or A, while the OFF result will indicate that the cell is in state B or C. Due to 2.4V on the control gate, the ON result of the sensing operation will indicate that the state of the cell is E, A, or B, and the OFF result will indicate that the state of the cell is C. The combination result of these three sense operations sequence constitutes a read operation on the four state memory indicating the state of each cell.

During DC sensing and due to a source voltage of 0V and a drain voltage of 0.5V, the threshold voltage of the cell may be 1V. The same cell with exactly the same amount of charge on the floating gate has a body effect shift VT of 2.0V if the source voltage is increased by 0.5V and the drain voltage is increased by 1.0V and maintains the same value of drain to source voltage. (In this discussion, the source body effect factor of 2 was estimated; for other factors, the values should be adjusted accordingly.). In other words, a 0.5V increase in body bias may correspond to 1.0V of cell V _th . Again, all these numerical values are exemplary only. The conventional dynamic sensing described in connection with FIG. 10 precharges a bit line to a high precharge value of, for example, 1.0V, and then reduces or discharges the bit line to a value of, for example, 0.4V for an ON cell. For the OFF cell, let's drop it slightly to 0.9V, for example. At the end of the sense integration period, the bit line voltage is compared with a reference value of 0.65V, for example, to determine whether the corresponding cell is ON or OFF. In typical dynamic sensing, unselected word lines in a NAND block must be driven with a sufficiently high V _READ value of 5.0 V, for example, to ensure that cells on unselected word lines do not interfere with the discharge of the bit line current. .

In a new sensing method that uses the body effect to raise the VT of the sensed cells, the overdrive requirement is also increased and requires V _READ which can exceed 7.5V. This high V _READ value does not pose a problem during program / verify operations when the exposure to this V _READ value is one exposure per block write operation. However, the read operation may be performed multiple times, exposing memory cells to read confusions aggravated by higher V _READ values that may cause excessive tunneling of charge to floating gates after multiple read operations. Read scrubbing techniques as described in US Pat. No. 5,532,962 can be used to treat these read disturb issues. Care should be taken to design the read operations to simulate the verify operation as closely as possible in most implementations. This is done to increase read fidelity. Therefore, one preferred embodiment includes using a body bias single read operation during read operations as well as during program / verify operations.

During programming operations, the same latches that have stored states to be programmed in the corresponding cells can be accessed to select the appropriate level of sense trip point required to verify the target state on the bit line on a bit line basis. For example, if a cell is programmed to state A, the reference trip point voltage for that cell is 1.5V (using example values from above), while programming to state B is 1.0 Requires a trip point voltage of V, and programming to state C requires a trip point voltage of 0.5V. In one embodiment shown in Fig. 13A, three bus lines 103a-c each carrying one of these voltages can be designed to extend in the same direction as the word lines, each bit Line comparator 101 uses one of these three reference voltages via MUX 121 with select signals 103d derived from latches holding target state data corresponding to each cell / bit line. Let's do it.

In another embodiment shown in FIG. 13B, one bus line 103 carries all three voltages sequentially, and the latch data of each bit line has a reference voltage of 0.5V, 1.0V or 1.5V. When applied to 103, it will determine if a valid comparison is made at one time. (There is no latch data available during read operations, so all three values will need to be compared). In another embodiment (FIG. 13C), three comparators 101a-c exist on each bit line (ABL architecture assumption) or on each pair of bit lines (more conventional NAND architecture assumption) and the bit line voltage is It is compared simultaneously with three reference voltages. This requires the cost of the additional circuitry required to have three comparators. Alternatively, the single comparator of FIG. 13B can perform three comparisons in sequence, providing a more compact design. The time penalty of this and other previously discussed sequential operations can be achieved through properly designed bus lines with small RC delays, where each comparison can be achieved with a few tens of nanosecond problems, and the time taken to change the reference bus line voltages is small. It can be very small because it can be small. In all these sequential embodiments, the mutual state sensing delays are not indicated by the RC time constants of the array or by the time required for precharging or sensing. This is in contrast to the mutual state sensing delays of the prior art embodiments where the recharge-discharge process takes an appropriately long time.

As noted above for cells storing many states, the dynamic range sufficient for the allowed source / drain voltages to allow all states to be determined for a single sense operation due to the magnitude of the body effect with confusion and reliability issues. There can be. For example, consider the case in which the memory cells store 8 states, or 3 bits, per memory cell in the process of FIG. For the illustrated V _WL values, the illustrated states of 11c may be only 0, 1, 2 and 3 states, and V _WL is too large to turn on the cells at higher states 4, 5, 6 and 7. Low; Or if V _WL is high enough to turn on the cells in these higher states, then all states 0, 1, 2, and 3 may reach the top in the upper curve.

In order to overcome this dynamic range defect, in another aspect, the present invention uses a hybrid sensing technique. In these embodiments, the multiple V _WL values are used according to the method described with respect to FIG. 11 with the cells being discharged, but charged through the source, and then multiple states are sensed. For each V _WL value, the total subset of multiple states is sensed so that when individual sensing of sub-operations is completed, sensing is completed for all of the states. As a result, all these subsets are typically separate and differ in at least some elements, although the subsets may have some states in common. Although greater efficiency arises from non-overlapping subsets, it may be easier to allow some overlap and ensure that no states are missed in some implementations for additional accuracy. Additionally, there may be cases where the highest or lowest subsets are completely contained within the larger and adjacent subsets.

It is noted that the hybrid method combines two somewhat opposite techniques: the technique of FIG. 11 eliminates the need to switch word line voltages for read, and all states (in FIG. 11) with the complexity of multiple read voltages. For 4 states). In contrast, the more common multiple word line voltage method can eliminate more involved switching operation of the source and drain polarities to assign the general task to the source and drain sides of the memory cell and promise body effects. Combining both methods may seem like an overly complex detection method at first. However, consideration of the allowed VREAD voltages indicated by the read confusion relations has led to the hybrid method of 1) having a high threshold window capable of supporting multi-state memory, and 2) reducing read confusion to manage manageable levels. VREAD sufficiently low, and 3) the body effect can form the best arbitration between the performance gain obtained by the application of multiple source-side voltages, which raises the threshold voltages and allows simultaneous verification operations of multiple data states.

14 is arranged similarly to FIG. This shows processing for three bits per cell system that reads four states in the first sense sub operation and four other states in the second sense operation. In this embodiment, the same set of comparison values is used for both subsets of states, although more generally a separate set of comparison values can be used for each sub-operation. As before, the process can be used for data reading and program verification where only the target state needs to be checked for which of the two sub-operations has occurred since the target data can be known at the time of the program operation.

Referring to FIG. 14 in more detail, before time t ₀ , the situation is similar to FIG. 11, in which the bit lines are discharged, the source line is charged, and other transistors of the NAND string are brought to this, for example, V _SGD on. And to keep V _SGS (or V _WL or both) low. Once these initial conditions are set between t ₀ and t ₁ , the source and drain select transistors are turned on, the non-selected transistors in the NAND string are turned on, and the word line is at a first value V _WL1 . This allows the bit lines (or sense nodes) to charge at various levels depending on the data state of the cell. V _WL1 is high enough so that states 0, 1, 2 and 3 can be separated, but not so high that the 0 and 1 states reach the top and cannot be determined. In this embodiment, V _WL1 leaves the higher states 4, 5, 6 and 7 unresolved.

Once these states stabilize, the sense node voltage varies between t ₁ and t ₂ as described above with respect to FIG. 11, although four values in this case are used instead of 3 and corresponding changes need to be made in FIGS. 13A-C. Can be compared with comparison values. This allows the determination of whether each cell will have data content corresponding to these substates. Here, sensing for four states is performed continuously, although one or more comparisons can be made simultaneously (as with changes to four comparison points), as one or more comparisons are made above with respect to FIG. 13.

Once the first sense sub-operation is performed at t ₂ , the word line voltage is raised to V _WL2 to distinguish between the states analyzed at V _WL1 > V _WL2 . (Where, the word line voltage is increased from one sense operation to the next, although other embodiments may use V _WL1 > V _WL2 ). Between t ₂ and t ₃ , the level on the bit lines transitions from the responses to V _WL1 to the response to V _WL2 .

In the embodiment shown in FIG. 14, the bit lines are not discharged between sense sub-operations. In other embodiments, the bit lines may be discharged between t ₂ and t ₃ , for example to stabilize the precharge level on the source side. This can be done in various ways such as grounding the selected word line voltage, grounding V _SGS (without lowering or lowering V _WL2 ), or blocking the source voltage with the drain side open to discharge cells on the selected word line. Can be done with. A preferred embodiment to achieve this will follow the specifications of a particular memory based on factors such as the relative speed and power consumption needed to raise and lower levels on these other lines. After recharging, the bit lines are charged again in response to V _WL2 . The word bit line may be replaced above by the sense node to cover the case where the sense node is not a bit line as in the ABL architecture.

In some embodiments, at time t ₃ , the new word line voltage V _WL2 will analyze some states that have not been analyzed for V _WL1 . In this embodiment, the bias conditions using V _WL2 will separate states 4, 5, 6 and 7 even though lower states (determined between t ₂ and t ₂ ) are now incorporated into state 4. Can be. Once the bit line levels are sufficiently stable at t ₃ , the second sense sub operation is performed. Here, this is done in the same manner and value as for V _WL2 , although other values and techniques could be used in both cases. For example, two reads with two word line values are sufficient to cover all cells. In other cases, the process may continue with third or more additional sensing sub operations if it is necessary to clearly analyze all the conditions.

The various alternating sensing techniques described in this section are particularly desirable when used in connection with a programming method of writing multiple states simultaneously. The method allows simultaneous programming of multiple states by proportionally delaying the program of cells with low target threshold voltage levels. This target state dependent delay of programming is achieved by creating half-inhibit or semi-boosting conditions of varying strengths depending on the target state. The resulting efficiencies can greatly improve memory performance by combining these concurrent programming of all or at least multiple states with these verify / read methods. This simultaneous programming is based on the program rate on the bit line in bit lines based on the program voltage of different cells according to the target state (described in US Pat. No. 6,738,289, incorporated herein by reference) or the target state of each memory cell. You can do Such bit line data dependent programming is described in US patent application Ser. No. 11 / 196,547, incorporated herein by reference, wherein the voltage bias level, amount of current allowed to flow, or both are independent of each cell based on the corresponding target state. Managed. For any of these methods, the number of programming pulses is reduced; As the sensing techniques described above reduce the number of verify reads required between each such pulse, the efficiencies combine to increase memory performance.

Dielectric storage Of elements  Other use

The above embodiments have been described in the context of a cell type using conductive floating gates as charge storage elements. However, various aspects of the present invention include nanocrystalline memories, and phase change memories, MRAM, FERAM, and various other memory technologies described in US patent application 10 / 841,379, filed May 7, 2004, incorporated herein by reference. Can be used in connection with these. For example, the invention may also be practiced in systems that use a charge trapping dielectric as storage elements in individual memory cells instead of floating gates. The dielectric storage element is sandwiched between the conductive control gate and the substrate in the channel region of the cell. Although the dielectric can be separated into individual elements with the same sizes and positions as the floating gates, this is generally not necessary because the charge is trapped locally by this dielectric. The charge trapping dielectric may extend over the entire array except for regions occupied by select transistors or the like.

Dielectric storage element memory cells are generally described in the following technical papers and patents incorporated herein by reference in their entirety: Chan et al., "A True Single-Transistor Oxide-Nitride-Oxide EEPROM Device," IEEE Electron Device Letters, Vol. EDL-8, no. 3, March 1987, pp. 93-95; Nozaki et al., "A 1-Mb EEPROM with MONOS Memory Cell for Semiconductor Disk Application," IEEE Journal of Solid State Circuits, Vol. 26, No. 4, April 1991, pp. 497-501; Eitan et al., "NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell," IEEE Electron Device Letters, Vol. 21, No. 11, November 2000, pp. 543-545, and US Pat. No. 5,851,881.

There are certain charge trapping dielectric materials and configurations that are practical for use. One is a three layer dielectric with a silicon dioxide initially grown on a substrate, a silicon nitride layer deposited thereon and another layer of silicon oxide ("ONO") grown and / or deposited on the silicon nitride layer. Another is a single layer of rich silicon dioxide sandwiched between the gate and the semiconductor substrate surface. Such later materials are described in the following two articles, which are hereby incorporated by reference in their entirety: DiMaria et al., "Electrically-alterable read-only-memory using Si-rich SIO ₂ injectors and a floating polycrystalline silicon storage layer," J. Appl. Phys. 52 (7), July 1981, pp. 4825-4842; Hori et al., "A MOSFET with Si-implanted Gate-SiO ₂ Insulator for Nonvolatile Memory Applications," IEDM 92, April 1992, pp. 469-472. Dielectric storage elements are further discussed in US patent application US 10 / 280,352, filed Oct. 25, 2002, which is incorporated herein by reference.

Although the invention has been described in terms of specific embodiments and variations thereof, it is understood that the invention is protected within the full scope of the appended claims.

Claims (42)

A method of operating an array of memory cells connected along word lines and bit lines, the method comprising: Selecting a multistate memory cell for sensing operation; Discharging the sense node of the selected memory cell to ground through the connected bit line; After discharging the sensing node of the selected memory cell, Applying a first voltage level to a source of the selected memory cell, and Applying a second voltage level to a word line to which the selected memory cell is connected, the first and second voltage levels being independent of the data content stored in the selected cell; After applying the first and second voltage levels, causing a corresponding voltage to develop on the bit line to which the selected memory cell is connected; Comparing the voltage developed at the sense node of the selected memory cell against a first plurality of reference values to determine if the data content of the selected memory cell corresponds to one of the first subset of the multiple states; Performing a sensing operation; After performing the first sensing operation, applying a third voltage level to a word line to which the selected memory cell is connected, wherein the second and third voltage levels are different; After applying the third voltage level, causing the selected memory cell to develop a corresponding voltage on the connected bit line; And Comparing the voltage developed at the sense node of the selected memory cell against a second plurality of reference values to determine if the data content of the selected memory cell corresponds to one of the second subset of the multiple states; Performing a sensing operation, wherein the first and second subsets of the multiple states are separate and each comprise a plurality of states. 2. The method of claim 1 wherein the first and second plurality of reference values are the same. 2. The method of claim 1 wherein the first and second subsets of the multiple states are not overlapped. 2. The method of claim 1 wherein the combination of the first and second subsets of the multiple states comprises less than both of the multiple states. 2. The method of claim 1, further comprising discharging the sense node of the selected memory cell to ground via the connected bit line after the first sense operation and before the second sense operation. 2. The method of claim 1 wherein the sense node corresponds to a bit line to which a selected memory cell is connected. 2. The method of claim 1 wherein the sense node is an intermediate node for the bit line to which the selected memory cell is connected. 2. The method of claim 1 wherein the selected memory cell is one of a plurality of memory cells selected for simultaneous sensing operation. 10. The method of claim 8, wherein the plurality of memory cells selected for simultaneous sensing operation are formed along the word line. The method of claim 1 wherein the array has a NAND architecture. 11. The method of claim 10, wherein said array has an all bit line architecture. 2. The method of claim 1, wherein said sensing operations are performed during a verify phase of a write operation. 2. The method of claim 1 wherein the sensing operations are performed during a read operation. The method of claim 1, wherein the voltage developed along the bit line in the first and second sensing operations are sequentially compared with at least some of the first and second plurality of reference values, respectively. The method of claim 1, wherein the voltage developed along the bit line in the first and second sensing operations are simultaneously compared to at least some of the first and second plurality of reference values, respectively. A method for simultaneously determining the state of multiple multi-state memory cells from a memory array, the method comprising: The plurality of memory cells are connected along a common word line, have sources connected to a common source line, are formed along separate bit lines, and the method includes: Discharging the memory cells to ground via corresponding bit lines; Subsequently applying a first voltage level to the common source line; Subsequently applying a second voltage level to the word line; In response to applying a second voltage level to a word line, determining whether each data content of memory cells corresponds to one of the first subset of multiple states; Later applying a third voltage level to the word line, the third voltage level being different from the second voltage level; And In response to applying a third voltage level to the word line, determining whether the data content of each of the memory cells corresponds to one of the second subset of the multiple states, wherein the first and second of the multiple states are present. Wherein the subsets are separate and each include a plurality of states, wherein the states of the plurality of multi-state memory cells are simultaneously determined. 17. The method of claim 16, wherein determining whether data content of each of the memory cells corresponds to one of the first or second subset of the multistates, Developing a voltage at each of the corresponding bit lines; And Comparing the voltages deployed along the bit lines against a plurality of reference values to determine the data content of the memory cells. 17. The method of claim 16, wherein the first and second subsets of the multiple states are not overlapped. 17. The method of claim 16, wherein the combination of the first and second subsets of the multi-states comprises less than all of the multi-states. 17. The method of claim 16, wherein the array has a NAND architecture. 21. The method of claim 20, wherein the array has all bit line architectures. 17. The method of claim 16, wherein determining whether each data content of the memory cells corresponds to one of the first subset and determining whether each data content of the memory cells corresponds to one of the second subset is a write operation. And simultaneously determining the state of the plurality of multi-state memory cells. 17. The method of claim 16, wherein determining whether each data content of the memory cells corresponds to one of the first subset and determining whether each data content of the memory cells corresponds to one of the second subset is a read operation. And simultaneously determine the state of multiple multi-state memory cells. A method of simultaneously writing multistate data into a plurality of multistate memory cells from a memory array, the method comprising: The plurality of memory cells are connected along a common word line, have sources connected to a common source line, are formed along separate bit lines, and the method includes: Applying a common programming pulse to a word line while controlling the amount of charge injected into each of the memory cells on a bit line basis on a bit line based on a corresponding target state of each of the memory cells; Performing a later verification operation, wherein performing the verification operation comprises: Discharging memory cells to ground via corresponding bit lines; Subsequently applying a first voltage level to the common source line; Subsequently applying a second voltage level to the word line; In response to applying a second voltage level to a word line, determining whether the data content of each of the memory cells corresponds to one of the first subset of the multiple states; Later applying a third voltage level to the word line, the third voltage level being different from the second voltage level; And In response to applying a third voltage level to a word line, determining whether the data content of each of the memory cells corresponds to one of the second subset of the multiple states; And wherein the second subsets are separate and each include a plurality of states, respectively. 25. The method of claim 24, wherein determining whether each data content of memory cells corresponds to one of the first or second subset of the multiple states, Causing a voltage to develop in each of the corresponding bit lines; And Comparing the voltage developed along the bit lines against a plurality of reference values to determine the data content of the memory cells. 25. The method of claim 24, wherein controlling the amount of charge injected into each of the memory cells on a bit line in units of bit lines based on the corresponding target state of each of the memory cells is based on the corresponding target state of each of the memory cells. And setting a voltage level on the bit lines in units of bit lines. 25. The method of claim 24, wherein controlling the amount of charge injected into each of the memory cells on a bit line in units of bit lines based on the corresponding target state of each of the memory cells is based on the corresponding target state of each of the memory cells. And setting a current limit on the bit lines on a per bit line basis. Non-volatile memory, An array of memory cells connected along word lines and bit lines; And A read circuit, wherein the read circuit includes: A precharge circuit capable of connecting to a source of one or more selected memory cells; A word line driving circuit capable of connecting selected memory cells to a word line to which a plurality of sense voltages can be applied; And And sensing circuitry capable of connecting to corresponding one or more sensing nodes of the one or more selected memory cells, whereby the corresponding sensing nodes of the selected memory cells in the pre-charging phase can be discharged to ground, and the multiple sensing in the sensing mode. The voltage developed at the corresponding sense nodes of the selected memory cells in response to the voltages may be compared with a plurality of reference values to determine if the data content of the selected memory cell corresponds to one of the subset of the multiple states, and The subset is one or more multiple states. 29. The nonvolatile memory as in claim 28, wherein the same plurality of reference values are used for one or more of a plurality of sense voltages. 29. The nonvolatile memory as in claim 28, wherein the sense nodes correspond to bit lines to which corresponding selected memory cells are connected. 29. The non- volatile memory as in claim 28, wherein the sense nodes correspond to intermediate nodes for bit lines to which corresponding selected memory cells are connected. 29. The nonvolatile memory as in claim 28, wherein the one or more selected memory cells are a plurality of memory cells selected for simultaneous sensing operation. 33. The nonvolatile memory as in claim 32, wherein the plurality of memory cells selected for simultaneous sensing operation are formed along the word line. 29. The nonvolatile memory as in claim 28, wherein the array has a NAND architecture. 35. The nonvolatile memory as in claim 34, wherein the array has an all bit line architecture. 29. The nonvolatile memory as in claim 28, wherein the read circuit is used during the verify phase of write operations. 29. The nonvolatile memory as in claim 28, wherein the read circuit is used during data read operations. 29. The non- volatile memory as in claim 28, wherein the sense circuitry sequentially compares the voltage developed at sense nodes in sense mode against at least some of a plurality of reference values. 29. The non- volatile memory as in claim 28, wherein the sense circuit simultaneously compares the voltage developed at sense nodes in a sense mode against at least some of a plurality of reference values. The method of claim 28, Further comprising a write circuit, wherein the write circuit, A word line driver circuit capable of connecting selected memory cells to a word line to which a programming pulse can be applied; And A bit line level control circuit capable of connecting selected memory cells to corresponding bit lines connected to control the amount of charge injected into corresponding memory cells on a bit line on a bit line basis based on a corresponding target state of each of the corresponding memory cells; Including, non-volatile memory. 41. The nonvolatile memory as in claim 40, wherein the bit line level control circuit comprises a data dependent biasing circuit for corresponding bit lines to which selected memory cells are connected. 41. The nonvolatile memory as in claim 40, wherein the bit line level comprises a data dependent current limiting circuit for corresponding bit lines to which selected memory cells are connected.

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