KR101344577B1 - 집적 회로 테스트를 위한 저전력 및 영역 효율적인 스캔 셀 - Google Patents

집적 회로 테스트를 위한 저전력 및 영역 효율적인 스캔 셀 Download PDF

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Publication number
KR101344577B1
KR101344577B1 KR1020110132930A KR20110132930A KR101344577B1 KR 101344577 B1 KR101344577 B1 KR 101344577B1 KR 1020110132930 A KR1020110132930 A KR 1020110132930A KR 20110132930 A KR20110132930 A KR 20110132930A KR 101344577 B1 KR101344577 B1 KR 101344577B1
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South Korea
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scan
output
cell
input
functional data
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KR20120108910A (ko
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라메쉬 씨 테쿠말라
프리예쉬 쿠마르
프라카쉬 크리쉬나무어시
파라그 마다니
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엘에스아이 코포레이션
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Assigned to 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 reassignment 아바고 테크놀로지스 제너럴 아이피 (싱가포르) 피티이 리미티드 권리의 전부이전등록 Assignors: 엘에스아이 코포레이션
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
KR1020110132930A 2011-03-25 2011-12-12 집적 회로 테스트를 위한 저전력 및 영역 효율적인 스캔 셀 Expired - Fee Related KR101344577B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161467411P 2011-03-25 2011-03-25
US61/467,411 2011-03-25
US13/216,336 2011-08-24
US13/216,336 US8566658B2 (en) 2011-03-25 2011-08-24 Low-power and area-efficient scan cell for integrated circuit testing

Publications (2)

Publication Number Publication Date
KR20120108910A KR20120108910A (ko) 2012-10-05
KR101344577B1 true KR101344577B1 (ko) 2013-12-26

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KR1020110132930A Expired - Fee Related KR101344577B1 (ko) 2011-03-25 2011-12-12 집적 회로 테스트를 위한 저전력 및 영역 효율적인 스캔 셀

Country Status (6)

Country Link
US (1) US8566658B2 (https=)
EP (1) EP2503347B9 (https=)
JP (1) JP2012202991A (https=)
KR (1) KR101344577B1 (https=)
CN (1) CN102692599A (https=)
TW (1) TWI428620B (https=)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8890563B2 (en) * 2008-05-07 2014-11-18 Mentor Graphics Corporation Scan cell use with reduced power consumption
US9903916B2 (en) 2012-09-27 2018-02-27 Nxp Usa, Inc. Scan test system with a test interface having a clock control unit for stretching a power shift cycle
KR102010454B1 (ko) * 2012-12-26 2019-08-13 삼성전자주식회사 스캔 플립-플롭, 이의 동작 방법, 및 이를 포함하는 데이터 처리 장치
US9395414B2 (en) 2012-12-28 2016-07-19 Nvidia Corporation System for reducing peak power during scan shift at the local level for scan based tests
US9222981B2 (en) * 2012-12-28 2015-12-29 Nvidia Corporation Global low power capture scheme for cores
US9377510B2 (en) 2012-12-28 2016-06-28 Nvidia Corporation System for reducing peak power during scan shift at the global level for scan based tests
US8839063B2 (en) * 2013-01-24 2014-09-16 Texas Instruments Incorporated Circuits and methods for dynamic allocation of scan test resources
CN104950241B (zh) * 2014-03-31 2017-10-24 联发科技（新加坡）私人有限公司 集成电路及在集成电路中建立扫描测试架构的方法
US9081061B1 (en) 2014-04-27 2015-07-14 Freescale Semiconductor, Inc. Scan flip-flop
US20160091563A1 (en) * 2014-09-30 2016-03-31 Taiwan Semiconductor Manufacturing Company Limited Scan flip-flop
CN105988080A (zh) * 2015-03-03 2016-10-05 联发科技（新加坡）私人有限公司 建立扫描测试架构的方法和集成电路与电子装置
CN106556792B (zh) * 2015-09-28 2021-03-19 恩智浦美国有限公司 能够进行安全扫描的集成电路
CN106771958B (zh) 2015-11-19 2020-11-03 恩智浦美国有限公司 具有低功率扫描系统的集成电路
TWI609190B (zh) * 2016-08-05 2017-12-21 國立成功大學 可將測試資料儲存於掃描鏈的積體電路自動測試架構及其方法
CN107783030B (zh) 2016-08-29 2021-04-23 恩智浦美国有限公司 具有低功率扫描系统的集成电路
KR102611888B1 (ko) 2016-11-07 2023-12-11 삼성전자주식회사 스위칭 액티비티에 기초한 반도체 장치의 배치 방법 및 이에 의해 제조된 반도체 장치
US10317464B2 (en) * 2017-05-08 2019-06-11 Xilinx, Inc. Dynamic scan chain reconfiguration in an integrated circuit
US10685730B1 (en) 2018-03-20 2020-06-16 Seagate Technology Llc Circuit including efficient clocking for testing memory interface
TWI689739B (zh) * 2019-01-09 2020-04-01 瑞昱半導體股份有限公司 電路測試系統及電路測試方法
CN111443275B (zh) * 2019-01-17 2022-06-17 瑞昱半导体股份有限公司 电路测试系统及电路测试方法
KR102771558B1 (ko) * 2019-11-14 2025-02-24 삼성전자주식회사 테스트 보드 및 이를 포함하는 테스트 시스템
KR102715979B1 (ko) * 2020-01-29 2024-10-14 에스케이하이닉스 주식회사 마이크로 범프를 구비한 반도체 장치 및 그의 테스트 방법
CN112305404B (zh) * 2020-09-29 2022-11-08 上海兆芯集成电路有限公司 核分区电路与测试装置
TWI722972B (zh) * 2020-10-19 2021-03-21 瑞昱半導體股份有限公司 具有測試機制的隔離電路及其測試方法
US11347920B2 (en) * 2020-10-21 2022-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit synthesis optimization for implements on integrated circuit
TWI739716B (zh) * 2021-03-03 2021-09-11 瑞昱半導體股份有限公司 測試電路
CN117396764A (zh) * 2021-06-28 2024-01-12 华为技术有限公司 芯片和芯片测试装置
CN118468775A (zh) * 2023-02-08 2024-08-09 华为技术有限公司 用于扫描测试的电路系统、方法、装置、介质和程序产品
CN118150987B (zh) * 2024-05-10 2024-08-16 飞腾信息技术有限公司 一种芯片老炼测试方法、系统及相关设备
KR102760401B1 (ko) 2024-08-12 2025-02-03 주식회사 행림엔지니어링종합건축사사무소 토목 기초공사용 흙막이 벽체 시공방법

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080250283A1 (en) 2007-04-04 2008-10-09 Lsi Logic Corporation Power saving flip-flop
US20090106613A1 (en) 2007-10-23 2009-04-23 Lsi Corporation Testing a circuit with compressed scan chain subsets

Family Cites Families (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4698588A (en) 1985-10-23 1987-10-06 Texas Instruments Incorporated Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit
JPH04165644A (ja) 1990-10-30 1992-06-11 Kawasaki Steel Corp 半導体集積回路装置
JP2918730B2 (ja) 1991-12-25 1999-07-12 株式会社日立製作所 デジタル論理装置のスキャン回路
US5907562A (en) * 1996-07-31 1999-05-25 Nokia Mobile Phones Limited Testable integrated circuit with reduced power dissipation
JP3003781B2 (ja) * 1996-08-28 2000-01-31 松下電器産業株式会社 検査容易化設計方法、バスエラー回避設計方法及び集積回路
US5887004A (en) 1997-03-28 1999-03-23 International Business Machines Corporation Isolated scan paths
US6412098B1 (en) 1998-06-30 2002-06-25 Adaptec, Inc. Scan cell including a propagation delay and isolation element
US6114892A (en) 1998-08-31 2000-09-05 Adaptec, Inc. Low power scan test cell and method for making the same
JP2000180510A (ja) * 1998-12-17 2000-06-30 Matsushita Electric Ind Co Ltd 半導体集積回路およびその設計方法
JP3644853B2 (ja) * 1999-09-14 2005-05-11 富士通株式会社 半導体集積回路
US6543018B1 (en) 1999-12-02 2003-04-01 Koninklijke Philips Electronics N.V. System and method to facilitate flexible control of bus drivers during scan test operations
JP2003518631A (ja) 1999-12-24 2003-06-10 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 低電力スキャンフリップフロップ
US6387030B1 (en) 2000-06-30 2002-05-14 Beckman Coulter, Inc. Internal adapter with a pellet well for a centrifuge container
US6615392B1 (en) * 2000-07-27 2003-09-02 Logicvision, Inc. Hierarchical design and test method and system, program product embodying the method and integrated circuit produced thereby
JP2002148309A (ja) * 2000-11-13 2002-05-22 Hitachi Ltd 半導体集積回路
TW594030B (en) 2001-01-11 2004-06-21 Faraday Tech Corp Low-power, high efficiency and accurate cycle testing apparatus
JP2002357636A (ja) * 2001-05-31 2002-12-13 Matsushita Electric Ind Co Ltd スキャンテスト用フリップフロップ回路、論理マクロ、スキャンテスト回路及びそのレイアウト方法
US6920597B2 (en) * 2002-07-31 2005-07-19 Thomas Hans Rinderknecht Uniform testing of tristate nets in logic BIST
US6853212B2 (en) 2002-12-20 2005-02-08 Texas Instruments Incorporated Gated scan output flip-flop
DE102004009693A1 (de) * 2004-02-27 2005-10-13 Advanced Micro Devices, Inc., Sunnyvale Technik zum Kombinieren eines Abtasttests und eines eingebauten Speicherselbsttests
KR101076809B1 (ko) * 2004-06-18 2011-10-25 삼성전자주식회사 불필요한 전력소모를 줄일 수 있는 스캔 플립플롭 회로
US7373572B2 (en) * 2005-01-26 2008-05-13 Intel Corporation System pulse latch and shadow pulse latch coupled to output joining circuit
US7165006B2 (en) * 2004-10-28 2007-01-16 International Business Machines Corporation Scan chain disable function for power saving
JP2007170822A (ja) * 2005-12-19 2007-07-05 Sharp Corp フリップフロップ、および半導体集積回路
JP5058503B2 (ja) * 2006-03-17 2012-10-24 日本電気株式会社 スキャンテスト用回路を備える電子回路、集積回路及び該集積回路に用いられる消費電力低減方法
US8352815B2 (en) 2006-10-18 2013-01-08 Arm Limited Circuit and method operable in functional and diagnostic modes
JP5537158B2 (ja) * 2007-02-12 2014-07-02 メンター グラフィックス コーポレイション 低消費電力スキャンテスト技術および装置
US8166357B2 (en) 2007-12-26 2012-04-24 International Business Machines Corporation Implementing logic security feature for disabling integrated circuit test ports ability to scanout data
JP5256840B2 (ja) * 2008-04-30 2013-08-07 富士通セミコンダクター株式会社 論理回路
JP2009288056A (ja) * 2008-05-29 2009-12-10 Toshiba Corp スキャン出力信号遮断機能付きスキャンフリップフロップ
CN101975922A (zh) * 2010-10-11 2011-02-16 上海电力学院 低功耗扫描测试电路及运行方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080250283A1 (en) 2007-04-04 2008-10-09 Lsi Logic Corporation Power saving flip-flop
US20090106613A1 (en) 2007-10-23 2009-04-23 Lsi Corporation Testing a circuit with compressed scan chain subsets

Also Published As

Publication number Publication date
KR20120108910A (ko) 2012-10-05
EP2503347A1 (en) 2012-09-26
EP2503347B9 (en) 2014-12-17
CN102692599A (zh) 2012-09-26
TWI428620B (zh) 2014-03-01
US20120246529A1 (en) 2012-09-27
EP2503347B1 (en) 2014-08-13
JP2012202991A (ja) 2012-10-22
US8566658B2 (en) 2013-10-22
TW201239377A (en) 2012-10-01

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