CN102692599A - 用于集成电路测试的低功率且面积优化的扫描单元 - Google Patents

用于集成电路测试的低功率且面积优化的扫描单元 Download PDF

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Publication number
CN102692599A
CN102692599A CN2011104156744A CN201110415674A CN102692599A CN 102692599 A CN102692599 A CN 102692599A CN 2011104156744 A CN2011104156744 A CN 2011104156744A CN 201110415674 A CN201110415674 A CN 201110415674A CN 102692599 A CN102692599 A CN 102692599A
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CN
China
Prior art keywords
output
scan
scanning element
scanning
input
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CN2011104156744A
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English (en)
Chinese (zh)
Inventor
R·C·泰库玛拉
P·库玛
P·克里施纳莫斯
P·迈德哈尼
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LSI Corp
Infineon Technologies North America Corp
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Infineon Technologies North America Corp
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Publication of CN102692599A publication Critical patent/CN102692599A/zh
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318541—Scan latches or cell details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318575—Power distribution; Power saving

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
CN2011104156744A 2011-03-25 2011-12-13 用于集成电路测试的低功率且面积优化的扫描单元 Pending CN102692599A (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201161467411P 2011-03-25 2011-03-25
US61/467,411 2011-03-25
US13/216,336 2011-08-24
US13/216,336 US8566658B2 (en) 2011-03-25 2011-08-24 Low-power and area-efficient scan cell for integrated circuit testing

Publications (1)

Publication Number Publication Date
CN102692599A true CN102692599A (zh) 2012-09-26

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CN2011104156744A Pending CN102692599A (zh) 2011-03-25 2011-12-13 用于集成电路测试的低功率且面积优化的扫描单元

Country Status (6)

Country Link
US (1) US8566658B2 (https=)
EP (1) EP2503347B9 (https=)
JP (1) JP2012202991A (https=)
KR (1) KR101344577B1 (https=)
CN (1) CN102692599A (https=)
TW (1) TWI428620B (https=)

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CN106556792A (zh) * 2015-09-28 2017-04-05 飞思卡尔半导体公司 能够进行安全扫描的集成电路
CN111443275A (zh) * 2019-01-17 2020-07-24 瑞昱半导体股份有限公司 电路测试系统及电路测试方法
CN113836854A (zh) * 2020-10-21 2021-12-24 台湾积体电路制造股份有限公司 计算机实施方法、计算机实施系统及计算机可读媒体
CN118150987A (zh) * 2024-05-10 2024-06-07 飞腾信息技术有限公司 一种芯片老炼测试方法、系统及相关设备
WO2024164595A1 (zh) * 2023-02-08 2024-08-15 华为技术有限公司 用于扫描测试的电路系统、方法、装置、介质和程序产品

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KR102010454B1 (ko) * 2012-12-26 2019-08-13 삼성전자주식회사 스캔 플립-플롭, 이의 동작 방법, 및 이를 포함하는 데이터 처리 장치
US9395414B2 (en) 2012-12-28 2016-07-19 Nvidia Corporation System for reducing peak power during scan shift at the local level for scan based tests
US9222981B2 (en) * 2012-12-28 2015-12-29 Nvidia Corporation Global low power capture scheme for cores
US9377510B2 (en) 2012-12-28 2016-06-28 Nvidia Corporation System for reducing peak power during scan shift at the global level for scan based tests
US8839063B2 (en) * 2013-01-24 2014-09-16 Texas Instruments Incorporated Circuits and methods for dynamic allocation of scan test resources
CN104950241B (zh) * 2014-03-31 2017-10-24 联发科技（新加坡）私人有限公司 集成电路及在集成电路中建立扫描测试架构的方法
US9081061B1 (en) 2014-04-27 2015-07-14 Freescale Semiconductor, Inc. Scan flip-flop
US20160091563A1 (en) * 2014-09-30 2016-03-31 Taiwan Semiconductor Manufacturing Company Limited Scan flip-flop
CN105988080A (zh) * 2015-03-03 2016-10-05 联发科技（新加坡）私人有限公司 建立扫描测试架构的方法和集成电路与电子装置
CN106771958B (zh) 2015-11-19 2020-11-03 恩智浦美国有限公司 具有低功率扫描系统的集成电路
TWI609190B (zh) * 2016-08-05 2017-12-21 國立成功大學 可將測試資料儲存於掃描鏈的積體電路自動測試架構及其方法
CN107783030B (zh) 2016-08-29 2021-04-23 恩智浦美国有限公司 具有低功率扫描系统的集成电路
KR102611888B1 (ko) 2016-11-07 2023-12-11 삼성전자주식회사 스위칭 액티비티에 기초한 반도체 장치의 배치 방법 및 이에 의해 제조된 반도체 장치
US10317464B2 (en) * 2017-05-08 2019-06-11 Xilinx, Inc. Dynamic scan chain reconfiguration in an integrated circuit
US10685730B1 (en) 2018-03-20 2020-06-16 Seagate Technology Llc Circuit including efficient clocking for testing memory interface
TWI689739B (zh) * 2019-01-09 2020-04-01 瑞昱半導體股份有限公司 電路測試系統及電路測試方法
KR102771558B1 (ko) * 2019-11-14 2025-02-24 삼성전자주식회사 테스트 보드 및 이를 포함하는 테스트 시스템
KR102715979B1 (ko) * 2020-01-29 2024-10-14 에스케이하이닉스 주식회사 마이크로 범프를 구비한 반도체 장치 및 그의 테스트 방법
CN112305404B (zh) * 2020-09-29 2022-11-08 上海兆芯集成电路有限公司 核分区电路与测试装置
TWI722972B (zh) * 2020-10-19 2021-03-21 瑞昱半導體股份有限公司 具有測試機制的隔離電路及其測試方法
TWI739716B (zh) * 2021-03-03 2021-09-11 瑞昱半導體股份有限公司 測試電路
CN117396764A (zh) * 2021-06-28 2024-01-12 华为技术有限公司 芯片和芯片测试装置
KR102760401B1 (ko) 2024-08-12 2025-02-03 주식회사 행림엔지니어링종합건축사사무소 토목 기초공사용 흙막이 벽체 시공방법

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CN101975922A (zh) * 2010-10-11 2011-02-16 上海电力学院 低功耗扫描测试电路及运行方法

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US6114892A (en) * 1998-08-31 2000-09-05 Adaptec, Inc. Low power scan test cell and method for making the same
US20050283691A1 (en) * 2004-06-18 2005-12-22 Chae Kwan-Yeob Scan flip-flop circuit with reduced power consumption
CN1766797A (zh) * 2004-10-28 2006-05-03 国际商业机器公司 用于禁止扫描链以节省功率的设备及方法
CN101663648A (zh) * 2007-02-12 2010-03-03 明导公司 低功耗扫描测试技术及装置
US20080250283A1 (en) * 2007-04-04 2008-10-09 Lsi Logic Corporation Power saving flip-flop
US20090172819A1 (en) * 2007-12-26 2009-07-02 David Warren Pruden Method and Apparatus for Implementing Logic Security Feature for Disabling Integrated Circuit Test Ports Ability to Scanout Data
CN101975922A (zh) * 2010-10-11 2011-02-16 上海电力学院 低功耗扫描测试电路及运行方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106556792A (zh) * 2015-09-28 2017-04-05 飞思卡尔半导体公司 能够进行安全扫描的集成电路
CN111443275A (zh) * 2019-01-17 2020-07-24 瑞昱半导体股份有限公司 电路测试系统及电路测试方法
CN111443275B (zh) * 2019-01-17 2022-06-17 瑞昱半导体股份有限公司 电路测试系统及电路测试方法
CN113836854A (zh) * 2020-10-21 2021-12-24 台湾积体电路制造股份有限公司 计算机实施方法、计算机实施系统及计算机可读媒体
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WO2024164595A1 (zh) * 2023-02-08 2024-08-15 华为技术有限公司 用于扫描测试的电路系统、方法、装置、介质和程序产品
CN118150987A (zh) * 2024-05-10 2024-06-07 飞腾信息技术有限公司 一种芯片老炼测试方法、系统及相关设备

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Publication number Publication date
KR20120108910A (ko) 2012-10-05
EP2503347A1 (en) 2012-09-26
EP2503347B9 (en) 2014-12-17
TWI428620B (zh) 2014-03-01
US20120246529A1 (en) 2012-09-27
EP2503347B1 (en) 2014-08-13
JP2012202991A (ja) 2012-10-22
KR101344577B1 (ko) 2013-12-26
US8566658B2 (en) 2013-10-22
TW201239377A (en) 2012-10-01

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