594030 修正日期9 2 · 7 . 8 〇6859twfl.doc/006 玖、發明說明： 本發明是有關於一種多功掃描胞（Multiplex Scan Cell)，且特別是有關於一種多功掃描胞，其可以在掃描數 據位移模式（Scan Data Shift Mode)時，防止在核心邏輯中 觸發多餘事件（Redundant Events)。 數位積體電路是由複雜的電路結構體系所組成，而用 來對數據實施許多邏輯操作。這些電路結構體系的複雜度 往往使得測試積體電路的變得相當困難。 因此，在積體電路中之電路可區分爲電路結構體系及 可掃描記憶元件。爲使得這些積體電路得以順利被測試， 這些記憶元件（例如是正反器）的原始操作結構設計是可以 重新裝配的。 用來測試積體電路的技術有很多種，其中一種技術爲 將閉鎖器及正反器配置於一串聯位移暫存器鏈，以將測試 信號移位至一元件以將響應濾通回饋出以作分析。 由於正反器爲可以重新設計的，在測試正反器時，其 可以裝置成其連接網路及電路之原始操作裝置，以對數據 實施邏輯操作。然後該正反器可以改回掃描結構，以將數 據移位出掃描鏈，以作爲分析之測試響應數據。 §靑参考第1圖’其繪不出一個傳統之多功（MUX)掃描 胞。此一型式之掃描測試的基本模組使用一多功器50驅 動一正反器60。該多功器50將數據在測試數據20及系統 數據10之掃描之間轉換，以代表一般或系統之資訊。一 選擇控制線（SEL)30控制此一轉換。在第一掃描胞中，該 594030 修正日期92 · 7 · 8 06859twf1.doc/006 串聯輸入連接至主要輸入（Primary Input)或是掃描輸入。在 中間掃描胞中’ S亥串聯輸入通常來自於之前的掃描胞輸 出。而在最後掃描胞中，輸出爲掃描輸出（s〇)7〇。選擇測 試或串聯模式產生一由輸入到輸出之完整的串聯位移途 徑。 在掃描數據移位模式中，SEL30爲邏輯1。在掃描數 據位移模式中，掃描輸出(SO)70數據與核心邏輯90無關。 然而，此一掃描輸出數據會不斷觸動核心邏輯90並產生 事件。這些多餘之事件使得模擬之複雜度增高，導致一較 長的模擬時間。還有，因爲這些不必要事件的產生，使得 在測試時耗損了較多的功率。 因此，爲克服傳統裝置之缺點，本發明提供一種方法， 以在掃描數據位移模式下，防止因觸發核心邏輯而產生多 餘事件。 第2圖係一方塊圖，其繪示出基於本發明之一多功掃 描胞的實施例。該多功掃描胞包括一多功器15〇, 一正反 器160，以及一邏輯元件18〇。而該多功器150在一測試數 據120及一系統數據11 〇之間作選擇。 邏輯元件180是由SEL130來控制的。在數據掃描移 位模式時，SEL130爲邏輯1，而因爲邏輯元件18〇被關 閉，所以沒有肘節數據（Toggled Data)會干擾到核心邏輯 190。因此，因爲沒有觸動到核心邏輯19〇，所以可以防止 多餘事件。 如以上所述，在傳統之多功掃描胞中，太多的多餘事 06859twfl . doc/006 修正日期9 2 · 7 · 8 件會在測試數據模式時被觸發。這些多餘事件導致不可接 受之長模擬時間。此外，這些多餘事件在測試時消耗過多 的功率。 相反地，本發明之多功掃描胞可以在掃描數據移位模 式時，防止觸發多餘事件。如此，使得摸擬時間縮短，加 速認證之操作。而且其還可以使得在測試所消耗之功率減 低。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖係繪示一傳統之多功掃描胞。 第2圖係一方塊圖，繪示出基於本發明之一多功掃描 胞的實施例。 第3圖係一電路圖，繪示出基於本發明之一多功掃描 胞的實施例。 第4圖係一電路圖，繪示出基於本發明之一多功掃描 胞的實施例。 圖式之標記說明： 10 :系統數據 20 ··測試數據 30 :選擇控制線 50 :多功器 60 :正反器 594030 06859twfl.doc/006 70 :掃描輸出 90 :核心邏輯 110 :系統數據 120 :測試數據 130 :選擇控制線 150 :多功器 160 :正反器 170 :掃描路徑 180 :邏輯元件 190 :核心邏輯 210 :系統數據 220 :測試數據 230 :選擇控制線 250 ··多功器 260 :正反器 270 :掃描路徑 280 :閉鎖器 290 :核心邏輯 310 :系統數據 320 :測試數據 330 :選擇控制線 350 :多功器 360 :正反器 370 :掃描路徑 修正日期9 2 · 7 . 8594030 Revised date 9 2 · 7.8 〇 6859twfl.doc / 006 玖, Description of the invention: The present invention relates to a multiplex scan cell, and in particular to a multiplex scan cell. When scanning data shift mode (Scan Data Shift Mode), prevent redundant events (Redundant Events) from being triggered in the core logic. The digital integrated circuit is composed of a complex circuit structure system, and is used to perform many logical operations on data. The complexity of these circuit architectures often makes it difficult to test integrated circuits. Therefore, the circuits in integrated circuits can be divided into circuit structure systems and scannable memory elements. To enable these integrated circuits to be tested successfully, the original operating structure design of these memory elements (eg, flip-flops) can be reassembled. There are many techniques for testing integrated circuits, one of which is to arrange the latch and the flip-flop in a series displacement register chain to shift the test signal to a component to filter the response back to do analysis. Since the flip-flop can be redesigned, when testing the flip-flop, it can be installed as its original operating device connected to the network and circuits to perform logical operations on the data. The flip-flop can then be changed back to the scan structure to shift the data out of the scan chain as test response data for analysis. § 靑 Refer to Fig. 1 ', it cannot draw a traditional MUX scanning cell. The basic module of this type of scanning test uses a multiplier 50 to drive a flip-flop 60. The multiplexer 50 converts data between the scans of the test data 20 and the system data 10 to represent general or system information. A selection control line (SEL) 30 controls this conversion. In the first scan cell, the 594030 correction date 92 · 7 · 8 06859twf1.doc / 006 tandem input is connected to the primary input or the scan input. In the middle scan cell, the 'S' tandem input usually comes from the output of the previous scan cell. In the last scanning cell, the output is the scanning output (s0) 70. Selecting test or series mode produces a complete series displacement path from input to output. In the scan data shift mode, SEL30 is a logic one. In the scan data shift mode, the scan output (SO) 70 data is independent of the core logic 90. However, this scan output data will constantly trigger the core logic 90 and generate events. These extra events increase the complexity of the simulation and lead to a longer simulation time. Also, because these unnecessary events occur, more power is consumed during the test. Therefore, in order to overcome the shortcomings of the conventional device, the present invention provides a method to prevent the occurrence of redundant events caused by triggering the core logic in the scan data displacement mode. Figure 2 is a block diagram illustrating an embodiment of a multi-function scanning cell based on the present invention. The multi-function scanning cell includes a multi-function device 150, a flip-flop 160, and a logic element 180. The multiplexer 150 selects between a test data 120 and a system data 110. The logic element 180 is controlled by the SEL 130. In the data scan shift mode, SEL130 is logic 1, and because logic element 180 is turned off, no toggle data will interfere with core logic 190. Therefore, since the core logic 19 is not touched, unnecessary events can be prevented. As mentioned above, in the traditional multi-function scanning cell, there are too many superfluous things. 06859twfl .doc / 006 Correction date 9 2 · 7 · 8 items will be triggered in the test data mode. These unwanted events result in unacceptably long simulation times. In addition, these extra events consume too much power during testing. In contrast, the multi-function scanning cell of the present invention can prevent unnecessary events from being triggered in the scan data shift mode. In this way, the simulation time is shortened and the operation of certification is accelerated. And it can also reduce the power consumed during testing. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the preferred embodiments are described below in detail with the accompanying drawings as follows: Brief description of the drawings: Figure 1 Draw a traditional multi-power scanning cell. Fig. 2 is a block diagram showing an embodiment of a multi-function scanning cell based on the present invention. Fig. 3 is a circuit diagram showing an embodiment of a multi-function scanning cell based on the present invention. Fig. 4 is a circuit diagram showing an embodiment of a multi-function scanning cell based on the present invention. Explanation of the marks of the drawings: 10: System data 20 ·· Test data 30: Select control line 50: Multi-function device 60: Flip-flop 594030 06859twfl.doc / 006 70: Scan output 90: Core logic 110: System data 120: Test data 130: Select control line 150: Multiplexer 160: Flip-flop 170: Scan path 180: Logic element 190: Core logic 210: System data 220: Test data 230: Select control line 250 Flip-flop 270: Scanning path 280: Blocker 290: Core logic 310: System data 320: Test data 330: Select control line 350: Multiplexer 360: Flip-flop 370: Scan path correction date 9 2 · 7.8
594030 修正日期92.7.8 0 6 8 5 9twf1 . doc/0 0 6 280 :或閘 390 :核心邏輯 實施例 爲克服傳統之多功掃描胞之缺點，本發明提供一種改 良的多功掃描胞，以在掃描數據位移模式下，防止在核心 邏輯中觸發多餘事件。 請參考第2圖，其係一方塊圖，繪示出本發明之一多 功掃描器之實施例。此一多功掃描器包括一多功器15〇, 一正反器160及一邏輯元件180。該多功器150在一測試 數據120及系統數據110之間作選擇。 邏輯元件180可以是任何邏輯元件或元件組合，其可 提供一種裝置，基於選擇信號，使數據流經該元件或該元 件組合，或是防止數據流經元件或元件組合。邏輯元件180 是由一選擇控制線SEL 130所控制。在掃描數據移位模式 下，SEL 130爲邏輯1。因此，因爲邏輯元件180爲關閉的， 所以沒有肘節數據會干擾核心邏輯190。只有掃描路徑(SI-S〇-SI)170繼續捺跳。因此，多餘事件得以防止。 參考第3圖，其繪示出基於本發明之一多功掃描胞之 電路圖。該多功掃描器包括一多功器250，一正反器260 及一閉鎖器280。該多功器250在測試數據220及系統數 據210之間作一選擇。 閉鎖器280是由SEL230所控制。在掃描數據位移模 式下，SEL230爲邏輯1。因此，因爲閉鎖器280爲關閉的， 所以沒有肘節數據會千擾到核心邏輯290。只有掃描路徑 594030 修正日期9 2 . 7 . 8 〇6859twfl.doc/006 (SI-SO-SI)270會繼續捺跳。因此，可以防止多餘事件。 參考第4圖，其繪示出基於本發明之一多功掃描胞之 電路圖。該多功掃描器包括一多功器350，一正反器360 及一或閘（OR Gate)380。該多功器350在測試數據320及 系統數據310之間作一選擇。 或閘380是由SEL 330所控制。在掃描數據位移模式 下，SEL330爲邏輯1。因此，因爲或閘380爲關閉的，也 就是維持輸出數據爲1，所以沒有肘節數據會干擾到核心 邏輯390。只有掃描路徑(SI-SO_SI)370會繼續捺跳。因此， 可以防止多餘事件。在正常操作下，SEL330爲低電位， 因此數據可由或閘380傳至核心邏輯390 ° 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者’在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。594030 Correction date 92.7.8 0 6 8 5 9twf1.doc / 0 0 6 280: OR gate 390: Core logic embodiment In order to overcome the shortcomings of the traditional multi-function scanning cell, the present invention provides an improved multi-function scanning cell to Prevents unnecessary events from being triggered in the core logic in scan data shift mode. Please refer to FIG. 2, which is a block diagram illustrating an embodiment of a multi-function scanner according to the present invention. The multi-function scanner includes a multi-function device 15, a flip-flop 160 and a logic element 180. The multiplexer 150 selects between a test data 120 and a system data 110. The logic element 180 may be any logic element or combination of elements, which may provide a means for causing data to flow through the element or combination of elements or prevent data from flowing through the element or combination of elements based on a selection signal. The logic element 180 is controlled by a selection control line SEL 130. In the scan data shift mode, the SEL 130 is a logic one. Therefore, because the logic element 180 is off, no toggle data will interfere with the core logic 190. Only the scan path (SI-SO-SI) 170 continues to hop. Therefore, unnecessary events are prevented. Referring to FIG. 3, a circuit diagram of a multi-function scanning cell according to the present invention is shown. The multi-function scanner includes a multi-function device 250, a flip-flop 260, and a latch 280. The multiplexer 250 selects between test data 220 and system data 210. The latch 280 is controlled by the SEL 230. In scan data shift mode, SEL230 is logic 1. Therefore, because the latch 280 is closed, no toggle data will disturb the core logic 290. Only the scan path 594030 correction date 9 2. 7. 8 〇 6859twfl.doc / 006 (SI-SO-SI) 270 will continue to jump. Therefore, unnecessary events can be prevented. Referring to FIG. 4, a circuit diagram of a multi-function scanning cell according to the present invention is shown. The multi-function scanner includes a multi-function generator 350, a flip-flop 360, and an OR gate 380. The multiplexer 350 selects between test data 320 and system data 310. The OR gate 380 is controlled by the SEL 330. In the scan data shift mode, SEL330 is logic 1. Therefore, because the OR gate 380 is closed, that is, the output data is maintained at 1, so no toggle data will interfere with the core logic 390. Only the scan path (SI-SO_SI) 370 will continue to hop. Therefore, unnecessary events can be prevented. Under normal operation, SEL330 is at a low potential, so the data can be transferred from OR gate 380 to the core logic 390 °. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Various changes and modifications can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.
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