KR101025055B1 - 프리프레그, 프리프레그의 제조 방법, 기판 및 반도체 장치 - Google Patents
프리프레그, 프리프레그의 제조 방법, 기판 및 반도체 장치 Download PDFInfo
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- KR101025055B1 KR101025055B1 KR1020107003486A KR20107003486A KR101025055B1 KR 101025055 B1 KR101025055 B1 KR 101025055B1 KR 1020107003486 A KR1020107003486 A KR 1020107003486A KR 20107003486 A KR20107003486 A KR 20107003486A KR 101025055 B1 KR101025055 B1 KR 101025055B1
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Abstract
Description
도 2는 제1 실시형태의 프리프레그가 갖는 제2 수지층의 두께에 대해 설명하기 위한 단면도이다.
도 3은 본 발명의 프리프레그를 제조하는 공정의 일례를 나타내는 공정도이다.
도 4는 본 발명의 프리프레그의 일례(제2 실시형태)를 나타내는 단면도이다.
도 5는 제2 실시형태의 프리프레그가 갖는 2개의 수지층의 두께의 관계를 설명하기 위한 단면도이다.
도 6은 본 발명의 기판의 일례를 나타내는 단면도이다.
도 7은 본 발명의 반도체 장치의 일례를 나타내는 단면도이다.
T0 [㎛] |
B1 [㎛] |
B2 [㎛] |
두께의 비 (B2/B1) |
열팽창 계수 [ppm] |
탄성률 [MPa] |
|
실시예 1 | 30 | 10 | 5 | 0.50 | 11 | 24 |
실시예 2 | 30 | 10 | 5 | 0.50 | 12 | 22 |
실시예 3 | 30 | 10 | 5 | 0.50 | 15 | 20 |
실시예 4 | 35 | 10 | 10 | 1.00 | 12 | 23 |
실시예 5 | 40 | 11 | 5 | 0.45 | 11 | 24 |
실시예 6 | 60 | 10 | 8 | 0.80 | 12 | 25 |
실시예 7 | 30 | 10 | 5 | 0.50 | 15 | 22 |
실시예 8 | 30 | 10 | 5 | 0.50 | 8 | 25 |
실시예 9 | 30 | 11 | 4 | 0.36 | 8 | 25 |
실시예 10 | 35 | 16 | 4 | 0.25 | 10 | 24 |
실시예 11 | 40 | 12 | 4 | 0.33 | 8 | 25 |
실시예 12 | 35 | 16 | 4 | 0.25 | 12 | 22 |
실시예 13 | 40 | 21 | 4 | 0.19 | 10 | 24 |
비교예 1 | 75 | 10 | 10 | 1.00 | 8 | 26 |
비교예 2 | 40 | 8 | 8 | 1.00 | 8 | 25 |
t1 [㎛] |
t2 [㎛] |
t3 [㎛] |
t3 - 설계값 | 기판의 두께 [㎛] |
|
실시예 1 | 12 | 4 | 24 | 0 | 146 |
실시예 2 | 12 | 5 | 25 | +1 | 148 |
실시예 3 | 12 | 4 | 24 | 0 | 146 |
실시예 4 | 12 | 4 | 28 | -1 | 154 |
실시예 5 | 12 | 5 | 34 | 0 | 166 |
실시예 6 | 12 | 5 | 55 | +1 | 208 |
실시예 7 | 12 | 7 | 27 | +3 | 152 |
실시예 8 | 12 | 4 | 22 | -2 | 142 |
실시예 9 | 18 | 2 | 20 | 0 | 150 |
실시예 10 | 18 | 7 | 27 | +1 | 164 |
실시예 11 | 18 | 3 | 31 | 0 | 172 |
실시예 12 | 18 | 7 | 26 | 0 | 162 |
실시예 13 | 18 | 12 | 30 | -1 | 170 |
비교예 1 | 18 | 1 | 64 | -2 | 238 |
비교예 2 | 18 | 0 | 31 | -(성형 불량) | 172 |
매립성 | 도금 밀착성 | 절연 신뢰성 | 접속 신뢰성 | |
실시예 1 | ◎ | ◎ | ◎ | ◎ |
실시예 2 | ◎ | ◎ | ◎ | ◎ |
실시예 3 | ◎ | ◎ | ◎ | ◎ |
실시예 4 | ◎ | ◎ | ◎ | ◎ |
실시예 5 | ◎ | ◎ | ◎ | ◎ |
실시예 6 | ◎ | ◎ | ◎ | ◎ |
실시예 7 | × | ◎ | ◎ | ○ |
실시예 8 | ○ | ○∼△ | ◎ | ◎ |
실시예 9 | ○ | ◎ | ◎ | ◎ |
실시예 10 | ◎ | ◎ | ◎ | ◎ |
실시예 11 | ○ | ◎ | ◎ | ◎ |
실시예 12 | ◎ | ◎ | ◎ | ◎ |
실시예 13 | ◎ | ◎ | ◎ | ◎ |
비교예 1 | △ | ◎ | × | × |
비교예 2 | × | ◎ | × | × |
Claims (29)
- 시트 형상 기재를 포함하는 코어층과,
상기 코어층의 한쪽 면 측에 설치되고 제1 수지 조성물로 구성된 제1 수지층과,
상기 코어층의 다른쪽 면 측에 설치되고 제2 수지 조성물로 구성된 제2 수지층을 가지며,
상기 제1 수지 조성물과 상기 제2 수지 조성물은 각각 경화성 수지와, 무기 충전재와, 에폭시실란 커플링제를 포함하고,
상기 제2 수지층에 배선을 갖는 회로 배선부를 형성할 때, 상기 제2 수지 조성물의 일부가 상기 회로 배선부의 상기 배선끼리 사이의 공극부에 매립되고,
상기 제2 수지 조성물의 일부가 상기 공극부에 매립된 부분의 상기 제2 수지층의 두께는 하기 식 1)로 표시되며,
B1 = t1 × (1 - S / 100) + t2 … 식 1)
(단, B1은 상기 제2 수지층의 상기 두께 ㎛를 나타내고, t1은 상기 회로 배선부의 두께 ㎛를 나타내며, S는 상기 회로 배선부의 잔동률 %를 나타내고, t2는 상기 회로 배선부의 윗면으로부터 상기 제2 수지층의 윗면까지의 두께 ㎛를 나타낸다)
상기 제1 수지층의 두께와 상기 제2 수지층의 상기 두께가 동일하고, 또한 상기 제1 수지 조성물과 상기 제2 수지 조성물 조성이 다른 것을 특징으로 하는 프리프레그. - 청구항 1에 있어서,
상기 제1 수지층 위에 도체층을 형성하여 사용되는 프리프레그. - 청구항 1에 있어서,
상기 시트 형상 기재의 두께가 25 ㎛ 이하인 프리프레그. - 청구항 2에 있어서,
상기 제1 수지층에 상기 도체층을 접합했을 때, 상기 제1 수지층과 상기 도체층의 박리 강도는 0.5 kN/m 이상인 프리프레그. - 청구항 2에 있어서,
상기 제1 수지층의 두께가 3∼15 ㎛인 프리프레그. - 삭제
- 청구항 1에 있어서,
상기 경화성 수지는 시아네이트 수지를 포함하는 것인 프리프레그. - 청구항 7에 있어서,
상기 시아네이트 수지는 노볼락형 시아네이트 수지를 포함하는 것인 프리프레그. - 청구항 2에 있어서,
상기 제1 수지 조성물은 추가로 경화제를 포함하는 것인 프리프레그. - 청구항 9에 있어서,
상기 경화제는 이미다졸계 화합물을 포함하는 것인 프리프레그. - 청구항 2에 있어서,
상기 제1 수지 조성물은 추가로 상기 경화성 수지와 종류가 다른 제2 수지를 포함하는 것인 프리프레그. - 청구항 11에 있어서,
상기 제2 수지는 페녹시계 수지를 포함하는 것인 프리프레그. - 청구항 3에 있어서,
상기 프리프레그의 두께는 35 ㎛ 이하인 프리프레그. - 삭제
- 삭제
- 삭제
- 청구항 1에 기재된 프리프레그를 제조하는 프리프레그의 제조 방법으로서,
상기 코어층과, 한쪽 면에 상기 제1 수지 조성물이 층상으로 부여된 제1 시트재(材)와, 제2 수지 조성물이 층상으로 부여된 제2 시트재를 준비하는 공정과,
상기 코어층에 상기 제1 수지 조성물 및 상기 제2 수지 조성물이 접촉하도록 상기 제1 시트재 및 상기 제2 시트재를 겹쳐 접합함으로써 적층체를 얻는 공정과,
상기 적층체 내로부터 기포를 제거하는 공정과,
상기 적층체로부터 상기 제2 시트재를 제거하는 공정과,
상기 제2 수지 조성물의 일부가 회로 배선부의 배선끼리 사이의 공극부에 매립되도록 상기 배선 회로부를 상기 제2 수지층 위에 형성하는 공정을 가지며,
상기 제2 수지 조성물의 일부가 상기 공극부에 매립된 부분의 상기 제2 수지층의 두께는 하기 식 1)로 표시되고,
B1 = t1 × (1 - S / 100) + t2 … 식 1)
(단, B1은 상기 제2 수지층의 상기 두께 ㎛를 나타내고, t1은 상기 회로 배선부의 두께 ㎛를 나타내며, S는 상기 회로 배선부의 잔동률 %를 나타내고, t2는 상기 회로 배선부의 윗면으로부터 상기 제2 수지층의 윗면까지의 두께 ㎛를 나타낸다)
상기 제1 수지층의 두께와 상기 제2 수지층의 상기 두께가 동일하며, 또한 상기 제1 수지 조성물과 상기 제2 수지 조성물 조성이 다른 것을 특징으로 하는 프리프레그의 제조 방법. - 청구항 17에 있어서,
상기 코어층과, 상기 제1 시트재 및 상기 제2 시트재의 접합은 감압하에 행해지는 프리프레그의 제조 방법. - 청구항 17에 있어서,
상기 적층체 내로부터의 기포의 제거는 가열 처리에 의해 행해지는 프리프레그의 제조 방법. - 청구항 19에 있어서,
상기 가열 처리는 상기 제1 수지 조성물 및 상기 제2 수지 조성물 중에서 융점이 높은 쪽의 수지 조성물의 융점 이상의 온도에서 행해지는 프리프레그의 제조 방법. - 청구항 17에 있어서,
상기 제1 시트는 도전재료로 구성되어 있는 것인 프리프레그의 제조 방법. - 청구항 17에 있어서,
상기 제1 시트재 및 상기 제2 시트재는 각각 수지 시트로 구성되어 있는 것이고,
상기 적층체 내로부터 기포를 제거하는 공정 후에 상기 적층체로부터 상기 수지 시트를 제거하는 공정을 갖는 프리프레그의 제조 방법. - 청구항 22에 있어서,
상기 수지 시트는 상기 수지 조성물이 부여되는 면에 박리 처리가 실시되고 있는 것인 프리프레그의 제조 방법. - 청구항 1에 기재된 프리프레그와,
상기 프리프레그의 상기 제2 수지층에 매설된 회로 배선부를 갖는 것을 특징으로 하는 기판. - 청구항 24에 있어서,
상기 프리프레그 전체의 두께를 T0[㎛]로 하고, 상기 회로 배선부의 높이를 t1[㎛]로 할 때, T0와 t1의 차가 35 ㎛ 이하인 기판. - 청구항 24에 있어서,
상기 프리프레그의 면 방향의 열팽창 계수가 16 ppm 이하인 기판. - 청구항 1에 기재된 프리프레그를 적층하여 얻어지는 것을 특징으로 하는 기판.
- 청구항 24에 기재된 기판과, 상기 기판에 탑재된 반도체 소자를 갖는 것을 특징으로 하는 반도체 장치.
- 청구항 27에 기재된 기판을 갖는 것을 특징으로 하는 반도체 장치.
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TR201722994A2 (tr) * | 2017-12-29 | 2019-07-22 | Kordsa Teknik Tekstil As | Bi̇r sicak eri̇yi̇k epoksi̇ reçi̇ne si̇stemi̇ ve yapimi i̇çi̇n proses |
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JP3862770B2 (ja) * | 1995-09-07 | 2006-12-27 | 日立化成工業株式会社 | 金属張積層板の製造方法 |
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JP2006160899A (ja) * | 2004-12-08 | 2006-06-22 | Matsushita Electric Ind Co Ltd | 電気絶縁性基材および配線基板の製造方法 |
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KR101014919B1 (ko) | 2011-02-15 |
US20090302462A1 (en) | 2009-12-10 |
US20110256367A1 (en) | 2011-10-20 |
KR20080066877A (ko) | 2008-07-16 |
US8110444B2 (en) | 2012-02-07 |
TW200726796A (en) | 2007-07-16 |
MY146044A (en) | 2012-06-15 |
WO2007063960A1 (ja) | 2007-06-07 |
KR20100023978A (ko) | 2010-03-04 |
US8044505B2 (en) | 2011-10-25 |
TW201341439A (zh) | 2013-10-16 |
TWI415880B (zh) | 2013-11-21 |
US20100300619A1 (en) | 2010-12-02 |
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