KR100976830B1 - Dram 센스 증폭기의 바이어스 센싱 - Google Patents
Dram 센스 증폭기의 바이어스 센싱 Download PDFInfo
- Publication number
- KR100976830B1 KR100976830B1 KR1020057003148A KR20057003148A KR100976830B1 KR 100976830 B1 KR100976830 B1 KR 100976830B1 KR 1020057003148 A KR1020057003148 A KR 1020057003148A KR 20057003148 A KR20057003148 A KR 20057003148A KR 100976830 B1 KR100976830 B1 KR 100976830B1
- Authority
- KR
- South Korea
- Prior art keywords
- voltage
- digit line
- coupled
- coupling
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000008878 coupling Effects 0.000 claims abstract description 115
- 238000010168 coupling process Methods 0.000 claims abstract description 115
- 238000005859 coupling reaction Methods 0.000 claims abstract description 115
- 239000003990 capacitor Substances 0.000 claims description 67
- 238000002955 isolation Methods 0.000 claims description 51
- 238000000034 method Methods 0.000 claims 15
- 230000004044 response Effects 0.000 claims 7
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000000926 separation method Methods 0.000 abstract description 37
- 238000010586 diagram Methods 0.000 description 26
- 230000008859 change Effects 0.000 description 14
- 230000007704 transition Effects 0.000 description 12
- 101100166255 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CEP3 gene Proteins 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 101100495436 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CSE4 gene Proteins 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000003071 parasitic effect Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000011664 signaling Effects 0.000 description 3
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/065—Differential amplifiers of latching type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/233,871 US6757202B2 (en) | 2002-08-29 | 2002-08-29 | Bias sensing in DRAM sense amplifiers |
| US10/233,871 | 2002-08-29 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020087020886A Division KR100939054B1 (ko) | 2002-08-29 | 2003-08-26 | Dram 센스 증폭기의 바이어스 센싱 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20070089894A KR20070089894A (ko) | 2007-09-04 |
| KR100976830B1 true KR100976830B1 (ko) | 2010-08-20 |
Family
ID=31977313
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020087020886A Expired - Lifetime KR100939054B1 (ko) | 2002-08-29 | 2003-08-26 | Dram 센스 증폭기의 바이어스 센싱 |
| KR1020057003148A Expired - Lifetime KR100976830B1 (ko) | 2002-08-29 | 2003-08-26 | Dram 센스 증폭기의 바이어스 센싱 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020087020886A Expired - Lifetime KR100939054B1 (ko) | 2002-08-29 | 2003-08-26 | Dram 센스 증폭기의 바이어스 센싱 |
Country Status (9)
| Country | Link |
|---|---|
| US (6) | US6757202B2 (enExample) |
| EP (2) | EP2309513B1 (enExample) |
| JP (2) | JP2005536827A (enExample) |
| KR (2) | KR100939054B1 (enExample) |
| CN (1) | CN1685438B (enExample) |
| AU (1) | AU2003260089A1 (enExample) |
| SG (1) | SG153662A1 (enExample) |
| TW (1) | TWI311319B (enExample) |
| WO (1) | WO2004021354A1 (enExample) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6978088B2 (en) * | 2002-08-27 | 2005-12-20 | Pentax Corporation | Optical element retracting mechanism for a retractable lens |
| US6757202B2 (en) * | 2002-08-29 | 2004-06-29 | Micron Technology, Inc. | Bias sensing in DRAM sense amplifiers |
| US20040257882A1 (en) * | 2003-06-20 | 2004-12-23 | Blaine Stackhouse | Bias generation having adjustable range and resolution through metal programming |
| US8324872B2 (en) * | 2004-03-26 | 2012-12-04 | Marvell World Trade, Ltd. | Voltage regulator with coupled inductors having high coefficient of coupling |
| US7372092B2 (en) * | 2005-05-05 | 2008-05-13 | Micron Technology, Inc. | Memory cell, device, and system |
| KR100869541B1 (ko) * | 2006-05-26 | 2008-11-19 | 삼성전자주식회사 | 오픈 비트라인 구조의 메모리 장치 및 이 장치의 비트라인데이터 센싱 방법 |
| US7408813B2 (en) * | 2006-08-03 | 2008-08-05 | Micron Technology, Inc. | Block erase for volatile memory |
| TWI381394B (zh) * | 2008-06-09 | 2013-01-01 | Promos Technologies Inc | 動態隨機存取記憶體之資料感測方法 |
| US8625372B2 (en) | 2008-12-24 | 2014-01-07 | Stmicroelectronics International N.V. | Noise tolerant sense circuit |
| US8164942B2 (en) * | 2010-02-01 | 2012-04-24 | International Business Machines Corporation | High performance eDRAM sense amplifier |
| US9087559B2 (en) * | 2012-12-27 | 2015-07-21 | Intel Corporation | Memory sense amplifier voltage modulation |
| US9053960B2 (en) * | 2013-03-04 | 2015-06-09 | Qualcomm Incorporated | Decoupling capacitor for integrated circuit |
| WO2014151659A1 (en) * | 2013-03-15 | 2014-09-25 | Silicon Image, Inc. | Method and apparatus for implementing wide data range and wide common-mode receivers |
| US9245604B2 (en) | 2013-05-08 | 2016-01-26 | International Business Machines Corporation | Prioritizing refreshes in a memory device |
| US9224450B2 (en) * | 2013-05-08 | 2015-12-29 | International Business Machines Corporation | Reference voltage modification in a memory device |
| US9318187B2 (en) * | 2013-07-23 | 2016-04-19 | Micron Technology, Inc. | Method and apparatus for sensing in a memory |
| US9378781B1 (en) | 2015-04-09 | 2016-06-28 | Qualcomm Incorporated | System, apparatus, and method for sense amplifiers |
| US9378780B1 (en) | 2015-06-16 | 2016-06-28 | National Tsing Hua University | Sense amplifier |
| US10395697B1 (en) * | 2018-02-08 | 2019-08-27 | Micron Technology, Inc. | Self-referencing sensing schemes with coupling capacitance |
| DE102018202871B4 (de) * | 2018-02-26 | 2019-09-12 | Dialog Semiconductor (Uk) Limited | Leistungseffiziente Treiberschaltung, die Ladungsrückgewinnung nutzt, und Verfahren zum Ansteuern einer Last |
| US10699755B2 (en) * | 2018-09-18 | 2020-06-30 | Micron Technology, Inc. | Apparatuses and methods for plate coupled sense amplifiers |
| US11727980B2 (en) * | 2021-03-30 | 2023-08-15 | Micron Technology, Inc. | Apparatuses and methods for single-ended global and local input/output architecture |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0177776B1 (ko) * | 1995-08-23 | 1999-04-15 | 김광호 | 고집적 반도체 메모리 장치의 데이타 센싱회로 |
| US20020009008A1 (en) | 2000-06-26 | 2002-01-24 | Stmicroelectronics S.A. | Process for controlling a read access for a dynamic random access memory and corresponding memory |
| US20020080664A1 (en) | 2000-12-25 | 2002-06-27 | Kabushiki Kaisha Toshiba | Semiconductor device |
Family Cites Families (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4625300A (en) * | 1982-12-01 | 1986-11-25 | Texas Instruments Incorporated | Single-ended sense amplifier for dynamic memory array |
| JPS60236191A (ja) | 1984-05-08 | 1985-11-22 | Matsushita Electric Ind Co Ltd | 半導体記憶装置 |
| JPS61217986A (ja) * | 1985-03-25 | 1986-09-27 | Hitachi Ltd | ダイナミツク型ram |
| JPS63282993A (ja) * | 1987-05-15 | 1988-11-18 | Mitsubishi Electric Corp | 半導体ダイナミック・ランダム・アクセス・メモリ |
| JPS63282994A (ja) * | 1987-05-15 | 1988-11-18 | Mitsubishi Electric Corp | 半導体ダイナミック・ランダム・アクセス・メモリ |
| JPH0758592B2 (ja) * | 1987-11-30 | 1995-06-21 | 日本電気株式会社 | 半導体メモリ |
| JPH03296989A (ja) * | 1990-04-16 | 1991-12-27 | Nec Corp | ダイナミック型センスアンプ |
| US5157634A (en) | 1990-10-23 | 1992-10-20 | International Business Machines Corporation | Dram having extended refresh time |
| JP2817552B2 (ja) * | 1992-01-30 | 1998-10-30 | 日本電気株式会社 | 半導体メモリ装置 |
| JPH05210975A (ja) * | 1992-01-30 | 1993-08-20 | Nec Corp | ダイナミックram |
| US5291437A (en) | 1992-06-25 | 1994-03-01 | Texas Instruments Incorporated | Shared dummy cell |
| JP3315293B2 (ja) * | 1995-01-05 | 2002-08-19 | 株式会社東芝 | 半導体記憶装置 |
| JP3272193B2 (ja) * | 1995-06-12 | 2002-04-08 | 株式会社東芝 | 半導体装置およびその動作方法 |
| KR100214462B1 (ko) | 1995-11-27 | 1999-08-02 | 구본준 | 반도체메모리셀의 라이트 방법 |
| JP3824370B2 (ja) * | 1997-03-03 | 2006-09-20 | 富士通株式会社 | 半導体装置 |
| JP3296989B2 (ja) | 1997-03-31 | 2002-07-02 | ユニ・チャーム株式会社 | 水解性シート及びその製造方法 |
| JPH10302469A (ja) * | 1997-04-25 | 1998-11-13 | Fujitsu Ltd | 半導体記憶装置 |
| JPH1144292A (ja) | 1997-07-25 | 1999-02-16 | Ishikawajima Harima Heavy Ind Co Ltd | 訓練シミュレータのポンプモデル |
| DE19735137C1 (de) | 1997-08-13 | 1998-10-01 | Siemens Ag | Schaltungsvorrichtung für die Bewertung des Dateninhalts von Speicherzellen |
| US5995421A (en) * | 1998-05-29 | 1999-11-30 | Stmicroelectronics, Inc. | Circuit and method for reading a memory cell |
| JP2000057772A (ja) | 1998-08-12 | 2000-02-25 | Nec Corp | 半導体記憶装置 |
| JP2000187985A (ja) | 1998-12-24 | 2000-07-04 | Hitachi Ltd | 半導体記憶装置 |
| US6157578A (en) * | 1999-07-15 | 2000-12-05 | Stmicroelectronics, Inc. | Method and apparatus for accessing a memory device |
| JP2001351383A (ja) * | 2000-06-07 | 2001-12-21 | Mitsubishi Electric Corp | 半導体集積回路装置 |
| KR100393224B1 (ko) * | 2001-06-30 | 2003-07-31 | 삼성전자주식회사 | 비트라인 쌍들의 부하를 차단하는 회로를 구비하는 반도체메모리장치 |
| US6757202B2 (en) * | 2002-08-29 | 2004-06-29 | Micron Technology, Inc. | Bias sensing in DRAM sense amplifiers |
| US6862208B2 (en) * | 2003-04-11 | 2005-03-01 | Freescale Semiconductor, Inc. | Memory device with sense amplifier and self-timed latch |
-
2002
- 2002-08-29 US US10/233,871 patent/US6757202B2/en not_active Expired - Lifetime
-
2003
- 2003-08-26 EP EP10185622.7A patent/EP2309513B1/en not_active Expired - Lifetime
- 2003-08-26 JP JP2004531500A patent/JP2005536827A/ja active Pending
- 2003-08-26 KR KR1020087020886A patent/KR100939054B1/ko not_active Expired - Lifetime
- 2003-08-26 AU AU2003260089A patent/AU2003260089A1/en not_active Abandoned
- 2003-08-26 CN CN038226332A patent/CN1685438B/zh not_active Expired - Lifetime
- 2003-08-26 SG SG200701489-7A patent/SG153662A1/en unknown
- 2003-08-26 WO PCT/US2003/026736 patent/WO2004021354A1/en not_active Ceased
- 2003-08-26 KR KR1020057003148A patent/KR100976830B1/ko not_active Expired - Lifetime
- 2003-08-26 EP EP03791803.4A patent/EP1540655B1/en not_active Expired - Lifetime
- 2003-08-29 TW TW092123964A patent/TWI311319B/zh not_active IP Right Cessation
-
2004
- 2004-06-23 US US10/874,995 patent/US7072235B2/en not_active Expired - Lifetime
-
2006
- 2006-06-13 US US11/452,783 patent/US7567477B2/en not_active Expired - Lifetime
-
2009
- 2009-07-07 US US12/498,541 patent/US7903488B2/en not_active Expired - Lifetime
- 2009-08-11 JP JP2009186921A patent/JP2009301700A/ja active Pending
-
2011
- 2011-03-02 US US13/039,169 patent/US8767496B2/en not_active Expired - Lifetime
-
2014
- 2014-06-26 US US14/316,368 patent/US9633714B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0177776B1 (ko) * | 1995-08-23 | 1999-04-15 | 김광호 | 고집적 반도체 메모리 장치의 데이타 센싱회로 |
| US20020009008A1 (en) | 2000-06-26 | 2002-01-24 | Stmicroelectronics S.A. | Process for controlling a read access for a dynamic random access memory and corresponding memory |
| US20020080664A1 (en) | 2000-12-25 | 2002-06-27 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| EP1540655B1 (en) | 2019-07-03 |
| US20040042276A1 (en) | 2004-03-04 |
| JP2005536827A (ja) | 2005-12-02 |
| US20090323448A1 (en) | 2009-12-31 |
| US20040228195A1 (en) | 2004-11-18 |
| KR20080083215A (ko) | 2008-09-16 |
| US6757202B2 (en) | 2004-06-29 |
| EP2309513B1 (en) | 2019-07-10 |
| EP2309513A2 (en) | 2011-04-13 |
| US7903488B2 (en) | 2011-03-08 |
| AU2003260089A1 (en) | 2004-03-19 |
| TWI311319B (en) | 2009-06-21 |
| US9633714B2 (en) | 2017-04-25 |
| EP1540655A1 (en) | 2005-06-15 |
| TW200426836A (en) | 2004-12-01 |
| US20110157962A1 (en) | 2011-06-30 |
| US20140307516A1 (en) | 2014-10-16 |
| EP2309513A3 (en) | 2011-05-25 |
| US8767496B2 (en) | 2014-07-01 |
| KR100939054B1 (ko) | 2010-01-28 |
| KR20070089894A (ko) | 2007-09-04 |
| US20060280011A1 (en) | 2006-12-14 |
| US7072235B2 (en) | 2006-07-04 |
| JP2009301700A (ja) | 2009-12-24 |
| WO2004021354A1 (en) | 2004-03-11 |
| SG153662A1 (en) | 2009-07-29 |
| CN1685438A (zh) | 2005-10-19 |
| CN1685438B (zh) | 2011-11-16 |
| US7567477B2 (en) | 2009-07-28 |
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