KR100880746B1 - 플라즈마 에칭 방법, 플라즈마 에칭 장치, 컴퓨터 기억매체 및 처리 레시피가 기억된 기억 매체 - Google Patents

플라즈마 에칭 방법, 플라즈마 에칭 장치, 컴퓨터 기억매체 및 처리 레시피가 기억된 기억 매체 Download PDF

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Publication number
KR100880746B1
KR100880746B1 KR1020070030488A KR20070030488A KR100880746B1 KR 100880746 B1 KR100880746 B1 KR 100880746B1 KR 1020070030488 A KR1020070030488 A KR 1020070030488A KR 20070030488 A KR20070030488 A KR 20070030488A KR 100880746 B1 KR100880746 B1 KR 100880746B1
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KR
South Korea
Prior art keywords
etching
plasma etching
plasma
point metal
melting point
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KR1020070030488A
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English (en)
Korean (ko)
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KR20070098614A (ko
Inventor
모토키 후지나가
Original Assignee
도쿄엘렉트론가부시키가이샤
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Application filed by 도쿄엘렉트론가부시키가이샤 filed Critical 도쿄엘렉트론가부시키가이샤
Publication of KR20070098614A publication Critical patent/KR20070098614A/ko
Application granted granted Critical
Publication of KR100880746B1 publication Critical patent/KR100880746B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67017—Apparatus for fluid treatment
    • H01L21/67063—Apparatus for fluid treatment for etching
    • H01L21/67069—Apparatus for fluid treatment for etching for drying etching

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
KR1020070030488A 2006-03-29 2007-03-28 플라즈마 에칭 방법, 플라즈마 에칭 장치, 컴퓨터 기억매체 및 처리 레시피가 기억된 기억 매체 KR100880746B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2006-00091721 2006-03-29
JP2006091721A JP2007266466A (ja) 2006-03-29 2006-03-29 プラズマエッチング方法、プラズマエッチング装置、コンピュータ記憶媒体及び処理レシピが記憶された記憶媒体

Publications (2)

Publication Number Publication Date
KR20070098614A KR20070098614A (ko) 2007-10-05
KR100880746B1 true KR100880746B1 (ko) 2009-02-02

Family

ID=38639133

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070030488A KR100880746B1 (ko) 2006-03-29 2007-03-28 플라즈마 에칭 방법, 플라즈마 에칭 장치, 컴퓨터 기억매체 및 처리 레시피가 기억된 기억 매체

Country Status (4)

Country Link
JP (1) JP2007266466A (ja)
KR (1) KR100880746B1 (ja)
CN (1) CN100492603C (ja)
TW (1) TW200809957A (ja)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5264834B2 (ja) 2010-06-29 2013-08-14 東京エレクトロン株式会社 エッチング方法及び装置、半導体装置の製造方法
JP5638405B2 (ja) * 2010-10-08 2014-12-10 パナソニック株式会社 基板のプラズマ処理方法
JP5766027B2 (ja) * 2011-05-20 2015-08-19 富士フイルム株式会社 ドライエッチング方法及びデバイス製造方法
KR20140039863A (ko) * 2012-09-25 2014-04-02 삼성디스플레이 주식회사 다결정 규소막 형성 방법, 다결정 규소막을 포함하는 박막 트랜지스터 및 표시 장치
JP7166950B2 (ja) * 2019-02-07 2022-11-08 キオクシア株式会社 半導体製造装置および半導体装置の製造方法
CN116598200B (zh) * 2023-07-18 2023-09-26 江苏鲁汶仪器股份有限公司 一种Mo基金属薄膜的刻蚀方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0170412B1 (ko) * 1991-05-29 1999-03-30 이노우에 아키라 드라이 에칭방법
KR100270249B1 (ko) 1996-02-16 2000-10-16 가네꼬 히사시 에칭속도,이방성,및실리콘산화물에대한선택비가개선된고융점금속층을패터닝하기위한건식에칭방법
JP2004134521A (ja) 2002-10-09 2004-04-30 Rohm Co Ltd 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3565127B2 (ja) * 2000-02-25 2004-09-15 松下電器産業株式会社 エッチング方法
JP4702983B2 (ja) * 2000-07-11 2011-06-15 アプライド マテリアルズ インコーポレイテッド タングステン／ポリシリコンゲートのエッチング方法
JP2004031409A (ja) * 2002-06-21 2004-01-29 Sanyo Electric Co Ltd 薄膜トランジスタの製造方法
JP3872069B2 (ja) * 2004-04-07 2007-01-24 エルピーダメモリ株式会社 半導体装置の製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0170412B1 (ko) * 1991-05-29 1999-03-30 이노우에 아키라 드라이 에칭방법
KR100270249B1 (ko) 1996-02-16 2000-10-16 가네꼬 히사시 에칭속도,이방성,및실리콘산화물에대한선택비가개선된고융점금속층을패터닝하기위한건식에칭방법
JP2004134521A (ja) 2002-10-09 2004-04-30 Rohm Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
CN100492603C (zh) 2009-05-27
JP2007266466A (ja) 2007-10-11
CN101047127A (zh) 2007-10-03
TW200809957A (en) 2008-02-16
KR20070098614A (ko) 2007-10-05

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