KR100489599B1 - 반도체 장치의 제조 방법 - Google Patents
반도체 장치의 제조 방법 Download PDFInfo
- Publication number
- KR100489599B1 KR100489599B1 KR10-2002-0036178A KR20020036178A KR100489599B1 KR 100489599 B1 KR100489599 B1 KR 100489599B1 KR 20020036178 A KR20020036178 A KR 20020036178A KR 100489599 B1 KR100489599 B1 KR 100489599B1
- Authority
- KR
- South Korea
- Prior art keywords
- etching
- semiconductor device
- overetching
- gas
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JPJP-P-2001-00351652 | 2001-11-16 | ||
| JP2001351652A JP3760843B2 (ja) | 2001-11-16 | 2001-11-16 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20030040008A KR20030040008A (ko) | 2003-05-22 |
| KR100489599B1 true KR100489599B1 (ko) | 2005-05-16 |
Family
ID=19163934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-2002-0036178A Expired - Fee Related KR100489599B1 (ko) | 2001-11-16 | 2002-06-27 | 반도체 장치의 제조 방법 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6651678B2 (enExample) |
| JP (1) | JP3760843B2 (enExample) |
| KR (1) | KR100489599B1 (enExample) |
| TW (1) | TW541618B (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230122198A (ko) | 2022-02-14 | 2023-08-22 | 경남정보대학교 산학협력단 | 일회용 샤워타월 키트 |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004134521A (ja) | 2002-10-09 | 2004-04-30 | Rohm Co Ltd | 半導体装置の製造方法 |
| US7208424B2 (en) * | 2004-09-17 | 2007-04-24 | Freescale Semiconductor, Inc. | Method of forming a semiconductor device having a metal layer |
| JP4672318B2 (ja) * | 2004-09-22 | 2011-04-20 | 東京エレクトロン株式会社 | エッチング方法 |
| JP2008010692A (ja) * | 2006-06-30 | 2008-01-17 | Hitachi High-Technologies Corp | ドライエッチング方法 |
| CN100461433C (zh) * | 2007-01-04 | 2009-02-11 | 北京京东方光电科技有限公司 | 一种tft阵列结构及其制造方法 |
| JP5500876B2 (ja) * | 2009-06-08 | 2014-05-21 | キヤノン株式会社 | 光電変換装置の製造方法 |
| JP5633588B2 (ja) * | 2013-02-25 | 2014-12-03 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
| JP7220603B2 (ja) * | 2019-03-20 | 2023-02-10 | 東京エレクトロン株式会社 | 膜をエッチングする方法及びプラズマ処理装置 |
| WO2025204138A1 (ja) * | 2024-03-25 | 2025-10-02 | 東京エレクトロン株式会社 | エッチング方法及びプラズマ処理システム |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990065807A (ko) * | 1998-01-16 | 1999-08-05 | 로버트 에이치. 씨. 챠오. | 식각 향상 방법 |
| KR20010019642A (ko) * | 1999-08-28 | 2001-03-15 | 윤종용 | 폴리실리콘 게이트의 식각 방법 |
| US6277716B1 (en) * | 1999-10-25 | 2001-08-21 | Chartered Semiconductor Manufacturing Ltd. | Method of reduce gate oxide damage by using a multi-step etch process with a predictable premature endpoint system |
| KR20020035992A (ko) * | 2000-11-07 | 2002-05-16 | 박종섭 | 반도체장치의 제조방법 |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06216069A (ja) * | 1993-01-13 | 1994-08-05 | Hitachi Ltd | エッチング方法及び装置 |
| JPH06232091A (ja) * | 1993-02-03 | 1994-08-19 | Nippon Telegr & Teleph Corp <Ntt> | シリコン層の異方性加工方法 |
| JP2822952B2 (ja) * | 1995-08-30 | 1998-11-11 | 日本電気株式会社 | 半導体装置の製造方法 |
| US6037266A (en) * | 1998-09-28 | 2000-03-14 | Taiwan Semiconductor Manufacturing Company | Method for patterning a polysilicon gate with a thin gate oxide in a polysilicon etcher |
| US6387820B1 (en) * | 2000-09-19 | 2002-05-14 | Advanced Micro Devices, Inc. | BC13/AR chemistry for metal overetching on a high density plasma etcher |
| US6559062B1 (en) * | 2000-11-15 | 2003-05-06 | Agere Systems, Inc. | Method for avoiding notching in a semiconductor interconnect during a metal etching step |
| US6551941B2 (en) * | 2001-02-22 | 2003-04-22 | Applied Materials, Inc. | Method of forming a notched silicon-containing gate structure |
| JP4498662B2 (ja) * | 2001-06-15 | 2010-07-07 | 東京エレクトロン株式会社 | ドライエッチング方法 |
-
2001
- 2001-11-16 JP JP2001351652A patent/JP3760843B2/ja not_active Expired - Fee Related
-
2002
- 2002-04-12 TW TW091107414A patent/TW541618B/zh not_active IP Right Cessation
- 2002-04-18 US US10/124,729 patent/US6651678B2/en not_active Expired - Fee Related
- 2002-06-27 KR KR10-2002-0036178A patent/KR100489599B1/ko not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR19990065807A (ko) * | 1998-01-16 | 1999-08-05 | 로버트 에이치. 씨. 챠오. | 식각 향상 방법 |
| KR20010019642A (ko) * | 1999-08-28 | 2001-03-15 | 윤종용 | 폴리실리콘 게이트의 식각 방법 |
| US6277716B1 (en) * | 1999-10-25 | 2001-08-21 | Chartered Semiconductor Manufacturing Ltd. | Method of reduce gate oxide damage by using a multi-step etch process with a predictable premature endpoint system |
| KR20020035992A (ko) * | 2000-11-07 | 2002-05-16 | 박종섭 | 반도체장치의 제조방법 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20230122198A (ko) | 2022-02-14 | 2023-08-22 | 경남정보대학교 산학협력단 | 일회용 샤워타월 키트 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003151954A (ja) | 2003-05-23 |
| KR20030040008A (ko) | 2003-05-22 |
| JP3760843B2 (ja) | 2006-03-29 |
| TW541618B (en) | 2003-07-11 |
| US20030096505A1 (en) | 2003-05-22 |
| US6651678B2 (en) | 2003-11-25 |
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Legal Events
| Date | Code | Title | Description |
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| A201 | Request for examination | ||
| PA0109 | Patent application |
St.27 status event code: A-0-1-A10-A12-nap-PA0109 |
|
| PA0201 | Request for examination |
St.27 status event code: A-1-2-D10-D11-exm-PA0201 |
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| PG1501 | Laying open of application |
St.27 status event code: A-1-1-Q10-Q12-nap-PG1501 |
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| E701 | Decision to grant or registration of patent right | ||
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| GRNT | Written decision to grant | ||
| PR0701 | Registration of establishment |
St.27 status event code: A-2-4-F10-F11-exm-PR0701 |
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| PR1002 | Payment of registration fee |
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| FPAY | Annual fee payment |
Payment date: 20080425 Year of fee payment: 4 |
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