KR100469913B1 - 반도체소자의 제조방법 - Google Patents
반도체소자의 제조방법 Download PDFInfo
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- KR100469913B1 KR100469913B1 KR10-2003-0020765A KR20030020765A KR100469913B1 KR 100469913 B1 KR100469913 B1 KR 100469913B1 KR 20030020765 A KR20030020765 A KR 20030020765A KR 100469913 B1 KR100469913 B1 KR 100469913B1
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- Prior art keywords
- nitride film
- pattern
- oxide film
- metal layer
- film
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
Claims (6)
- 반도체기판상에 게이트산화막과 다결정실리콘층 및 제1질화막을 순차적으로 형성하는 공정과,상기 제1질화막과 다결정실리콘층, 게이트산화막 및 소정두께의 반도체기판을 소자분리 마스크를 이용하여 순차적으로 식각하여 게이트산화막 패턴과, 다결정실리콘층 패턴과 제1질화막 패턴 및 트랜치를 형성하는 공정과,상기 구조의 전표면에 소자분리용 산화막을 증착한 후, 상기 제1질화막 패턴이 노출되도록 평탄화 식각하여 소자분리 산화막으로 분리시키는 공정과,상기 반도체기판의 예정되어있는 부분에 p웰과 n웰을 형성하는 공정과,상기 제1질화막 패턴을 제거하는 공정과,상기 소자분리 산화막을 소정두께 습식식각하여 리세스를 형성하는 공정과,상기 구조의 전표면에 상기 리세스 보다 얇은 두께의 제2질화막과 희생산화막을 순차적으로 형성하는 공정과,상기 희생산화막의 상부를 식각하여 상기 제2질화막을 노출시키는 희생산화막 패턴을 형성하는 공정과,상기 다결정실리콘층 패턴 상부의 제2질화막을 제거하는 공정과,상기 소자분리 산화막 상부의 희생산화막을 제거하여 소자분리 산화막의 상부에 제2질화막 패턴이 남도록하는 공정과,상기 구조의 전표면에 장벽금속층과 금속층 및 제3질화막을 순차적으로 형성하는 공정과,상기 제3질화막에서 제2질화막 패턴까지를 워드라인 마스크를 이용하여 순차적으로 식각하여 제3질화막 패턴, 장벽금속층 패턴, 금속층 패턴 및 제2질화막 패턴을 형성하고 패턴들의 측벽에 질화막 절연 스페이서를 형성하는 공정과,상기 제2질화막 패턴을 마스크로 노출되어있는 다결정실리콘층을 식각하여 제3질화막 패턴과 중첩되어있는 다결정실리콘층 패턴과 장벽금속층 패턴 및 금속층 패턴으로된 게이트전극을 형성하는 공정과,상기 다결정실리콘층 패턴의 측벽에 선택 산화막을 형성하는 공정을 구비하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 제1 질화막의 두께가 10~70nm 인 것을 특징으로하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 리세스는 다결정실리콘층 표면으로부터 20~100nm 의 깊이로 형성되며, 상기 제2 질화막의 두께는 10~90nm 인 것을 특징으로하는 반도체소자의 제조방법.
- 제 1 항에 있어서,상기 장벽금속층은 WN, TiN 및 TiSiN을 이루어지는 군에서 선택되는 하나의 물질로 형성하고, 상기 금속층은 W, Ti 실리사이드, W 실리사이드 및 Co 실리사이드로 이루어지는 군에서 선택되는 하나의 물질로 형성하는 것을 특징으로하는 반도체소자.
- MOS FET을 구비하는 반도체소자에 있어서,상기 MOS FET의 게이트 전극이 소자분리 산화막 위에서의 게이트 전극은 질화막 위에 장벽금속층, 그 위에 금속층, 그위에 절연막으로 구성되어 있고, 활성 영역상의 게이트 산화막 위에서의 게이트 전극은 폴리실리콘과 장벽금속층, 금속층 및 절연막으로 구성되어 있는 반도체소자.
- 제 5 항에 있어서,상기 장벽금속층은 WN, TiN 및 TiSiN을 이루어지는 군에서 선택되는 하나의 물질로 형성하고, 상기 금속층은 W, Ti 실리사이드, W 실리사이드 및 Co 실리사이드로 이루어지는 군에서 선택되는 하나의 물질로 형성하는 것을 특징으로하는 반도체소자.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2003-0020765A KR100469913B1 (ko) | 2003-04-02 | 2003-04-02 | 반도체소자의 제조방법 |
US10/734,227 US6964904B2 (en) | 2003-04-02 | 2003-12-15 | Semiconductor device and method for manufacturing the same |
JP2003435028A JP2004311952A (ja) | 2003-04-02 | 2003-12-26 | 半導体素子及びその製造方法 |
US11/219,795 US7365400B2 (en) | 2003-04-02 | 2005-09-07 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR10-2003-0020765A KR100469913B1 (ko) | 2003-04-02 | 2003-04-02 | 반도체소자의 제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR20040085912A KR20040085912A (ko) | 2004-10-08 |
KR100469913B1 true KR100469913B1 (ko) | 2005-02-02 |
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KR10-2003-0020765A KR100469913B1 (ko) | 2003-04-02 | 2003-04-02 | 반도체소자의 제조방법 |
Country Status (3)
Country | Link |
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US (2) | US6964904B2 (ko) |
JP (1) | JP2004311952A (ko) |
KR (1) | KR100469913B1 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7425489B1 (en) * | 2004-11-19 | 2008-09-16 | Cypress Semiconductor Corporation | Self-aligned shallow trench isolation |
KR100709437B1 (ko) * | 2005-04-01 | 2007-04-18 | 주식회사 하이닉스반도체 | 반도체 소자 |
KR100800647B1 (ko) * | 2006-08-29 | 2008-02-01 | 동부일렉트로닉스 주식회사 | 반도체 소자의 게이트 전극 형성 방법 |
JP4106072B1 (ja) * | 2006-12-18 | 2008-06-25 | 松下電器産業株式会社 | 光ピックアップ装置 |
CN101157520B (zh) * | 2007-09-20 | 2010-08-11 | 上海交通大学 | 同时具有微米纳米结构的复合图形的构建方法 |
KR100909633B1 (ko) * | 2007-12-20 | 2009-07-27 | 주식회사 하이닉스반도체 | 반도체소자의 랜딩 플러그 콘택 형성방법 |
KR101010482B1 (ko) * | 2008-06-26 | 2011-01-21 | 주식회사 동부하이텍 | 반도체 소자의 제조방법 및 반도체 소자 |
KR101738894B1 (ko) | 2010-11-04 | 2017-05-24 | 삼성전자 주식회사 | 게이트 형성 방법 및 이를 이용한 반도체 소자의 제조 방법 |
CN103137672A (zh) * | 2011-11-25 | 2013-06-05 | 上海华虹Nec电子有限公司 | 兼容自对准孔和表面沟道的金-氧-半场效应管的栅极膜结构及其制造方法 |
US20140001576A1 (en) * | 2012-06-27 | 2014-01-02 | Applied Materials, Inc. | Lowering tungsten resistivity by replacing titanium nitride with titanium silicon nitride |
US8878242B1 (en) * | 2013-07-08 | 2014-11-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pickup device structure within a device isolation region |
TWI778118B (zh) * | 2017-09-05 | 2022-09-21 | 美商應用材料股份有限公司 | 來自次氧化物的自對準結構 |
Family Cites Families (8)
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US2002A (en) * | 1841-03-12 | Tor and planter for plowing | ||
US2004A (en) * | 1841-03-12 | Improvement in the manner of constructing and propelling steam-vessels | ||
JP3313024B2 (ja) * | 1996-05-27 | 2002-08-12 | 三菱電機株式会社 | トレンチ分離構造の最適化方法 |
US5963818A (en) * | 1997-09-17 | 1999-10-05 | Motorola, Inc | Combined trench isolation and inlaid process for integrated circuit formation |
US6326263B1 (en) * | 2000-08-11 | 2001-12-04 | United Microelectronics Corp. | Method of fabricating a flash memory cell |
KR100343146B1 (ko) * | 2000-11-02 | 2002-07-05 | 윤종용 | 다마신 구조의 게이트 전극이 형성된 반도체 소자 및 그의형성방법 |
KR100650467B1 (ko) * | 2001-03-12 | 2006-11-28 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 집적 회로 장치 및 그 제조 방법 |
US6645798B2 (en) * | 2001-06-22 | 2003-11-11 | Micron Technology, Inc. | Metal gate engineering for surface p-channel devices |
-
2003
- 2003-04-02 KR KR10-2003-0020765A patent/KR100469913B1/ko active IP Right Grant
- 2003-12-15 US US10/734,227 patent/US6964904B2/en not_active Expired - Lifetime
- 2003-12-26 JP JP2003435028A patent/JP2004311952A/ja active Pending
-
2005
- 2005-09-07 US US11/219,795 patent/US7365400B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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JP2004311952A (ja) | 2004-11-04 |
US7365400B2 (en) | 2008-04-29 |
US20060001112A1 (en) | 2006-01-05 |
US6964904B2 (en) | 2005-11-15 |
US20040195635A1 (en) | 2004-10-07 |
KR20040085912A (ko) | 2004-10-08 |
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