KR100368504B1 - 반도체장치제조방법 - Google Patents

반도체장치제조방법 Download PDF

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Publication number
KR100368504B1
KR100368504B1 KR1019950007691A KR19950007691A KR100368504B1 KR 100368504 B1 KR100368504 B1 KR 100368504B1 KR 1019950007691 A KR1019950007691 A KR 1019950007691A KR 19950007691 A KR19950007691 A KR 19950007691A KR 100368504 B1 KR100368504 B1 KR 100368504B1
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KR
South Korea
Prior art keywords
copper
layer
silicon nitride
silicide layer
semiconductor device
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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KR1019950007691A
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English (en)
Korean (ko)
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KR950034530A (ko
Inventor
스탠리피리피아크
아브제리노스게라토스
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모토로라 인코포레이티드
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Publication of KR950034530A publication Critical patent/KR950034530A/ko
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Publication of KR100368504B1 publication Critical patent/KR100368504B1/ko
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/055—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by formation methods other than physical vapour deposition [PVD], chemical vapour deposition [CVD] or liquid deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/064—Manufacture or treatment of conductive parts of the interconnections by modifying the conductivity of conductive parts, e.g. by alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019950007691A 1994-04-01 1995-03-31 반도체장치제조방법 Expired - Lifetime KR100368504B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US222,759 1994-04-01
US08/222,759 US5447887A (en) 1994-04-01 1994-04-01 Method for capping copper in semiconductor devices

Publications (2)

Publication Number Publication Date
KR950034530A KR950034530A (ko) 1995-12-28
KR100368504B1 true KR100368504B1 (ko) 2003-04-03

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950007691A Expired - Lifetime KR100368504B1 (ko) 1994-04-01 1995-03-31 반도체장치제조방법

Country Status (3)

Country Link
US (1) US5447887A (enExample)
KR (1) KR100368504B1 (enExample)
TW (1) TW269046B (enExample)

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* Cited by examiner, † Cited by third party
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